Abstract: A configurable register method and structure included configuration logic to form a register value. A data bridge system, for connecting an interface of a computer system to a plurality of application-specific integrated circuits (ASIC), has a data bridge operatively coupled between the computer interface and the plurality of ASICs that employs the configurable registers. The data bridge has a read only memory for storing at least the initial values and mask values for each ASIC of the plurality of ASICs. The data bridge upon initialization forms base address registers and other configuration data that are queried by the computer system. When the ASICs are graphic processors, the initial values and the mask values stored in the read only memory define the base address registers in the data bridge as a function of the configuration requirements of the graphic processors. The base address registers are thus programmable as a function of the initial values and mask values in the read only memory.

Abstract: A memory map evaluation tool is provided which allows a program to be organised in a manner most compatible with use of a cache. This is done by executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract: An interleaver which is applied to an encoding apparatus and/or a decoding apparatus in a data transmission/reception system comprises two banks of single-port RAM, and a control unit for controlling writing and reading of data to and from the two banks of RAM. The interleaver controls writing and reading of data to and from the two banks of RAM with the control unit such that the input data, wherein permuting from the input data into the output data is symmetrical, and which is at an arbitrary position wherein, with regard to an integer i which is 2 or greater and integers j and k which are 0 or greater but less than i, the residue from division by i is j, is output as the output data at a position wherein the residue from division by i is k. Accordingly, consecutive interleaving processing can be realized with a small circuit size.

Abstract: In a data recording and reproducing method, data blocks are recorded in a storage unit. Priority levels each for one of the data blocks are set and stored. It is determined whether or not a vacant area of the storage unit is expected to be short. When the vacant area of the storage unit is expected to be short. The data blocks recorded in the storage unit are recompressed in accordance with the stored priority levels.

Abstract: A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.

Abstract: A system for processing data includes a first set of cache memory and a second set of cache memory that are each coupled to a main memory. A compute engine coupled to the first set of cache memory transfers data from a communications medium into the first set of cache memory. The system transfers the data from the first set of cache memory to the second set of cache memory, in response to a request for the data from a compute engine coupled to the second set of cache memory. Data is transferred between the sets of cache memory without accessing main memory, regardless of whether the data has been modified. The data is also transferred directly between sets of cache memory when the data is exclusively owned by a set of cache memory or shared by sets of cache memory.

Abstract: A method for reducing power consumption within a processing architecture, the processing architecture including a processor and a memory device, the memory device having a memory cell, the processor having a processing element, the processor configured to read from the memory device and write to the memory device is described. The method comprises configuring the memory with logical processing circuits internal to the memory device which access the memory cell, performing logical operations to data within the memory cell utilizing the logical processing circuits within the memory device, and performing mathematical operations within the processing element of the processor. The method is embodied through a logic memory which significantly reduces power consumption of digital signal processors, microprocessors, micro-controllers or other computation engines in electronic systems.

Abstract: In response to determining a requested line of data is not stored within a local memory, the requested line of data is written to the local memory from a remote memory. Additionally, a victim page is selected in the local memory in response to the requested line of data not being in the local memory and it is determined whether one or more lines of the victim page are dirty. Furthermore, the one or more dirty lines are written to the remote memory in response to determining that the one or more lines are dirty and the requested line of data is fetched from the remote memory. Moreover, the requested line of data is stored within the page of data at a location previously occupied by the victim page.

Abstract: Data are prefetched into a cache from a prefetch region of memory, based on a program instruction reference and on compile-time information that indicates the bounds of the prefetch region, a size of a prefetch block, and a location of the prefetch block. If the program reference address lies with the prefetch region, an offset distance is used to determine the address of the prefetch block. Prefetching is performed either from a continuous one-dimensional prefetch region, or an embedded multi-dimensional prefetch region. The prefetch block address is respectively determined in one dimension or multiple dimensions. Program-directed prefetching is implemented by a media processor or by a separate processing component in communication with the media processor. The primary components include a program-directed prefetch controller, a cache, a function unit, and a memory. Preferably, region registers store the compile-time information, and the prefetched data are stored in a cache prefetch buffer.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache. In both embodiments, communications with main memory and power consumption are reduced.

Abstract: A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding block of data. Entries in the history cache are used to index into a pattern memory containing coherence predictions.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.

Abstract: A method includes determining at least one queue parameter for a process running on a system and configuring one or more queues on a storage device in accordance with at least one queue parameter.

Abstract: A digital signal processor includes a programmable memory, a processor and an access controller. The programmable memory has blocks each of which is capable of reading and writing an instruction of a program. The processor sequentially executes the instruction stored in the programmable memory. The access controller sequentially stores the instruction of the program in the blocks of the programmable memory on the basis of an address indicating a location of the respective blocks where the instruction is stored. The access controller controls an access of the processor to the respective blocks.

Abstract: Techniques are described for providing a memory challenge and response to allow access to a protected memory area of a semiconductor memory or to authenticate the data written therein. These techniques may be combined with known cryptographic approaches. Further data stored in the protected areas may include mediametric values to further enhance security.

Abstract: A method is provided for managing memory resources in a service gateway environment. The method includes: receiving a service request, the service request having an associated memory space requirement that exceeds total available memory space associated with the gateway environment; determining a number of dependent service instances for each service instance; determining an accumulative memory space requirement for each service instance; identifying a subset of service instance whose memory space requirement exceeds the memory space requirement of the service request, the subset having a minimal number of the service instances; and performing a memory resource management operation in relation to the identified subset of service instances.

Abstract: The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

Abstract: An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.

Abstract: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the present invention includes flexible data typing, permutation, and type matching of operands. The flexible data typing, permutation and type matching of operands provides programming flexibility to support different filtering and DSP algorithms having different types of filter coefficients or data samples. A data typer and aligner within each signal processing unit within the ASSP supports flexible data typing, permutation and type matching of operands of the instruction set architecture.

Abstract: A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: The invention recasts the virtual register file frame calls to alias hazard detection in the hazard detect logic of the physical register file. By way of example, mapping to the stacked registers may be aliased with three sets of 32 registers rows, from 32 to 127, for data hazard calculations to decrease size implementation with minor performance decrease. The invention sacrifices occasional hazard detections—resulting in occasional pipeline stalls as a loss of processor performance—in order to remove the row-by-row dependencies on physical register size. The invention thus reduces the logic requirements associated with the “height” and “width” of the register file: “height” corresponds to the number of registers (e.g., 128), and “width” corresponds to the pipeline stages.

Abstract: A method for forwarding data within a pipeline of a pipelined data processor having a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. The result generated by each execution pipeline stage is selectively coupled to an operand input of one of the execution pipeline stages.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal “ADVANCE POINTER” from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.

Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.

Abstract: There is disclosed a method of starting up an information processing apparatus which is capable of introducing a variety of elements into an image that is displayed when the information processing apparatus is started up according to a boot sequence. A memory card comprises a flash memory for storing boot data to be executed according to a boot sequence of the information processing apparatus, and a CPU having a transmitting function to transmit the boot data from the flash memory to the information processing apparatus and a control function to manage data. The boot data comprises a startup image display program for displaying a startup image when the information processing apparatus is started up, or its startup image data.

Abstract: A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in.

Abstract: Disclosed is a single-chip microcomputer capable of facilitating debugging even in the case of including a plurality of CPUs. In the single-chip microcomputer 41 carrying two CPUs 41A and 41B, the CPU 42A is released from its reset condition by a power-on reset circuit 33 at power-on, while another CPU 42B is released from its reset condition through a CPU(B) reset register 44 in accordance with processing based on the control program of the CPU 42.

Abstract: A memory module storing therein boot codes, a core logic device capable of distinguishing such memory module from the other memory modules of the same module specification, and a method for realizing the boot codes from the memory module storing therein the boot codes are disclosed. All the memory modules are electrically connected to the core logic device via respective signal pins, but the memory module storing therein boot codes outputs an identifying signal different from the identifying signals outputted by the other memory modules in a booting process. Therefore, the core logic device can locate the memory module storing therein the boot codes, and the host device can accomplish the booting process by reading the boot codes from the specific memory module.

Abstract: A system and method of automating the management of public and private key pairs of a sender and recipient of electronic messages over a network and for retrieving public keys of senders or recipients from secured servers, local key rings, PKI server, or Certificate Authority without requiring client-side software or user maintenance.

Abstract: The present invention provides a computer implemented method for acquiring secure test result data. In one embodiment, the method comprises presenting a test to a test subject through a computer device. Raw test response data based on the subject's response to the presented test is received from the test subject. The raw data is processed to generate test result data. The test result data is encrypted to generate encrypted test result data. The encrypted test result data is made available to a user, but unencrypted raw test response and result data is not accessible. In this way, only users with access to the decryption method for decrypting the encrypted result data have practical access to test result and raw data received from the test subject.

Abstract: The present invention is to perform authentication to enable linkage among a plurality of different applications providing a service.

Abstract: A peripheral apparatus which can communicate with a server via a network has: user interface means for operating the peripheral apparatus; communicating means for performing a log-in to the server; information obtaining means for obtaining operating environment information of the log-in user from operating environment managing means of each user of the server when the user is authenticated by the server; user interface constructing means for constructing a user interface such as an operating picture plane or the like in accordance with the operating environment information of the user; program downloading means for, when execution of a predetermined program held by program information managing means of each user on the server is instructed by the user interface means, downloading the program whose execution has been instructed from the server; data managing means for holding the downloaded program; and program executing means for executing the downloaded program.

Abstract: A universal crypto-adaptor system is adapted for supporting one or more smartcard applications with a plurality of smart cards through a smart card reader. The system includes an API unit for providing implementations of API specification for said smartcard applications, and a universal smart card API for communicating with said API means and said smart card reader for handling smart card operations including file and data managements and cryptographic operations, wherein said universal smart card comprises at least a smartcard translator to retrieve and translate smart card data saved in said respective smart card into a plurality of logic partitions that are compatible with each of said smartcard applications of said API means.

Abstract: This invention concerns an optical storage medium which stores a public key infrastructure(PKI)-based private key and a digital certificate for certificate for certification and security used in electronic commerce, and a method and system for issuing the private key and digital certificate, as well as a method of using such an optical storage medium and system. The optical storage medium, such as a compact disk or digital video disk, provides for a digital signature and may be used in conjunction with a memorized password by the user. By providing an optical storage medium capable of storing large amounts of data, the user can employ the private key and digital certificate even though he or she is not familiar with a computer.

Abstract: The present invention provides a copy control technique using digital watermark information, which makes it possible to prevent a content from being erroneously subjected to a copy control process according to wrong copy control information at a content-to-content transition. Copy control information in the form of digital watermark information (WM) is embedded in a content to control copying of the content in accordance with the embedded copy control information. A content-to-content transition is detected by detecting a change in a content state such as a change in image luminance, or a change in copy control information associated with a content or is detected on the basis of a flag, a descriptor, or channel switching.

Abstract: Data application method enabling evaluations to be properly received while content is being protected, enabling content users to use only what they want to use in the amount they want to use it, and enabling advertising providers in certainty to have users use ads. The method includes: a step of converting first data for permitting use based on predetermined conditions, into encrypted first data by means of a predetermined encryption key; a step of generating watermarked second data in which the encryption key is embedded, as an invisible electronic watermark, into second data for permitting use unconditionally; and a step of compositing and distributing the encrypted first data and the watermarked second data.

Abstract: By a program process, CPU 31 embeds a watermark data into a waveform data stored in wave memory 41a. The program includes a step for detecting a characterizing part (attack part and loop part) of a waveform data that represents a waveform of a musical tone where the characterizing part represents characteristics of the musical tone, and a step for embedding a watermark data into a part of the waveform data excluding the detected characterizing part. Further, CPU 31 can also extract the watermark data by a program process including a step for detecting the characterizing part and a step for extracting the watermark data embedded in a part excluding the detected characterizing part. Thus, from waveform data including a watermark data, natural musical tones can be reproduced without deteriorating the characteristics of the musical tones at the time of reproduction.

Abstract: A user's usage of network resources is controlled, after the user has been authenticated, without using any network resources beyond the user's entry point to the network. Packet rules may be provisioned to the user's entry point to the network, and the packet rules may be applied to each packet received from the user before any network resources beyond the entry point are used. These packet rules may be associated with an identity of the user and then provisioned to the user's entry point in response to the user being authenticated. Usage of network resources of a communications network by a user beyond a network device of the communications network that serves as the user's entry point to the communications network is controlled. The port module of the network device is configured with one or more packet rules corresponding to an identity of the user.

Abstract: Techniques for managing access to digital assets via a designated place or its sub-places are disclosed. The designated place may be a file folder, a directory, a local or remote store. The designated place is characterized by or associated with a securing module that causes all files stored in the designated place to have substantially similar security. In other words, a file to be secured can be simply dropped into the designated place and the securing module is configured to take actions to secure the file transparently in accordance with the security characteristics of the designated place. Likewise, a designated place can be set up to unsecure the secured files being deposited in the designated place, provided a user of the secured files is permitted to do so.

Abstract: A method of authenticating a user of a security token which has confidential information accessible only in response to a predetermined access code, the method including capturing biometric information of the user, creating a user biometric profile from the captured biometric information, comparing the user biometric profile created from the captured biometric information with a plurality of a biometric profiles contained within a database containing the user biometric profile and other biometric profiles, each biometric profile in the database of biometric profiles having a unique associated code, selecting from the database of biometric profiles the biometric profile corresponding most closely to the user profile created from the captured biometric data, and providing the code associated with the selected biometric profile to the security token.

Abstract: A secure print system comprises a sending computer entity and a plurality of receiving entities, each capable of decrypting and printing a specified number of copies of a document. The sending computer entity and the plurality of receiving devices are each pre-registered with each other by means of unique device identification number, which is embedded in inaccessible hardware, firmware or software components at the point of manufacture, linking the sending computer entity and the plurality of receiving devices. The receiving devices, after decrypting a received message, print a specified number of copies only, before deleting the electronic data from which the document copies have been printed.

Abstract: The invention relates to a method and an arrangement for the manufacture of mask-programmed ROMs while utilizing a mask comprising a plurality of systems, as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for optimizing the protection against attacks by hackers by individualizing the ROM code masks during the manufacture of ROMs with security-relevant data.

Abstract: A data security device for data storage medium includes a USB mass storage class controller connected to an operation system, such as a personal computer, and a data protection device connecting the USB mass storage class controller to a data storage medium. The data security device may be incorporated in a USB-based data accessing device and can be activated by a user via the operation system. The data protection device includes a write protection unit which provides write protection to the data storage medium when data are to be written by the operation system to the data storage medium, an enciphering unit which enciphers data written into the data storage medium and a deciphering unit which deciphers the enciphered data stored in the data storage medium when the operation system retrieves data from the data storage medium.

Abstract: The invention relates to a device for access-protected processing of electronic data. The inventive device consists of an electronic data processing device, particularly a PC, with means of acquiring electronic data of a first electronic document and of retaining the data in an allocated volatile or permanent storage unit. The first electronic document has a predetermined document-specific data format involving a plurality of electronic streams linked by means of a tree, network, database and/or folder structure. By means of a display of the data processing device these streams can be read and displayed to the user as the first electronic document. At least one stream is suitable for having embedded and/or attached hidden data that cannot be discerned by the user when the display unit shows the document and can be retained, together with the first electronic document, in the storage unit.

Abstract: A system, method, and article of manufacture are provided for accurately tracking transactions involving software. First, a plurality of decryption keys are provided which each allow use of corresponding software. Next, a request is received for a decryption key from a requestor after which a transaction represented by the request for the decryption key is logged. The decryption key is then outputted to the requester. Thereafter, the transaction is reported for allowing the tracking of revenue generated by the sale of the software.

Abstract: An information recording medium includes a plurality of modulated data areas for recording a plurality of modulated codes; and a plurality of SYNC code areas for recording a plurality of SYNC codes. Data other than the plurality of modulated codes is recorded in at least one of the plurality of SYNC code areas in the form of at least one SYNC code.

Abstract: The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed.

Abstract: In a content distribution system, a recording-management system makes a storing section of a first terminal device store a predetermined content stored in a content-storing section of a distribution device obligatorily. Under this condition, when a second terminal device requests the recording management system to distribute the predetermined content, the recording management system transmits the address identifying the first terminal device that stores the predetermined content to the second terminal device. The content stored in the first terminal device is transmitted and received between the second terminal device and the first terminal device having the received address through a user network to obtain the predetermined content. Thus, the content requested by a given terminal device can be distributed to the terminal device that has made the request without increasing the scale of the distribution device.