Patents Issued in October 14, 2003
  • Patent number: 6633474
    Abstract: The instantaneous tripping threshold of the selective tripping device is a decreasing function of a quantity representative of the time necessary for the current to reach the peak value. The variation curve is disposed between first and second curves, obtained experimentally, representative of envelopes of the peak current values. The first curve is obtained when the circuit breaker associated to the selective tripping device is alone and the second curve when it is connected in series with another circuit breaker connected down-line.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: October 14, 2003
    Assignee: Schneider Electric Industries SA
    Inventor: Dominique Boudaud
  • Patent number: 6633475
    Abstract: A low cost high side supply shut down circuit that operates to deactivate the power supply of a central supply, such as to pressure regulators, solenoid valves, etc., as parts of non-repairable electro-hydraulic transmission modules in the event of a malfunction, e.g. a low side driver circuit failure. The supply voltage is connected to the high side of a fuse. The load circuits receive power or no power depending on the operating condition of the fuse. Coupled across the fuse is a fuse trigger status detection circuit as part of a diagnostics and control module. The diagnostics and control module is connected to the input of a shut down low side output driver circuit. The attached low side loads have individual detection circuits that are coupled to the diagnostics and control module as well as their enable inputs.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 14, 2003
    Assignee: Robert Bosch Corporation
    Inventor: Karsten E. Thiele
  • Patent number: 6633476
    Abstract: The present invention relates to an apparatus comprising a watt-hour meter adapter housing having a substantially cylindrical outline with a translucent window into its interior, and having visible therewithin one or more lights connected between respective input power phases and ground. The invention also relates to a transient voltage surge suppression (TVSS) apparatus containing a TVSS means including varistors in a housing fitting in a plug-and-jack manner between a watt-hour meter and its customary socket in a utility box or panel, improved on-line TVSS status indication means comprising a translucent window in the housing, and an indicator light connected to show the status and visible through the window to an outside observer.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: October 14, 2003
    Assignee: Meter Treater, Inc.
    Inventor: Edward F. Allina
  • Patent number: 6633477
    Abstract: The object of the invention is to provide a conductive member capable of attenuating the noise having frequency components, for example, of the order of several GHz efficiently. Signal line 21 is formed by using the first conductive paste containing a silver powder, a ferrite powder, an organic binder, a dispersant, and a solvent.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: October 14, 2003
    Assignee: Koninklijke Philips Electronics N. V.
    Inventors: Kenichi Horie, Hiroyuki Ishida
  • Patent number: 6633478
    Abstract: A control circuit is provided for use in an electromagnetic device with a coil where the electromagnetic device is actuated with an actuating current and held in an operative condition by a holding current with the holding current being significantly lower in magnitude than the actuating current. The control circuit includes first and second transistors wherein, during a powered mode, the first transistor is disposed in an on state and the second transistor is disposed in an off state, and, during a shorted mode, the first transistor is disposed in an off state and the second transistor is disposed in an on state. Additionally, a power source selectively communicates with the coil, and during a first time interval, the power source communicates with the coil in the powered mode and, during a second time interval, the power source is disconnected from the coil in the shorted mode.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: October 14, 2003
    Assignee: Xerox Corporation
    Inventors: Michael A. Parisi, Judith L. Hannon
  • Patent number: 6633479
    Abstract: A portable, reusable apparatus for providing temporary electrical service is disclosed. The apparatus includes a support structure with at least one service line, a meter base, and a breaker box secured thereto. One or more electrical receptacles may also be secured to the support structure. The apparatus may be configured to alternately connect to overhead and underground power supplies. A remote power supply apparatus is also disclosed. The remote power supply apparatus includes an electrical cord that is connectable to temporary electrical service. Systems that include these apparatus and methods of using the apparatus are also disclosed.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: October 14, 2003
    Assignee: Robert Karl Benson, Inc.
    Inventor: Robert Karl Benson
  • Patent number: 6633480
    Abstract: An induction foil cap sealing system includes a ferrite core having a plurality of openings therethrough and a mounting plate with a plurality of openings therethrough which are aligned with the plurality of openings in the ferrite core. Air is directed to flow through the openings to draw heat away. A litz wire coil is disposed proximate to the ferrite core which produces an electromagnetic field within the ferrite core. The ferrite core and litz wire coil are adapted to direct the electromagnetic field toward abject to heat it.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: October 14, 2003
    Inventor: Kenneth J. Herzog
  • Patent number: 6633481
    Abstract: A system according to the invention for mounting multiple media drives includes a housing and multiple modules that are insertable into and removable from the housing. Each module is adapted to hold a media drive. Furthermore, the system includes a resilient layer disposed between the housing and the modules when the modules are inserted into the housing for attenuating shocks and vibrations. The resilient layer includes a slot for inhibiting transmission of shocks and vibrations between at least two of the modules.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: October 14, 2003
    Assignee: Storage Technology Corporation
    Inventor: Eric G. Pavol
  • Patent number: 6633482
    Abstract: A system for installing an interactive driver information system into an existing vehicle is disclosed. An off-the-shelf driver-to-vehicle interface device such as a PDA is received in a corresponding docking station. A custom adapter device mechanically and electrically receives the PDA components and enables a mechanical and electrical connection from the PDA components to the vehicle. The custom adapter device is configured in a variety of embodiments to interfit with a pre-existing cavity in the vehicle such as a cup holder, ashtray cavity, coin holder, or seam in the dashboard. The custom adapter device further provides an electrical connection from the PDA components to the power system of the vehicle and to an electronic on board controller. The PDA docking station may be structurally integrated with a microphone, a speaker, and a control panel of manually operable elements to be manipulated by a driver.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: October 14, 2003
    Assignee: Siemens VDO Automotive Corporation
    Inventor: Melvin A. Rode
  • Patent number: 6633483
    Abstract: The present invention relates to a portable information terminal apparatus including a stopper mechanism for operating in such a manner that, in a state in which a detachable built-in electronic device such as a memory card is inserted and attached to a connector arranged in the apparatus, when an external impact is applied, the memory card is prevented from being detached from the connector on the rear side of the memory card or, even when the card is detached, the detachment is restricted within a detachment allowable range where electrical connection is not influenced.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: October 14, 2003
    Assignee: Olympus Optical Co., Ltd.
    Inventors: Toshimasa Akagi, Akifumi Kabeya, Tatsuyuki Uemura, Takashi Suzuki, Hideki Okuyama
  • Patent number: 6633484
    Abstract: An enhanced heat dissipation system and a method to extract heat from an integrated circuit device include a thermally conductive core having upper and lower outer surface areas. The system further includes a first conductive ring having a first array of radially extending fins. The first conductive ring is thermally coupled to the upper outer surface area. The first array and the lower outer surface area of the thermally conductive core are of sufficient size to allow components on a motherboard to encroach around and onto the integrated circuit device when the heat dissipation device is mounted onto the integrated circuit device.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: October 14, 2003
    Assignee: Intel Corporation
    Inventors: Seri Lee, Lloyd L. Pollard, II
  • Patent number: 6633485
    Abstract: A snap-in heat sink assembly that has an injection molded one piece frame having a plurality of spring members extending outwardly with protrusions at the free ends thereof. The assembly has a spring located against the frame and an electronic component is located atop of the spring. A heat sink has lateral surfaces with elongated grooves formed along those lateral surfaces. The sink is affixed to the frame by a simple step of inserting the heat sink into the space between the spring members such that the protrusions of the spring members snap into the grooves when the heat sink is in the desired location. By sandwiching the spring between the frame and the electronic component, the spring creates a bias to force the electronic component against the heat sink to assure good conductivity of heat from the electronic component through the heat sink.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: October 14, 2003
    Assignee: Illinois Tool Works Inc.
    Inventors: Dennis R. Sigl, Richard Mark Achtner
  • Patent number: 6633486
    Abstract: A technique is provided for coupling and uncoupling modular devices with electronic and computing devices. A latch is coupled to a release member, which operates to release the latch from a mate latch by bending the release member to move the latch laterally away from the mate latch. The release member also may have grips for tool-lessly bending the release member to release the latch from the mate latch, and for removing the desired device. The technique also may embody a modular device having the latch and release member, or it may embody an overall system having the modular device disposed in a receptacle.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: October 14, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Henry C. Coles, Hector Vidales, Joseph R. Allen, Tri Nguyen
  • Patent number: 6633487
    Abstract: A required interlayer circuit board 1 is constituted so as to provide a punched portion in which only a collapsible cable portion 2 for connecting a plurality of component mounting portions to each other is exposed. An external layer board 6 is superimposed on at least one side of the internal layer circuit board 1 through an adhesive member 4 to which an opening portion 5 is formed at a position corresponding to the cable portion 2, the external layer substrate 6 having an opening portion 7 at a similar position. Thereafter, a wiring pattern for the component mounting portions is formed on the external layer board 6, and a blank and pierce process of the respective component mounting portions except the cable portion is carried out, thereby integrally connecting a plurality of the component mounting portions to each other through the collapsible cable portion.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: October 14, 2003
    Assignee: Nippon Mektron, Ltd.
    Inventors: Akihiko Toyoshima, Kunihiko Azeyanagi
  • Patent number: 6633488
    Abstract: A printed circuit board unit comprising a printed circuit board and a correction member. The correction member contacts the printed circuit board at a pair of contact points and support points arranged between the contact points. The support points are defined at a position withdrawing from a plane including the contact points. Screws serve to urge the printed circuit board against the correction member. The correction member is adapted to generate an intentional warp or bend. Such warp serves to correct or modify the curvature of the front surface of the printed circuit board. The front surface of the printed circuit board can be maintained flat.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Morita
  • Patent number: 6633489
    Abstract: The present invention relates to a method and apparatus that prevents/minimizes cracking in the ceramic body of processors. The ability to prevent/minimize cracking can ensure successful operation and substantially increase processor lifetime. The present invention discloses a device for maintaining a microprocessor in a desired relationship with a printed wiring board while limiting the transmission of shock and vibrational motion to and from the processor includes a printed wiring board, a processor, and a dynamic isolating mount compressed between the printed wiring board and the processor, wherein the processor maintains the dynamic isolating mount in a compressed state such that the dynamic isolating mount bears on the printed wiring board.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: October 14, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Daniel L. Callahan, Raymond J. Iannuzzelli
  • Patent number: 6633490
    Abstract: An electronic board assembly carrying connectors on each side of its lower edge which is adapted to withstand the relatively strong forces required to insert or remove the assembly, e.g., from a backplane board, and yet provide many electrical contacts along the interconnection sites. The electronic board assembly comprises two symmetrical elementary PCBs electrically coupled together, each carrying a connector on its external lower edge. In one embodiment, these two PCBs are coupled together by a flexible adhesive insulative layer and maintained by mechanical devices such that the distance between these two connectors is set to a predetermined distance (to align precisely with the backplane board). The mechanical device used to maintain a predetermined distance between the two connectors of the assembly may comprise a U-shaped member, the upper part of this member being strategically inserted between these connectors.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: October 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bruno Centola, Claude Gomez, Christian Ouazana
  • Patent number: 6633491
    Abstract: A method and apparatus to support varying sizes of memory cards against shock and vibration. One embodiment of the invention involves a method to assemble a support clip to one or more cards attached on a substrate by a connector. A second embodiment of the invention involves a method to fabricate a support clip. A third embodiment of the invention involves an assembled substrate with a plurality of cards secured by one or more support clips to the substrate.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: October 14, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christopher Gregory Malone, Stephan Karl Barsun, Thomas J. Augustin
  • Patent number: 6633492
    Abstract: A PCB package for shielding electromagnetic radiation from exiting or entering the package. In one embodiment the package includes first and second electrically conductive covers and first and second electrically conductive frames. The first frame electrically connected to the first cover and the second frame electrically connected to the second cover. The first frame is then electrically connected to the second frame. The first and second frames can be made of electrically conductive plastics or metals or any other electrically conductive materials. Methods of assembling the packages of the various embodiments are also set forth.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: October 14, 2003
    Assignee: Methode Electronics, Inc.
    Inventors: Ryan Kimura, James Farquhar, Jeffrey Allen, Michael Chao, Stephen Hatch, Scott Herbert, Brandt Weibezhan, Iggoni Fajardo
  • Patent number: 6633493
    Abstract: A power distribution system is described for supplying power to electronic assemblies, in particular for use in the field of deep ocean oil production. The electrical power is supplied from a voltage source via a supply cable to theprimary winding of a distribution transformer. A number of secondary windings, preferably four, are disposed in addition to the primary winding on the core of the distribution transformer. The windings on the common core are subdivided into a number n of winding packs corresponding to the number n of secondary windings, and with each winding pack containing an n-th part of the primary winding and one of the secondary windings. Electronic assemblies are each connected via a connecting cable to one of the secondary windings.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: October 14, 2003
    Assignee: ABB Patent GmbH
    Inventors: Lothar Heinemann, Jens Helfrich
  • Patent number: 6633494
    Abstract: A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: October 14, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Bob Roohparvar, Kevin Z. Mahouti, Karl Rapp
  • Patent number: 6633495
    Abstract: The voltage applied to a power converter is detected by a voltage detector, a function generator produces a voltage proportional to this detected voltage, and a high-pass filter detects an AC component superimposed on the voltage. An adder adds a bias voltage to this AC component, and an adder adds the output from the adder and the output from the function generator. The output from the adder is compared with a triangular wave produced from a rectangular wave generator, and a switching element is controlled to make switching operation according to the compared result. When a DC current is decreased by the AC component, a resistance current Ib is increased so that the AC components superimposed on the current and resistance current can be cancelled out.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Ishda, Toshiaki Okuyama, Tetsuo Kojima, Kiyoshi Nakata, Akira Horie
  • Patent number: 6633496
    Abstract: A memory array includes a first plurality of metal lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line. The memory also includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: October 14, 2003
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Eduardo Maayan, Boaz Eitan
  • Patent number: 6633497
    Abstract: A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and electrically conductive hard mask material on the memory element. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 14, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Janice H. Nickel
  • Patent number: 6633498
    Abstract: A magnetoresistive tunneling junction memory cell (10) including a pinned ferromagnetic region (17) having a magnetic moment vector (47) fixed in a preferred direction in the absence of an applied magnetic field wherein the pinned ferromagnetic region has a magnetic fringing field (96), an electrically insulating material positioned on the pinned ferromagnetic region to form a magnetoresistive tunneling junction (16), and a free ferromagnetic region (15) having a magnetic moment vector (53) oriented in a position parallel or anti-parallel to that of the pinned ferromagnetic region wherein the magnetic fringing field is chosen to obtain a desired switching field.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: October 14, 2003
    Assignee: Motorola, Inc.
    Inventors: Bradley N. Engel, Jason Allen Janesky, Nicholas D. Rizzo
  • Patent number: 6633499
    Abstract: A symmetric segmented array has select transistors and column select transistors. At least one of the select and/or column select transistors is a low threshold voltage device. Alternatively, at least one select transistor and/or column select transistor of the array has a channel length shorter than a standard channel length of a process.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: October 14, 2003
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Boaz Eitan, Eduardo Maayan
  • Patent number: 6633500
    Abstract: The present invention is related to methods and systems for refreshing non-volatile memories. A refresh token associated with a first wordline is located. A determination is made as to whether a first cell current for a first cell coupled to the first wordline is within a first range. At least partly in response to determining that the first cell current is within the first range, the first cell is refreshed.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: October 14, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hung Chou, Chia Hsing Chen
  • Patent number: 6633501
    Abstract: An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the access control circuits results in a blocking of the data output circuits.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: October 14, 2003
    Assignee: Infineon Technologies AG
    Inventor: Armin Wedel
  • Patent number: 6633502
    Abstract: A semiconductor device is provided with a memory, scan chains each comprising plural flip-flops, combination circuits which receive the outputs from the respective flip-flops in the scan chains, and a selector circuit which receives the outputs from the respective flip-flops and the outputs from the combinational circuits, selects test signals outputted from the flip-flops when the semiconductor device is in a test mode, and outputs the test signals to the memory, thereby to operate the memory. Therefore, stress can be reliably applied to the memory when a burn-in test is carried out.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: October 14, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tamaki Iwasaki
  • Patent number: 6633503
    Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: October 14, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Christopher K. Morzano
  • Patent number: 6633504
    Abstract: A synchronous DRAM and method are provided in which main cells and spare cells are accessed by an external address during automatic refresh of a test mode. In the synchronous DRAM, a mode register setting circuit receives an external signal in response to a plurality of control signals to generate a mode register setting signal, during an automatic refresh operation in a test mode. An address selector selects and outputs an external address to the memory cell array, in response to the activation of the mode register set signal, during the automatic refresh operation in the test mode. The address selector selects and outputs an internal address to the memory cell array, in response to the deactivation of the mode register set signal, during an automatic refresh operation in a normal mode. Therefore, the main cells and the spare cells in the memory cell array are sequentially accessed and refreshed by the external address during the automatic refresh operation in the test mode.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: October 14, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mahn-joong Lee, Man-sik Choi
  • Patent number: 6633505
    Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventor: Mitsuhiro Higashiho
  • Patent number: 6633506
    Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: October 14, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. Casper, Chris G. Martin
  • Patent number: 6633507
    Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: October 14, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Douglas J. Cutter, Fan Ho, Kurt D. Beigel
  • Patent number: 6633508
    Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: October 14, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
  • Patent number: 6633509
    Abstract: A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-array groups. All the associated sub-array groups are preferably selected during a read cycle to simultaneously read the various bits of the data set, but when writing the data set, a smaller number of sub-array groups are activated during each of several write cycles to simultaneously write only a portion of the data set. Consequently, the read bandwidth remains high and is driven by the number of bits simultaneously read, but the write power is reduced since during each write cycle fewer bits are written. Such a memory array is particularly advantageous with passive element memory cells, such as those having antifuses.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: October 14, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roy E. Scheuerlein, Matthew P. Crowley
  • Patent number: 6633510
    Abstract: A dual time piece having at least two clock faces thereon with each clock face having indicia thereon that enable the user to determine whether the time displayed by each time piece represents time before noon or time after noon.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: October 14, 2003
    Inventor: Alfred E. Hall
  • Patent number: 6633511
    Abstract: An inside notch (37) serving as an adjusting section is provided for a magnetic balancing adjustment between stators (31 and 32) and a rotor (12). The inside notch acts to reduce cogging torque, thereby allowing the rotor to rotate using a slight torque. Therefore, the rotor can be more readily started without using a complicated structure, can be prevented from easily stopping due to an external disturbance, and can be made more reliable. In reducing the cogging torque, it is not necessary to reduce the number of magnetic flux lines by, for example, making a rotor magnet (12b) smaller, making it possible to maintain the efficiency with which electrical power is produced.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: October 14, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Masatoshi Moteki, Hirokazu Sekino, Kinya Matsuzawa
  • Patent number: 6633512
    Abstract: The present invention provides an information storage apparatus which at least records information by applying a magnetic field to a recording medium with a smaller power consumption. A default value of a recording magnetic field is set to a minimum value of the apparatus. Through a learning process, the default value of the recording magnetic field is changed to a value in the vicinity of the minimum value.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventors: Shinya Kobayashi, Shigenori Yanagi
  • Patent number: 6633513
    Abstract: A magneto-optical head for magneto-optical writing and reading systems having an improved construction for a field modulating coil and a miniature objective lens, and a method of manufacturing the magneto-optical head.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 14, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-bae Kim, Byoung-chan Lee, Hyung-gae Shin, Cheol-sung Yeon, Sang-hun Lee, Jong-woo Shin
  • Patent number: 6633514
    Abstract: A magneto-optical recording medium has magneto-optical recording layers (11, 12, 13) and reproducing layers (21, 22, 23). The information recorded in the reproducing layers are reproduced by means of reproducing light beams (31, 32, 33) of different wavelengths, respectively. In reproduction, magnetic domains (4) recorded in the recording layers are transferred in the reproducing layers formed on the respective recording layers, the transferred magnetic domains (5) are enlarged with an external magnetic field, and the information is reproduced. Since information is recorded and reproduced for each recording layer, the recording density is improved. Further since the reproduction signals are amplified by the magnetic domain enlargement, the C/N is improved.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: October 14, 2003
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Hiroyuki Awano, Katsusuke Shimazaki, Hiroki Takao, Norio Ohta, Akiyoshi Itou, Katsuji Nakagawa
  • Patent number: 6633515
    Abstract: Audio-centered information is stored on a unitary storage medium through a Table-of-Contents (TOC) mechanism that specifies an actual configuration of various audio items. In particular, in addition to the TOC mechanism a file-based access mechanism is assigned to the audio-centered information by a higher level Audio file. At a next-lower level a mechanism is assigned separately as one or more track-wise organized files indicating exclusively audio items contained in the area, and separately therefrom a comprehensive file indicating audio tracks as well as interposed pause intervals.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: October 14, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Marcel S. E. Van Nieuwenhoven, Johannes J. Mons
  • Patent number: 6633516
    Abstract: Pieces of address information are recorded on an optical disc such that they are successively continuous addresses within each zone but discontinuous at a beginning of a zone next to the previous zone, and an address after repeating the addresses of the previous zone for two rounds becomes the forefront address of the zone next to the previous zone. Access to the land tracks is performed by returning to the first address position in a zone after the addresses of the groove tracks become the last address of the zone, and the access is performed by recognizing an address continued from the last address of the groove tracks suppositionally on the pieces of address information recorded on the groove tracks, and then the access is successively performed to move to the next zone after the addresses of the land tracks become the last address of the zone.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: October 14, 2003
    Assignee: Sony Corporation
    Inventors: Yasuo Tone, Hideo Tada
  • Patent number: 6633517
    Abstract: A connecting member connects a pair of holder plates toward the end of the holder plates at the recessed end in the direction in which the disk is inserted. By forming the holding member holding disks using three pieces, there is less deformation causes by high temperatures compared to integrally formed units. Also, since this connecting member only serves to connect the pair of holder plates, a thin rod-shaped connecting bar can be used. This allows the clearance between the disks held toward the back of the device and the rear panel to be minimized, thus contributing to a reduced depth dimension for the device.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: October 14, 2003
    Assignees: Mechanical Research Corporation, Alpine Electronics, Inc.
    Inventor: Niro Nakamichi
  • Patent number: 6633518
    Abstract: A disk recording and/or reproducing apparatus recording and/or reproducing information on and/or from anyone of a plurality of disk-like recording mediums. Freedom in design is improved by effectively utilizing spaces in which respective portions and mechanisms of the apparatus are disposed. In the apparatus, a first planet gear and second planet gear meshed with a racked portion are switched, whereby the disk tray is moveable between a loading position at which the disk tray is loaded into the apparatus and an eject position at which the disk tray is ejected to a location outside the apparatus body.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: October 14, 2003
    Assignee: Sony Corporation
    Inventor: Tsuyoshi Minote
  • Patent number: 6633519
    Abstract: An optical pick-up device includes: a yoke plate having yokes formed at a front side where a magnetic body and a magnetic driving coil are positioned to drive an objective lens; a frame molded to the yoke plate in such a manner that a portion of the rear side of the yoke plate is inserted thereinto; and a PCB with at least two portions fixed to the frame, for applying a drive signal to the magnetic driving unit. Since the frame is press-fit to the yoke plate and the PCB with several portions coated with the adhesive is fixedly attached to the frame, it is not necessary to use an engaging member such as a screw, so that its assembly can be improved and the frame and the PCB can be prevented from being shaken.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: October 14, 2003
    Assignee: LG Electronics Inc.
    Inventors: Hee Jin Park, In Woo Lee
  • Patent number: 6633520
    Abstract: A center error signal is used to control the sled during fine search operations. The center error signal is used to synchronize the motion of a tracking actuator and a sled. A head is mounted on a sled in a disk drive. The sled is positioned by a sled motor and the head is positionally mounted on the sled. The head includes a lens that is optically coupled to a photo-sensor on the head. A tracking actuator positions the lens with respect to a track on the disk. A center error signal indicates a position of the lens with respect to a track on a disk. A tracks-to-jump signal specifies a predetermined number of tracks on the disk that the sled motor is to move. A modified tracks-to-jump signal is produced in response to the center error signal. The sled motor is controlled with the modified tracks-to-jump signal.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: October 14, 2003
    Assignee: Oak Technology, Inc.
    Inventor: Hubert Song
  • Patent number: 6633521
    Abstract: The present invention relates to a storage device and a servo recovery method for the storage device, which restores the head to a track when the head goes off from the track of a storage medium, and whereby it prevents the servo recovery process from being continuously called over a short period of time. The storage device comprises a storage medium, a head and a control circuit which performs the servo recovery process. The servo recovery process, having multiple recovery processes, is called up when off track is detected. The frequency that the recovery process is called up is detected, and one of the multiple recovery processes is executed according to the detected call-up frequency. A different recovery process is performed when the call-up frequency is high, therefore this recovery process makes it possible to prevent frequent occurrence of the off-track state.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventors: Hideshi Mochizuki, Toru Ikeda
  • Patent number: 6633522
    Abstract: In a focus control of an optical disk with a fast reproduction velocity and a large face deflection, the present invention can effect a mistakeless and reliable focus pull-in method. The present invention comprises: means for applying a braking signal to a focus actuator before closing a focus control loop; means for detecting a reversal of a relative velocity between an objective lens performing a focus search operation and an optical disk which effects an up-and-down motion due to the face deflection; and means for detecting the relative velocity between the objective lens and the optical disk from a focus error signal which is detected in each layer of a multi-layer disk.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomoaki Ryu
  • Patent number: 6633523
    Abstract: An optical memory apparatus has an offset inserting unit for inserting a predetermined offset to the focus error signal, and a focus servo pull-in determining unit for inserting, when the focus servo control unit executes focus servo pull-in, offset to the focus error signal, detecting level change of the focus error signal and determining success or failure of focus servo pull-in.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: October 14, 2003
    Assignee: Fujitsu Limited
    Inventors: Takashi Masaki, Toru Ikeda