Abstract: The invention relates to an optical waveguide comprising at least a non linear optical (NLO) polymer.

Abstract: The present invention relates to a photochromic fluorescent polymer and a preparation method thereof, and more particularly, to a photochromic fluorescent polymer having bonds between diarylethenes and aryethene-vinylene precursors with a weight average molecular weight of 500 to 1,000,000, which exhibits highly improved photochromic and fluorescent characteristics compared to conventional photochromic fluorescent materials and excellent solubility to organic solvents, thus being applicable for photofunctional materials and information processing device such as optical recording, optical switches, non-destructive optical recording materials.

Abstract: A system for detecting, capturing and retrieving a wire, optical cable, string, coaxial cable, or other line or object from within a wall or other type of enclosed structure. The system uses magnetic forces to detect and capture the object through a wall or other type of structure of the enclosure. The system also comprises a retrieval mechanism for drawing the object toward an opening in the enclosure for retrieval from the enclosure.

Abstract: An improved cable pulling device and method is shown. The cable pulling device is smaller, less expensive, and easy to use for lateral line replacement. The cable pulling device includes a cable contacting portion that provides supplemental frictional force during a rotational pulling stroke. Among other advantages, this allows a smaller, more compact design that provides higher gripping and pulling power. Embodiments as described above further allow for a smooth jaw configuration that reduces cable damage. A cable pulling device is also shown that includes a configuration of a force distributing device. One embodiment includes substantially orthogonal plates that help to reduce device twisting during a pulling operation. In a further embodiment, a force distributing device is adapted for attachment to a ground working implement arm.

Abstract: The present invention relates to a convertible winch (A), comprising a basic body (1), motion transmission and reduction means (5; 5′, 5″), for the manual and powered operation, with a mono-direction rotation, and manual or powered operation according to at least two directions, with different rotation speed, and a central hole (4) for the insertion of manual operation means, said motion transmission and reduction means (5; 5′, 5″) providing at least a central gear (5′), a lower gear (5″), and a slidable side gear (21), coupling, by pawls (19, 20), with said central gear (5′) or with said lower gear (5″), determining the rotation according to different speed in function of the rotation direction of the manual or powered operation means, said winch (A) further providing, inside said body (1), means (18) interacting with said slidable gear (21), on which a operable button (14) removably acts, inside said insertion central hole (4) of the manual operation means (18

Abstract: A cable guardrail release system includes a first number of anchor posts installed adjacent a roadway. Each of the first number of anchor posts secures an end of a respective cable. Each anchor post is operable to release the respective cable secured by the anchor post upon a vehicle impact to the anchor post. The system may include a length of need section that includes a plurality of intermediate support posts each configured to support each of the respective cables. The length of need section may include portions of each of the respective cables running in between the plurality of intermediate support posts. Each anchor post may be configured to resist release of the respective cable secured by the anchor post upon a vehicle impact to the length of need section generally at an angle to the flow of traffic on the roadway.

Abstract: A fence assembly including a post and interconnecting rails. The post includes an interior chamber structure defined by numerous compartments, an exterior wall structure and a plurality of inwardly projecting rail-receiving channels. The rail-receiving channels at least partially define the geometry of the interior chamber structure. The assembly may be made of extruded plastic material such that the post, rails and additional components, such as channel inserts, are generally hollow along their respective elongate dimensions. Each of the components within the assembly may be cut to user-defined lengths. The purpose of the abstract is to enable the United States Patent and Trademark Office and the public generally to determine from a cursory inspection the nature and gist of the technical disclosure, and is not to be used for interpreting the scope of the claims.

Abstract: A modular railing system with handicap access is disclosed based on commercially available tubing assembled into a railing through use of fittings that connect to each other and the rails and posts of the railing system to allow all possible standard rail configurations. All connections are thereby held together by mechanical, rather than welded, connections.

Abstract: A group III nitride film is formed on an epitaxial substrate having an underlayer film containing Al. According to the present invention, the change of the properties of the II nitride film may be reduced The properties of the semiconductor device may be thus reduced and the production yield may be improved. An underlayer 2 made of a group III nitride containing at least Al is formed on a substrate 1 made of a single crystal. An oxide film 3 is formed on the underlayer film 2 to produce an epitaxial substrate 10. The oxygen content of the oxide film 3 at the surface is not lower than 3 atomic percent and the thickness is not larger than 50 angstrom.

Abstract: A substrate including a base substrate, an interfacial bonding layer disposed on the base substrate, and a thin film adaptive crystalline layer disposed on the interfacial bonding layer. The interfacial bonding layer is solid at room temperature, and is in liquid-like form when heated to a temperature above room temperature. The interfacial bonding layer may be heated during epitaxial growth of a target material system grown on the thin film layer to provide the thin film layer with lattice flexibility to adapt to the different lattice constant of the target material system.

Abstract: A single molecular species having a low-forward-voltage rectifying property is provided.

Abstract: An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor layer between a source electrode and a drain electrode, and gate electrodes shaped like a comb or a mesh, which are provided at intervals approximately in the central part of the organic semiconductor layer approximately parallel to the source electrode and the drain electrode. The organic semiconductor layer consists of an electric field luminescent organic semiconductor material such as compounds of naphthalene, anthracene, tetracene, pentacene, hexacene, a phthalocyanine system compound, an azo system compound, a perylene system compound, a triphenylmethane compound, a stilbene compound, poly N-vinyl carbazole, and poly vinyl pyrene.

Abstract: Integrated circuit chips include an internal circuit including interconnected semiconductor devices that are configured to provide integrated circuit functionality, and a Test Element Group (TEG) circuit that is configured to allow measuring of electrical characteristics of the semiconductor devices. By providing a TEG circuit in the same integrated circuit chip as the internal circuit, the TEG circuit may accurately represent the electrical characteristics of the interconnected semiconductor devices of the internal circuit of the associated integrated circuit chip. The integrated circuit chip may be coupled to a test apparatus. The test apparatus includes a test probe that is configured to simultaneously contact the internal circuit and the TEG circuit. The test apparatus also can simultaneously test the integrated circuit functionality of the internal circuit, and measure the electrical characteristics of the semiconductor devices via the TEG circuit.

Abstract: A method is disclosed for remedying defective cells that enables automatic cutting of capacitor fuses as part of the fabrication process. A comparison circuit determines whether defective cells are present in a memory cell array by comparing data that have been read from an I/O bus with data that have been determined in advance to determine whether the data are identical and supplies the determination result as a determination signal. An address buffer circuit, upon receiving a determination signal from the comparison circuit, latches the row address signal and column address signal that are being supplied as output at that time and supplies these latched signals as a capacitor fuse row address signal and a capacitor fuse column address signal for cutting capacitor fuses. Capacitor fuses in a capacitor fuse block are then each cut based on the capacitor fuse row/column address signals that have been latched by the address buffer circuit.

Abstract: An organic EL device is fabricated by a novel method to reduce the occurrence of poor luminescence in the organic EL device. The pixel aperture is formed at the part excluding above the contact hole formed for connecting the source electrode of the driving transistor and the pixel electrode of the organic light emitting device. The part where the pixel electrode is uneven is covered with the insulating layer to avoid the short between the pixel electrode and the counter electrode.

Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.

Abstract: In a thin film semiconductor device according to the present invention, a continuous oscillating light beam from a solid laser or the like is modulated on time axis and spatially, thereby realizing crystal growth that is nearly optimum for a crystal structure and a growth speed of crystals in a Sin thin film. Crystal grains with a large diameter, flatness with no projections at their grain boundaries, and controlled surface orientations are thereby formed. By forming channels with these crystal grains, high-mobility semiconductor devices and an image display device using these semiconductor devices are realized.

Abstract: A material for forming an insulating film with low dielectric constant of this invention is a solution including a fine particle principally composed of a silicon atom and an oxygen atom and having a large number of pores, a resin and a solvent.

Abstract: An active matrix substrate for a liquid crystal display and method of forming the same. To form the active matrix substrate five masks are needed. The first mask forms gate lines on the transparent substrate. The second mask patterns a stacked layer of a metal layer/an n-doped layer/a semiconductor layer formed on a gate insulating layer to form data lines. After forming a low k dielectric layer, the third mask forms openings therein. The forth mask patterns pixel electrodes and conducting lines with source pattern on the low k dielectric layer and further patterns the metal layer and the n-doped layer. After depositing a passivating layer the fifth mask defines the passivating layer.

Abstract: A thin-film capacitor device for performing temperature compensation is manufactured by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={&egr;0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, &egr;0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, and the seco

Abstract: A capacitive structure including single crystal silicon and an insulating layer in a semiconductor substrate. One embodiment of the present invention includes an optical switching device having one or more capacitive structures including single crystal silicon in a substrate such as a silicon-on-insulator (SOI) wafer and can be used in a variety of high bandwidth applications including multi-processor, telecommunications, networking or the like. In one embodiment, a capacitive structure includes single crystal silicon disposed in a first semiconductor material with an insulating layer disposed between the single crystal silicon and the semiconductor material. In one embodiment, a capacitive structure may be formed by laterally growing single crystal silicon through an opening in a trench adjacent to a trench where the capacitive structures is formed.

Abstract: It is an object of the present invention to provide a solid-state image pickup device capable of preventing any output variation due to a threshold voltage variation, and preventing a dynamic range from being narrowed in conjunction with deterioration in outputs due to a lowered threshold voltage. The present invention provides improvements in type and connection of a reset transistor, a select transistor, and an amplifier transistor to achieve the above object. Specifically, the present invention provides a solid-state image pickup device comprising a first MOS transistor serving as a reset switch, a second MOS transistor serving as a select switch, a photodiode, and a third MOS transistor having a source connected in series with the photodiode.

Abstract: Conductors to interconnect electronic devices, the conductors being formed on a detachable substrate. The substrate is aligned with a package containing electronic devices. The conductors are bonded to pads on the devices. Then, the substrate is detached. Each conductor is self supporting between the devices, has a two dimensional shape and has a surface that is substantially parallel to a surface of the pads.

Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.

Abstract: A luminescent diode chip for flip-chip mounting on a carrier, having a conductive substrate (12), a semiconductor body (14) that contains a photon-emitting active zone and that is joined by an underside to the substrate (12), and a contact (18), disposed on a top side of the semiconductor body (14), for making an electrically conductive connection with the carrier (30) upon the flip-chip mounting of the chip, whereby either the carrier is solder covered or a layer of solder is applied to the contact. An insulating means (40, 42, 44, 46, 48) is provided on the chip, for electrically insulating free faces of the semiconductor body (14) and free surfaces of the substrate (12) from the solder.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: A multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds. The vertical stacked structure is formed on a glass base having a transparent coating of ITO or similar metal to provide a substrate. Deposited on the substrate is the vertical stacked arrangement of three double heterostructure devices, each fabricated from a suitable organic material. Stacking is implemented such that the double heterostructure with the longest wavelength is on the top of the stack. This constitutes the device emitting red light on the top with the device having the shortest wavelength, namely, the device emitting blue light, on the bottom of the stack. Located between the red and blue device structures is the green device structure.

Abstract: A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.

Abstract: A light emitting diode incorporating an active emitting layer (14) overlying a transparent substrate (10) is provided with a reflective diffraction grating (30) on the bottom surface of the substrate. Emitted light passing downwardly through the substrate is diffracted outwardly toward edges (21) of the substrate and passes out of the die through the edges. This effect enhances the external quantum efficiency of the diode.

Abstract: A capacitive structure including single crystal silicon and an insulating layer in a semiconductor substrate. One embodiment of the present invention includes an optical switching device having one or more capacitive structures including single crystal silicon in a substrate such as a silicon-on-insulator (SOI) wafer and can be used in a variety of high bandwidth applications including multi-processor, telecommunications, networking or the like. In one embodiment, a capacitive structure includes single crystal silicon disposed in a first semiconductor material with an insulating layer disposed between the single crystal silicon and the semiconductor material. In one embodiment, a capacitive structure may be formed by laterally growing single crystal silicon through an opening in a trench adjacent to a trench where the capacitive structures is formed.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Abstract: A heterojunction bipolar transistor comprises, an emitter made of a first compound semiconductor of a first conductivity type; a base made of a second compound semiconductor of a second conductivity type and having a bandgap smaller than the first compound semiconductor; and a collector made of a third compound semiconductor of a first conductivity type and having a bandgap wider than the second compound semiconductor. The emitter and the base form a heterojunction of type I. The base and the collector form a heterojunction of type II. Further, the base includes impurities by a concentration equal to or more than 5×1019 cm−3.

Abstract: The present invention relates to the design and manufacture of and includes monolithically integrated diodes for use in planar, thin-film, photovoltaic devices, such as solar cells.

Abstract: A semiconductor device includes an insulating oxide layer formed by oxidizing a nitride semiconductor and an electrode formed of a conductive metal oxide on the insulating oxide layer.

Abstract: The operation of a bipolar transistor is controlled comprising by producing a first voltage that is a product of a static collector current of the bipolar transistor times an emitter resistance. The first voltage is then compared to a predetermined reference voltage to produce a control signal. Current is then injected a base of the bipolar transistor in response to the control signal. In a specific implementation, the first voltage, which is a product of the static collector current (Ic) of the bipolar transistor times its emitter resistance (RE) , is slaved to a predetermined reference voltage (Vref) whose value is substantially equal, to within a tolerance, to 13 mV at a temperature at or about 27° C.

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Abstract: A fuse state circuit for reading the state of a fuse that is enhanced to reduce the circuits susceptibility to ESD, EOS or CDM events.

Abstract: A power semiconductor device that uses a lead frame for making connection to a semiconductor device and has a structure less subject to fatigue failure at the connection part of the lead frame. A mold resin of a casing (14) is used for integrally covering the lead frame (6, 7, 13), semiconductor device (1), and metal block (15) serving as a substrate mounting the semiconductor device (1). The mold resin surrounding the lead frame (6) and semiconductor device (1) strengthens the joint therebetween, resulting in the power semiconductor device less subject to fatigue failure at the connection part of the lead frame (6).

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided, on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract: A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.

Abstract: A charge-coupled device (CCD) includes first-level transfer electrodes and second-level transfer electrodes alternately arranged along a transfer channel, wherein charge storage sections underlying the first-level transfer electrodes have a larger width than barrier sections underlying the second-level transfer electrodes. First and second interconnect lines supply two-phase driving signals to the transfer electrodes. Contact plugs connecting the first interconnect line to the transfer electrodes and contact plugs connecting the second interconnect line are located at opposite sides with respect to the center line of the transfer channel.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

Abstract: Disclosed is a ferroelectric capacitor in which polarization of a ferroelectric thin film can readily be reversed and polarization-reversal charge increased. The ferroelectric capacitor has a bottom electrode, a ferroelectric thin film and a top electrode. The top electrode comprises Ru1-xOx (where X is equal to or greater than 0.005 and equal to or less than 0.05, that is, the oxygen content in the Ru metal is 0.5 to 5 atm %) and has an Ru metal crystalline phase.

Abstract: A semiconductor device has a ferroelectric capacitor including a ferroelectric film provided on a lower electrode and an upper electrode provided on the ferroelectric film, wherein the upper electrode is formed of a first layer of a non-stoichiometric oxide and a second layer of a non-stoichiometric or stoichiometric oxide provided on the first layer, the second oxide having a composition closer to the stoichiometric composition as compared with the first layer.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A first repair chip, wherein BANK 2 functions properly although BANKs 0, 1 and 3 have become defective, and a second repair chip, wherein BANKs 1, 2 and 3 function properly although BANK 0 has become defective, are mounted on a rear surface of a module substrate in order to substitute for the functions of BANK 2 of the first bare chip and of BANKs 1 and 2 of the second bare chip that have become defective on the front surface of the module substrate. Thereby, a semiconductor memory module is obtained that can be repaired by mounting chips that carry out functions substituting for those of defective banks while effectively utilizing the functions of other banks that are not defective.

Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Abstract: A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.