Abstract: One aspect of the invention is a method for reconstructing a moving table MR image. The method comprises receiving an input array that includes a plurality of uncorrected k-space data points. The method further comprises clearing a summation array. For uncorrected k-space data points in the input array the following steps are performed. A kernel associated with the k-space data point is obtained. Corrected data is created in response to the k-space data point, the input array and the kernel. Creating the corrected data includes correcting the uncorrected k-space data point for gradient non-linearities, where the correction is performed in k-space, and correcting the uncorrected k-space data point for table movement. The corrected data is added into the summation array. The image is reconstructed in response to the data in the summation array.

Abstract: In a method for evaluating a time signal that is generated as a magnetic resonance signal by means of magnetic resonance technology and that contains spectroscopic information, an apodized time signal is formed by multiplying the time signal by a bell-shaped window function, an apodized spectrum is formed by Fourier transformation of the apodized time signal, an apodized informational spectrum is generated by removing noise components from the apodized spectrum, an apodized informational time signal is formed by Fourier back-transformation of the apodized informational spectrum, and an informational time signal is formed by multiplying the apodized informational time signal by an inverse function that corresponds in at least one section to the inverse window function.

Abstract: A method and system are provided for acquiring images using a magnetic resonance imaging (MRI) system. The method comprises the step of applying a plurality of steady-state free precession (SSFP) radio-frequency (RF) excitation pulses in a selected pattern of varying amplitudes and phases such that signals corresponding to the pattern of pulses are substantially immune to magnetic field inhomogeneity of the MRI system. The pulses have substantially equal spacing between all neighboring pulses and between successive groups of pulses. The method further comprises the step of reading a plurality of signals corresponding to the pulses.

Abstract: A transmit coil array assembly for use in a magnetic resonance imaging (MRI) system comprises a plurality of radio frequency (RF) coils arranged in a configuration for transmitting in parallel during transmission mode of the MRI system and a plurality of corresponding RF amplifiers each coupled to a corresponding RF coil for driving currents in the RF coils. The currents are controlled for defining and steering an excitation volume within an examined subject. The currents along with the currents in the gradient coils are further controlled to effect accelerated multi-dimensional excitation. A method for magnetic resonance imaging (MRI) with multiple transmit coils comprises the step of exciting a portion of an examined subject with the multiple transmit coils and the step of receiving magnetic resonance (MR) signals from at least one radio frequency (RF) coil for generating images corresponding to the selected portion of the subject.

Abstract: The present invention includes a method and apparatus to correct for gradient field distortions. The invention is particularly applicable in moving table imaging where a single extended image is desirable. The invention includes acquiring MR data in motion in the presence of gradient non-linearities, transforming the MR data acquired into the image domain, and then applying a warping correction function to the transformed MR data. The warp-corrected MR data is then corrected for motion induced during the MR acquisition. The data may be acquired point-by-point, line-by-line, or another sub-portion of the entire MR data acquired, and processed to minimize the amount of motion correction needed. Based on table velocity or acquisition sequence applied, the data is partitioned based on a common motion correction factor, and after correcting for motion, the data is accumulated to build up a final image.

Abstract: A method for compensating for magnetic noise fields in spatial volumes includes determining the strength of a magnetic field outside said spatial volume; defining the correlation between the noise field outside the spatial volume and the corresponding noise field inside said spatial volume; generating a magnetic compensation field for neutralizing the noise field in said spatial volume. The method further provides separate detection of noise fields with frequencies in the range of at least two different frequency bands.

Abstract: In a method and magnetic resonance tomography apparatus for spatially resolved presentation of a change of functional activities in the brain of a living subject by means of magnetic resonance, temporally successive magnetic resonance images of the brain of the subject stimulated with a stimulus are produced upon variation of at least one of the excitation angle and the echo time, a noise part for each pixel is calculated referenced to identical pixels of the temporally successive images, the noise part of each pixel is resolved into a first noise component independent of the excitation angle and a second noise component dependent n the excursion angle, the second noise component of the noise part of each pixel is resolved into a third noise component independent of the echo time and a fourth noise component dependent on the echo time, and the fourth noise component of the noise part of each pixel obtained in this way is employed for detecting neural activity changes in the brain of the living subject under o

Abstract: In a method for designing a selective RF pulse for a magnetic resonance apparatus, based on a determination of a first polynomial (An(z)) and a second polynomial (Bn(z)) that are Shinnar-LeRoux transforms of the RF pulse, a flip angle distribution (&agr;(x)) to be achieved with the RF pulse is prescribed, the first polynomial (An(z)) is determined proceeding from the flip angle distribution (&agr;(x)), the phase distribution of the transverse magnetization to be achieved with the RF pulse is prescribed, and the second polynomial (Bn(z)) is determined such that the magnitude is determined by the flip angle distribution (&agr;(x)) and the phase thereof corresponds to a sum of the prescribed phase distribution and the phase of the, first polynomial (An(z)).

Abstract: A radio frequency (RF) detector array and a MRI system are provided. The detector array comprises a plurality of conductive array elements being substantially parallel to a conductive ground plane, a plurality of capacitors, wherein at least one capacitor is shunted from each array element to the ground plane to adjust a corresponding electrical length of each conductive array element, and, wherein a combination of each respective array element, at least one corresponding capacitor and the ground plane forms a resonator that resonates at a selected frequency. The detector array further a decoupling interface, and a plurality of matching boxes for matching each decoupled conductive strip to a selected impedance. A MRI system is provided including a detector array as described herein to produce MR images of the object to be imaged.

Abstract: In a shim tray, a gradient coil system and a magnetic resonance apparatus for the acceptance of the shim tray, the shim tray is sub-divided, in the direction of insertion into the gradient coil system or the magnetic apparatus into at least two sub-boxes that can be released from one another.

Abstract: A radio frequency (RF) detector array assembly for use in a magnetic resonance imaging (MRI) system comprises at least one RF detector array, wherein the array has a plurality of RF detector elements for use in simultaneously acquiring radio frequency (RF) signals from the MRI system, and, a decoupling interface coupled to each of the plurality of detector elements for decoupling each detector element from the remaining detector elements. A method for decoupling radio frequency (RF) detector array elements in a magnetic resonance imaging (MRI) system is provided. The method comprises the steps of providing at least one RF detector array, wherein the detector array has a plurality of RF detector elements, and, providing a decoupling interface coupled to each of the plurality of detector elements for decoupling each detector element from the remaining detector elements.

Abstract: To generate a transient high voltage, which continuously follows the zero crossing of the high-current in the test circuit-breaker, on a test circuit-breaker arranged initially in a high-current circuit, by means of a high-voltage oscillating circuit and by transferring oscillating current with constant parameters from an auxiliary circuit-breaker in the high-current circuit as sequence current to the test circuit-breaker, which is consequently located in the high-voltage oscillating circuit. A high-voltage oscillating circuit (I), connected in parallel with the auxiliary circuit-breaker (Ba) by firing the switching spark gap (SGhv) and the oscillating current (ihv) superimposed on the high-current (ihc) with opposite polarity just before the high-current zero crossing.

Abstract: A method and apparatus for determining the state of charge of a lead-acid battery. The present invention includes steps to determine a current-based state of charge while accounting for such factors as current, temperature, charge efficiency, parasitic losses and self-discharge. The present invention is capable of measuring and/or calculating the open circuit voltage during and after operation to determine a voltage-based state of charge while compensating the open circuit voltage for its transient behavior and accounting for the voltage shift caused by charge events. The correlation of the open circuit voltage to the state of charge is dependent on the battery's mode of operation. The present invention is adaptive to battery aging by updating the battery resistance, correcting coulomb errors, and accounting for capacity degradation while in operation.

Abstract: Sensors that are capable measuring the rate of flow of a fluid that passes over the electrodes of the sensor. In these sensors, an electrode, designated the flow rate-determining electrode, is used in conjunction with the conventional electrodes, e.g., the working electrode, the reference electrode, and the counter electrode, to determine the rate of flow of the fluid. In one aspect, this invention provides a sensor for measuring the concentration of an analyte in a sample of fluid when the sample flows continuously over the electrodes of the sensor, especially when the rate of flow of the sample is relatively low. In another aspect, this invention provides a method for measuring the concentration of an analyte in a sample of fluid, wherein the rate of flow of the sample varies during the period of time that the sensor is in place. In a preferred embodiment, the sensor employs four electrodes, namely, a working electrode, a reference electrode, a counter electrode, and a flow rate-determining electrode.

Abstract: A system and a method are distinguished by the fact that, if it is determined that the system is not operating properly, a control device is stopped and it is ensured that the control device, when operation is continued, begins with the execution of the operation whose faulty execution may be the cause for the fault registered, or which was being executed when the fault was registered. This makes it possible, with little effort and without noticeable disruption to the operation of the system, to determine whether improper operation of the system is of only a temporary nature or of a permanent nature, and for the system or parts of the same to be deactivated or reset only when the fault that has occurred is not a temporary fault.

Abstract: Insulation monitoring of an electrical network such as a DC network which is electrically insulated with respect to the ground of a device, includes at least two insulation monitoring devices that monitor different network sections, which can be isolated by one or more switches. Non-contacting switches are used to alternatingly connect and isolate respective measuring resistors of the monitoring devices to, and from, ground, as a result of which the insulation monitoring devices can not negatively affect each other's measurements.

Abstract: Disclosed is a device for detecting a partial discharge of power equipment. EM (electromagnetic wave) sensors detect EM signals from a partial discharge in a metal clad switchgear, a power cable, and a GIS. EM detectors amplify the signals from the sensors, and output only noise-removed IF signals. A pulse generator integrates the IF-processed EM to compare the integrated value with a previous value, and outputs a pulse according to a partial discharge. An EM level processor compares the IF-processed EM with reference voltages to output EM pulses of a plurality of levels. A waveform shaper shapes the pulses. A controller calculates the average number of pulses per 1 cycle by counting the partial discharge pulses for a predetermined time, receives the waveform-shaped pulses to calculate the partial discharge amount, and transmits the calculated amount, combined with the average number, to an external monitoring system.

Abstract: A control module for a vehicle device control system contains a diagnostic circuit with one or more ASICs having a plurality of loops. The loops may contain either a squib, forming a squib loop, or a replacement resistor, forming a replacement resistor loop. A multiplexer connected to one loop of the ASIC diagnoses all of the replacement resistor loops. By using a multiplexer to detect replacement resistors, the invention eliminates the need to include an additional ASIC just to diagnose the replacement resistor loops.

Abstract: An RF power sensor for measuring power for an RF signal using capacitance includes a substrate preferably formed of a semiconductor, such as silicon or of a dielectric substance, a fixture part fixed to the substrate and forming a signal line and ground lines that transmit RF signals, and a bridge connected to the ground lines and floating over the signal line, wherein the bridge is driven by an external driving force, and the external driving force induces capacitance between the bridge and the signal line. Accordingly, power for an RF signal can be measured through the capacitance between the signal line and the bridge. The RF power sensor facilitates matchings, reduces insertion loss, and can be used in a wide bandwidth because it is based on transmission lines having characteristic impedance. Further, high power can be measured depending upon bridge designs.

Abstract: A transducer comprising at least one planar capacitor with a thin coverlayer of material selected to maximize electric field coupling between cooperating capacitor electrodes within a region external to a principal surface of the coverlayer. Preferred coverlayer materials have low values of moisture absorption, surface free energy, permittivity, dielectric dissipation, and electrical conductance. According to one embodiment of the invention, a driven shield further enhances electric field coupling over and in a region external to the principal surface. The transducer also can promote a physical change in specific adsorbates and materials and simultaneously detect and measure an effect of the induced change. Applications for the transducer of the invention include the measurement of the moisture content of grain and bulk stored commodities, humidity, a dew point temperature, the onset of condensation and rates of adsorption and desorption.

Abstract: The invention relates to a method for measuring the moisture content of skin, in which method a probe (1) is placed on the skin for measuring the capacitance of the skin. The invention relates also to an apparatus for applying the method, which apparatus comprises a probe (17) and devices (20-28) connected to the probe for transmitting, transferring and analysing a signal. In the method in accordance with the invention a wave signal is transmitted into the probe, the capacitance of the probe (17) is measured by comparing the wave phases of the transmitted and reflected wave, and the applied radio frequency is low, approximately 0.2-5 MHz. The apparatus in accordance with the invention comprises a device (26) into the input of which a wave formed by the signal reflected from the probe is arranged to be led, and into the other input of which a wave forming the signal and transmitted to the probe is arranged to be led, whereat the capacitance can be measured by comparing the wave phases.

Abstract: Disclosed is an assembly kit for an apparatus for simultaneously obtaining a biological sample and measuring the electrical resistance of said sample at at least two different frequencies for diagnosis of a condition of said sample. The assembly kit of the invention includes a main case; an aspirating needle adapted to be connected to the main case; a liquid collector adapted to be connected to said aspirating needle; and an electroimpedancemeter. The aspirating needle is used for obtaining a sample of biological liquid. The liquid collector receives said sample of said biological liquid and having a metal conductor in electrical contact with said needle and a metal piston. The electroimpedancemeter simultaneously measures electrical resistance of the sample at at least two different frequencies. Also disclosed is a method simultaneously obtaining a biological sample and measuring electrical impedance of the sample for the purpose of diagnosis of a condition of the sample.

Abstract: A current detection equipment comprises a first coil and a second coil connected in series with the first coil. The current detection equipment is capable of detecting a current flowing through an object which is provided between the first and second coils or provided in a vicinity of the first or second coil. Each of the first and second coils having first conductive patterns provided on a surface of a substrate, a second conductive patterns provided on a back of the substrate and connecting parts which connect the first and second conductive patterns. A semiconductor device including the current detection equipment to measure the current flowing in a semiconductor element is also proposed.

Abstract: Described are probes, designed to make electrical contact with high-density chips or similar electronic devices. Two groups of probes are covered. The first group includes probes that are moved laterally, parallel to the surface of the contact pads of the device under test, after the initial contact has been made. This is to create the desired wipe or scrub. The second group includes probes that operate on the principle of suction cups. When the probe is pushed against the device under test, the probe lips stretch outwardly and create the desirable wipe or scrub.

Abstract: A test module having a lid to force a chip in contact with the test pads using a bed of nails to conform to the shape of the chip. The lengths of the nails are cut to conform to be of equal length above the chip with different size heads to apply the proper force. A pressurized bag may be placed above the head of nails to apply force to the chip.

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

Abstract: A semiconductor device includes a plurality of logic cells formed on a semiconductor substrate, wherein each of the plurality of logic cells has a circuit for a function block of a logic circuit; and a wiring layer which connects the plurality of logic cells to form the logic circuit function blocks and thereby the logic circuit. The wiring layer includes a power supply wiring line pattern formed in a region corresponding to each of the plurality of logic cells; a ground wiring line pattern formed in the region; and a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the circuit of the logic cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern.

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract: Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.

Abstract: A general-purpose logic cell used in a general-purpose logic cell array for a logic circuit, includes a plurality of kinds of logic circuit elements, each of which has a plurality of terminals with no connection. The plurality of kinds of logic circuit elements includes a flip-flop and a first inverter set. In this case, each of first inverters of the first inverter set is possible to be connected with an input of the flip-flop in parallel or as one of a series connection of at least two of the first inverters. Also, each first inverter is possible to be connected with an output of the flip-flop in parallel or as one of a series connection of at least two of the first inverters.

Abstract: A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

Abstract: Techniques of increasing drive strength and reducing propagation delays of a digital logic circuit through the use of feedback are presented. Logic circuitry operative to receive an input signal of the digital logic circuit and a delayed version of an output signal of the digital logic circuit turns “ON” a supplemental drive transistor for a digital state transition of the output signal. The supplemental drive transistor provides supplemental drive current to the digital logic circuit during the output signal digital state transition, thus advantageously reducing propagation delay and increasing fan-out capability. The logic circuitry turns “OFF” the drive transistor once the output signal digital state transition is complete.

Abstract: A distributed dynamically optimizable processing, communications, and storage system (DD0PCASS), and the system includes: (A) a queue based processing and communications hardware environment, said environment maintaining, in a large address space, (first) at least three general purpose logical queues, and (second) an at least minimum connective communications topology distributed there-between; and (B) substantially-hierarchically above said queue based processing and communications hardware environment, another processing and communications hardware environment having (first) an input/process/output capability, and (second) data-communications linked to the queue based processing and communications hardware environment, and (third) a resource tracker operating task-specifically.

Abstract: A bulk input differential logic circuit. The circuit outputs a large signal high enough to assert a logic High and Low by variations of the threshold voltage controlled by the bulk input signal and amplification of the sense amplifier. A boost circuit is disposed on the bulk input terminal, which may receive multiple bulk input signals. This makes it possible to use fewer circuit elements and smaller circuit area for a complicated logic operation.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: A power-up signal generation circuit includes a first power-up detecting unit, to which an external power supply voltage is applied, for activating a first power-up signal when an increase of the external power supply voltage is detected, a second power-up detecting unit, to which an internal power supply voltage is applied, for activating a second power-up signal when an increase of the internal power supply voltage is detected and a power-up signal generating unit for activating a final power-up signal in response to combination of the first and the second power-up signals.

Abstract: A PLL circuit includes a voltage controlled oscillator (VCO), a phase comparator detecting phase difference between a reference signal and a feedback signal provided from the VCO, an input voltage control unit controlling input voltage to be provided to the VCO according to the phase difference detected by the phase comparator, a switching unit switching a value of the input voltage to be provided to the VCO, and a switching timing control unit controlling a switching timing of the switching unit based on the given reference signal, wherein the VCO controls a frequency of the feedback signal according to the input voltage provided from the input voltage control unit. As a result, the VCO can rapidly make the feedback signal in phase with the reference signal and therefore it is possible to effectively reduce the required lock-up time.

Abstract: A phase-locked loop (PLL) device is disclosed. The PLL device includes an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal, a timing error detector in communication with the interpolator for detecting a timing error value of the output signal, a loop filter in communication with the timing error detector for outputting the interpolation timing value to the interpolator in response to the timing error value, and a lock controller in communication with the loop filter for adjusting the interpolation timing value according to a timing quality of the output signal, and providing the adjusted interpolation timing value for the interpolator. A signal generation method for use in the data pick-up device with the aid of the digital phase-locked loop (PLL) device is also disclosed.

Abstract: A phase locked loop (PLL) with low steady state phase errors and a calibration circuit for adjusting the delay time for the PLL.

Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop charge pump is provided. The adjustment and calibration system includes at least one adjustment circuit, to which a phase locked loop charge pump output is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs the measurement to keep the external and internal signals synchronized. The time interval between one measurement and the next measurement is unequal to the cycle time of the external signal.

Abstract: A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the plurality of clock pairs output from the switch, for outputting clock signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clocks of the pair; a plurality of latch circuits which receive input data in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output.

Abstract: A temperature-sensing circuit includes a first circuit block outputting an output voltage having negative or positive temperature coefficients and a second circuit block amplifying the output voltage of the first circuit block to a predetermined amplitude and outputting the amplified output voltage. It further includes a third circuit block producing a voltage having temperature coefficients of a polarity opposite to that of the first circuit block and adding the produced voltage to the output voltage of the second circuit block to cancel out components of second order temperature coefficients contained in the output voltages of the first and second circuit blocks.

Abstract: A latch circuit is configured so that even if a power-on-reset circuit is not operated in putting a power supply to work, a depletion type MIS transistor is connected as a pull-down element to an output terminal of an RS latch to thereby reliably activate the RS latch in a reset state, whereby a circuit or a semiconductor integrated circuit device is prevented from being unintendedly operated. Furthermore, channel impurities of the depletion type MIS transistor are introduced into only a part, whereby it is possible to realize a semiconductor integrated circuit device which is excellent in safety and which is readily operated with less current consumption and with low cost.

Abstract: A delay circuit that delays an input signal to produce an output signal. The input signal and output signals has a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Abstract: A timing generation circuit includes: a delay section including a plurality of delay circuits for sequentially transferring a clock signal therethrough, wherein the clock signal is delayed by a predetermined amount of time before being output from one of the plurality of delay circuits in the delay section; and a control circuit for changing a delay time of at least one of the plurality of delay circuits in the delay section in accordance with a frequency of the clock signal.

Abstract: Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.