Patents Issued in January 6, 2004
-
Patent number: 6675251Abstract: A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the second ports includes a PCI master, a PCI target and an AGP Target. The bridge further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the second ports and arbitrators for arbitrating a contention between the transactions on the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.Type: GrantFiled: April 18, 2000Date of Patent: January 6, 2004Assignee: Renesas Technology Corp.Inventors: Robert Streitenberger, Hiroyuki Kawai, Yoshitsugu Inoue, Junko Kobara
-
Patent number: 6675252Abstract: A circuit arrangement and method implement the data path used during the processing of multiplied (e.g., 2× or 4×) Accelerated Graphics Port (AGP) fast write transactions within a circuit block outside of the PCI circuit block conventionally used to handle the address phases of such transactions. Rather than implementing the data path within the PCI circuit block, a control path is defined between the PCI circuit block and the other circuit block to permit the PCI circuit block to initiate the data phase of the multiplied AGP fast write transaction in the other circuit block after the address phase of the transaction has been initiated in the PCI circuit block. A circuit arrangement and method also implement a logic circuit used to generate AGP fast write transactions with support only for single block multiplied AGP fast write transactions—and without any support for multiple block multiplied AGP fast write transactions.Type: GrantFiled: February 7, 2001Date of Patent: January 6, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Reji Thomas
-
Patent number: 6675253Abstract: A drive array controller or other data handling system supports dynamic data routing across multiple data paths between a source controller and a destination controller. Each data path between the source controller and the data controller can include a cache memory. Based on detection of a cache address, the data path with the cache memory corresponding to the cache address is selected. Data transfer to a single destination controller can be alternated between different data paths based on detection of different cache addresses. Each data path can include a plurality of bus/memory interface devices and a peripheral bus such as a peripheral component interconnect (PCI) bus. As an alternative to dynamic data routing based on addressing, data routing can be based on command type.Type: GrantFiled: April 4, 2000Date of Patent: January 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hubert E. Brinkmann, Jr., Ryan A. Callison
-
Patent number: 6675254Abstract: A system and method for transferring information at a fast rate between add-in cards in a rack mount system are described. In one embodiment, the invention allow all the add-in cards within the rack mount system to be interconnected. All the main cards within the rack mount system connect to a switch card using point-to-point differential copper pairs. All communication over these differential copper pairs use a messaging protocol that provides a messaging protocol destination address that is used to route the information to the intended destination main card. The messaging protocol may be the Ethernet protocol. In an alternative embodiment, data redundancy is provided by having two switch cards in the rack mount system. A particular main card transmits one set of information to the first switch card and a second set of information (that is identical to the first set of information) to the second switch card.Type: GrantFiled: September 29, 2000Date of Patent: January 6, 2004Assignee: Intel CorporationInventor: Robert D. Wachel
-
Patent number: 6675255Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory system comprising a memory controller, and a synchronous memory device coupled to the memory controller. The synchronous memory includes a plurality of non-volatile elements, and control circuitry to read a status of the plurality of non-volatile fuses during an initialization operation. The memory has input command connections coupled to receive an initialization command from the memory controller. The control circuitry initiates the initialization operation in response to the initialization command.Type: GrantFiled: June 30, 2000Date of Patent: January 6, 2004Assignee: Micron Technology, Inc.Inventor: Frankie F. Roohparvar
-
Patent number: 6675256Abstract: A method and a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers. An access request including a page address, a column address, a write or read order, a possibly data to be written is received. The page address of the current request is compared with the page address of the preceding request and, if they are different, the controller stores the current request page in one non-used of the cache registers, preferably that which has not been used last.Type: GrantFiled: November 17, 2000Date of Patent: January 6, 2004Assignee: STMicroelectronics S.A.Inventor: Michel Harrand
-
Patent number: 6675257Abstract: A system and method store information to a sequential storage media such that storage space occupied-by data deemed obsolete may be reclaimed. Information may be written to the storage media as sequential data sets with each data set including a catalog describing the information in the data set. A reclamation catalog identifies the obsolete data stored on the media and is written to the media. A generation number on the storage media may indicate whether the storage media has been reclaimed. A reclamation process transfers data from the source media (e.g., the tape media that includes obsolete data) to a destination media (e.g., a blank tape) while excluding the obsolete data identified in the reclamation catalog. The reclamation process may read a catalog stored on the source media that describes the data stored on the source media. The reclamation process then modifies that catalog by the information stored in the reclamation catalog to create a unified catalog.Type: GrantFiled: June 28, 2000Date of Patent: January 6, 2004Assignee: Microsoft CorporationInventors: ATM Shafiqul Khalid, Ravisankar Pudipeddi
-
Patent number: 6675258Abstract: Methods and associated structure for updating and propagating firmware updates in a multiple redundant controller storage subsystem. The methods of the present invention assure that the storage subsystem remains operable processing host system I/O requests while the redundant controllers manage the firmware update process. At least one controller of a plurality of redundant controllers in the system remains available for processing of host I/O requests as the controllers manage the firmware update process. A management client process operable on an administrative system coupled to the first of the redundant storage controllers transfers a structured firmware file to the first redundant controller. The management client need perform no further management of the update process. Rather, the controller themselves manage the process in accordance with metadata stored within the firmware file along with the programmed instructions to be updated.Type: GrantFiled: June 30, 2000Date of Patent: January 6, 2004Assignee: LSI Logic CorporationInventors: Walter Bramhall, Rodney A. Dekoning, William P. Delaney, Ray Jantz
-
Patent number: 6675259Abstract: Method and apparatus for ensuring availability of disk units in a disk pool which may be switched between a primary system and one or more backup systems. One embodiment provides a method for ensuring accessibility of one or more disk units by a system, comprising: configuring a storage pool for the system; validating availability of the one or more disk units for the storage pool; and selecting one or more valid disk units for the storage pool. The method may further comprise ranking availability of each disk unit for the storage pool and selecting one or more valid disk units for the storage pool according to availability ranking.Type: GrantFiled: July 26, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Sherry Lynn Gordon, Clinton Gene Laschkewitsch, Michael James McDermott, Amartey Scott Pearson
-
Patent number: 6675260Abstract: A virtual electronic data library system has a plurality of storage elements. Each storage element is adapted to store a medium of a plurality of media. Preferably, a plurality of subsets of the media each have one format of a plurality of formats. A plurality of input/output elements are preferably adapted to receive and read the media stored in the storage elements. Each of the input/output elements is capable of operatively receiving media having at least one of the formats. A library controller has firmware wherein the subsets of the media are each assigned a logical unit number for use by the controller to partition the library. At least one transport is operable to remove the media from the storage elements and operatively deploy the media for use by one of the input/output elements. The transport deploys the media in an input/output element according to the logical unit numbers.Type: GrantFiled: October 31, 2001Date of Patent: January 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: William W. Torrey, Colette T. Howe
-
Patent number: 6675261Abstract: A request, such as those embedded in URLs and XML documents, is assigned to a thread of execution in a server that is in communication with a data store. The thread of execution includes a thread local storage with a pointer to a cache object. The cache object maintains copies of data store entries frequently accessed by the assigned request. The cache object is accessed in response to data store access commands arising from the request. When a data store access command specifies a data store entry not found in the cache object, the server creates and loads a corresponding cache object entry. The cache object is not updated when other requests alter data store entries, and memory access commands arising from other requests cannot cause the cache object to be accessed. When the request causes the server to write data to the data store, the cache object also maintains a copy of the written data.Type: GrantFiled: November 30, 2001Date of Patent: January 6, 2004Assignee: Oblix, Inc.Inventor: Michael J. Shandony
-
Patent number: 6675262Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.Type: GrantFiled: June 8, 2001Date of Patent: January 6, 2004Assignee: Hewlett-Packard Company, L.P.Inventors: Kenneth Mark Wilson, Fong Pong, Lance Russell, Tung Nguyen, Lu Xu
-
Patent number: 6675263Abstract: In general, the PBVT structure provides an effective method of filtering a stream of hardware generated prefetches by eliminating prefetch addresses that have proven to be inaccurate in the past. When compared to a design that uses a PFB of equal number of entries, the PBVT along with a small PFB provides virtually equivalent prefetch accuracy and miss rate reduction while using much less hardware area (97% less data storage space for a 1024-entry PFB case).Type: GrantFiled: August 27, 2002Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: James R. Anderson, Jeff J. Baxter, Ernest T. Lampe
-
Patent number: 6675264Abstract: A method of writing to cache in a clustered environment. A first node in a storage cluster receives a request to write data from a user application. The first node determines if the data is owned by a remote node. If the data is owned by a remote node, the data in the remote node may be invalidated, if necessary. Such invalidation may not be necessary if a global cache directory is utilized. Thereafter, the data is written in a cache of the first node. Additionally, the data is written in a cache of a partner node of the first node. Confirmation of the cache write in the partner node is then received in the first node.Type: GrantFiled: May 7, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Ying Chen, Honesty Cheng Young
-
Patent number: 6675265Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.Type: GrantFiled: June 11, 2001Date of Patent: January 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets, Jr.
-
Patent number: 6675266Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.Type: GrantFiled: December 29, 2000Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
-
Patent number: 6675267Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.Type: GrantFiled: October 5, 2001Date of Patent: January 6, 2004Assignee: STMicroelectronics LimitedInventor: Fabrizio Rovati
-
Patent number: 6675268Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.Type: GrantFiled: December 11, 2000Date of Patent: January 6, 2004Assignee: LSI Logic CorporationInventors: Rodney A. DeKoning, Charles D. Binford, Michael J. Gallagher, Ray M. Jantz
-
Patent number: 6675269Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: February 4, 2003Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
-
Patent number: 6675270Abstract: A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.Type: GrantFiled: April 26, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, Warren Edward Maule
-
Patent number: 6675271Abstract: A PACS including a source of medical data, such as a CT unit (20), a workstation (100) capable of creating an image of the data, and a local area network (40). A server (60) stores compressed medical data in a RAID (70) and also in a magneto-optical unit (80) and a tape DLT unit (90). The tape unit (90) has a transfer rate equal to or greater than the transfer rate of the RAID.Type: GrantFiled: December 16, 1999Date of Patent: January 6, 2004Assignee: General Electric CompanyInventors: Xiaofeng Xu, Glenn Robert Kulpinski
-
Patent number: 6675272Abstract: A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.Type: GrantFiled: April 24, 2001Date of Patent: January 6, 2004Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
-
Patent number: 6675273Abstract: A memory circuitry is designed to efficiently obtain a predictable array output when an invalid address is requested. The memory circuit comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.Type: GrantFiled: May 31, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Steven Michael Eustis, Robert Lloyd Barry, Peter Francis Croce
-
Patent number: 6675274Abstract: Described are techniques for determining temporary storage areas for logical volumes to be swapped. Logical volumes may be swapped in a computer system in connection with efforts to improve performance of associated data storage entities in the computer system. As part of the data swapping and physical relocation of logical volumes, temporary storage locations are used. A temporary storage location is associated and used with each logical volume being swapped. Determining a temporary storage area for a logical volume may be made in accordance with particular criteria. A temporary storage area is determined for each logical volume from a list of one or more possible candidate locations. The problem of matching a logical volume to a unique temporary storage area may be represented as a bipartite graph matching problem using solutions, such as the maximum flow, and other techniques to find a match for each logical volume.Type: GrantFiled: March 15, 2001Date of Patent: January 6, 2004Assignee: EMC CorporationInventors: Tao Kai Lam, Yoav Raz, Ruben I. Michel, Musik Schreiber, Avigail Matalon
-
Patent number: 6675275Abstract: A computer system for CPU command conversion or real-time compilation with excellent performance. A part of a memory is operated as a special memory area for CPU command conversion or for real-time compilation. The computer system includes: a CPU; a memory; a memory controller for controlling the memory; a chip set; a ROM; a special memory setting table for setting a memory capacity to be mounted, and a capacity setting value of the special memory area corresponding to the capacity setting value of the special memory area corresponding to the capacity of each memory capacity; and a special memory area setting unit for reading the capacity setting value of the special memory area corresponding to the capacity of all the mounted memories from the special memory setting table at the time of starting, and then setting the special memory area.Type: GrantFiled: September 21, 2001Date of Patent: January 6, 2004Assignee: Fujitsu LimitedInventors: Kazuaki Nimura, Hiroshi Yamada
-
Patent number: 6675276Abstract: A one-time programmable memory is described with a storage allocation table which is compatible with a host computer.Type: GrantFiled: November 13, 2001Date of Patent: January 6, 2004Assignee: Eastman Kodak CompanyInventors: Paul E. Schulze, Laurence J. Lobel
-
Patent number: 6675277Abstract: A method and apparatus for using a memory adapter may allow a system to access the memory adapter. The memory adapter may comprise a list of entries for data within the memory adapter. Each entry may include an adapter memory segment offset, a segment length, a segment status, and a corresponding system memory address. The adapter memory segment offset may be the location of the offset within the memory adapter. A processor may access the adapter memory segment offsets through the system address space. The method and apparatus may be used to perform functions, such as read adapter memory, write adapter memory, insert adapter memory segment, remove an adapter memory segment, scan for an adapter memory segment, scan for a removable adapter memory segment, and potentially other functions.Type: GrantFiled: July 25, 2001Date of Patent: January 6, 2004Assignee: TNS Holdings, Inc.Inventors: Karlon K. West, Lynn P. West
-
Patent number: 6675278Abstract: A method and apparatus of managing a memory (2) having a number of pages (5) involves mapping the physical pages (5) to corresponding pages (4) in a logical address space (1) using a map table (3). When the number of pages utilised by an application increases or decreases, or if an application is deleted or a new application is loaded, the physical pages used by the remaining applications are unchanged, but the logical pages are moved so that the logical pages used by a single application are contiguous and so that the unused pages are contiguous. Thus, after moving the logical pages, the mapping of the logical pages to the physical pages is updated and a free page pointer (6) indicates the next available free logical page.Type: GrantFiled: April 19, 2000Date of Patent: January 6, 2004Assignee: Motorola, Inc.Inventors: Dipendra Chowdhary, Dhiwakar Viswanathan, Sung-Ho Jee, Peter McGinn
-
Patent number: 6675279Abstract: A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a fetch prediction means, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory.Type: GrantFiled: October 16, 2001Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, William J. Starke
-
Patent number: 6675280Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.Type: GrantFiled: November 30, 2001Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: Robert N. Cooksey, Stephan J. Jourdan
-
Patent number: 6675281Abstract: In accordance with the objectives of the invention a new method is provided for the updating and erasing of flash memory data. The new method effects and improves the write, the update and the read operations of the flash memory cell.Type: GrantFiled: January 22, 2002Date of Patent: January 6, 2004Assignee: iCreate Technologies CorporationInventors: Yaw Oh, Jen Chieh Tuan
-
Patent number: 6675282Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.Type: GrantFiled: February 12, 2003Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: Herbert H. J. Hum, Stephan J. Jourdan, Deborrah Marr, Per H. Hammarlund
-
Patent number: 6675283Abstract: A device for a hierarchical connection of a plurality of functional units in a processor comprises a first connector with at least two inputs and an output, which is adapted for connecting one of the inputs to the output, a second connector with at least one input and an output, which is adapted for connecting the input to the output, and a buffer connected between the output of the second connector and the input of the first connector for buffering, for at least one clock cycle, a signal applicable to the at least one input of the second connector before H is forwarded to a further input of the first connector. The output of the first connector is connected to an input of a first functional unit. An output of a second functional unit is connected to a first input of the at least two Inputs of the first connector. The at least one input of the second connector is connected to a third functional unit.Type: GrantFiled: June 28, 2000Date of Patent: January 6, 2004Assignee: SP3D Chip Design GmbHInventor: Gordon Cichon
-
Patent number: 6675284Abstract: An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received.Type: GrantFiled: August 20, 1999Date of Patent: January 6, 2004Assignee: STMicroelectronics LimitedInventor: Robert Warren
-
Patent number: 6675285Abstract: A method and apparatus for eliminating memory contention in a computation module is presented. The method includes, for a current operation being performed by a computation engine of the computation model, processing that begins by identifying one of a plurality of threads for which the current operation is being performed. The plurality of threads constitutes an application (e.g., geometric primitive applications, video graphic applications, drawing applications, etc.). The processing continues by identifying an operation code from a set of operation codes corresponding to the one of the plurality of threads. As such, the thread that has been identified for the current operation, one of its operation codes is being identified for the current operation. The processing then continues by determining a particular location of a particular one of a plurality of data flow memory devices based on the particular thread and the particular operation code for storing the result of the current operation.Type: GrantFiled: April 21, 2000Date of Patent: January 6, 2004Assignee: ATI International, SrlInventors: Michael Andrew Mang, Michael Mantor
-
Patent number: 6675286Abstract: Partitioned sigma instructions are provided in which processor capacity is effectively distributed among multiple sigma operations which are executed concurrently. Special registers are included for aligning data on memory word boundaries to reduce packing overhead in providing long data words for multimedia instructions which implement shifting data sequences over multiple iterations. Extended partitioned arithmetic instructions are provided to improve precision and avoid accumulated carry over errors. Partitioned formatting instructions, including partitioned interleave, partitioned compress, and partitioned interleave and compress pack subwords in an effective order for other partitioned operations.Type: GrantFiled: April 27, 2000Date of Patent: January 6, 2004Assignee: University of WashingtonInventors: Weiyun Sun, Stefan G. Berg, Donglok Kim, Yongmin Kim
-
Patent number: 6675287Abstract: An apparatus for forwarding storehit data within a pipelined microprocessor is provided. The apparatus has a plurality of response buffers that receive data from a bus that couples a system memory to the microprocessor and multiplexing and forwarding logic. When a store instruction generates a miss of the microprocessor's instruction cache, the store results are written not only to store buffers for updating the cache, but also to one of the response buffers. The missing cache line implicated by the store miss is requested from the system memory, received into the response buffer, and merged with the store results. The cache is updated with the merged data. However, in addition, storehit conditions with the store results generated by load instructions coming down the pipeline are satisfied from the response buffer. The multiplexing and forwarding logic is capable of forwarding the store results from the response buffer to the pipeline both before and after the missing cache line is received.Type: GrantFiled: April 7, 2000Date of Patent: January 6, 2004Assignee: IP-First, LLCInventors: Darius D. Gaskins, G. Glenn Henry, Rodney E. Hooker
-
Patent number: 6675288Abstract: A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.Type: GrantFiled: May 9, 2002Date of Patent: January 6, 2004Assignee: Hewlett-Packard Development Company L.P.Inventors: James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Lawrence Leibholz, Derrick R. Meyer
-
Patent number: 6675289Abstract: A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.Type: GrantFiled: June 30, 2000Date of Patent: January 6, 2004Assignee: Broadcom CorporationInventors: Ian S. Eslick, Mark Williams, Robert S. French
-
Patent number: 6675290Abstract: The present invention provides a processor capable of carrying out a plurality of operation instructions simultaneously in one cycle which improves utilization of an instruction when carrying out a single operation instruction, and a system equipped with such a processor. In this processor, an operation mode indicating whether or not a coprocessor should be run in parallel is retained in an operation mode register, and in the integer processor operation mode, a value “0” is set in the operation mode register in an operation mode controller of an integer processor, and an instruction register delivers an integer processor instruction to a decoder, so that an execution unit will execute the integer processor instruction, and outputs a no operation instruction to a data processor without embedding an instruction that defines an operation thereof, and puts the data processor in the halt condition.Type: GrantFiled: June 28, 2000Date of Patent: January 6, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Takashi Miyamori
-
Patent number: 6675291Abstract: Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.Type: GrantFiled: April 26, 2000Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Alain Benayoun, Jean-Francois Le Pennec, Claude Pin, Patrick Michel
-
Patent number: 6675292Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.Type: GrantFiled: August 13, 1999Date of Patent: January 6, 2004Assignee: Sun Microsystems, Inc.Inventors: J. Arjun Prabhu, Douglas M. Priest
-
Patent number: 6675293Abstract: A method and system comprising at least one service processor that is connected to memory and a host system. Additionally, the host system includes at least one host input resource device, such as, for example, a floppy disk, and an interface connecting the host input resource device to the service processor. The interface provides a means for the host input resource device to update, restore, or initialize host system parts or images. In one embodiment, this invention disconnects the host input resource device from main system power and connects it to auxiliary standby power. Thus, the host input resource device makes possible a less costly, less burdensome update of any piece of a data processing system.Type: GrantFiled: November 2, 2000Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: William Eldred Beebe, Christopher L. Canestaro, Robert Allan Faust, Craig Henry Shempert
-
Patent number: 6675294Abstract: The invention provides the ability to interactively select and configure a product among a set of related products based on availability and compatibility of features and options. It does not impose an order in the selection of products, features or options; only valid selections can be made at any time. To create an electronic representation of the product information to achieve the above goal, the invention provides a framework for defining a systems by defining the components of the system using elements contained in a parts catalog and defining relationships between the components of a system. A configuration system validates a configuration using the system definition, the current state of the configuration and user input.Type: GrantFiled: April 25, 2002Date of Patent: January 6, 2004Assignee: Trilogy Development Group, Inc.Inventors: Neeraj Gupta, Venky Veeraraghavan, Ajay Agarwal
-
Patent number: 6675295Abstract: Methods and systems for detecting and correcting computer software problems that cause an application program to crash upon startup are provided. Unsafe startup actions that are costly to initiate in terms of processor time and memory are handled by placing an unsafe startup action marker into the system registry prior to attempting startup. If an unsafe program module starts or boots successfully without causing the software application to crash, the unsafe startup action marker is deleted from the system registry. If loading the unsafe program module causes the application to crash, then startup actions, including corrective actions, are written into the unsafe startup action marker and are used on subsequent startup of the crashed application program to instruct the application on how to fix the problem. Other unsafe startup actions that are not costly in terms of processor time and memory are initially handled by an exception handler.Type: GrantFiled: June 19, 2000Date of Patent: January 6, 2004Assignee: Microsoft CorporationInventors: Michael R. Marcelais, Brian T. Hill, Eric LeVine, Steven Miles Greenberg
-
Patent number: 6675296Abstract: A certificate issuing apparatus and method creates a new certificate of a differing format from an existing certificate format to facilitate certificate conversion. A certificate converting unit receives first certificate data in a first format and desired certificate format criteria data, such as data representing the format of a certificate to which the first certificate is to be converted. The apparatus and method then generates second certificate data in a second format in response to the desired certificate format criteria data. In one embodiment, this is done using certificate format template data, such as templates representing the format and/or syntax of a plurality of differing certificate formats. The format template data is then mapped so that information from one certificate can be suitably mapped and then placed in a proper format and syntax for a different certificate format.Type: GrantFiled: June 28, 1999Date of Patent: January 6, 2004Assignee: Entrust Technologies LimitedInventors: Sharon M. Boeyen, James Steven Lloyd, Ronald J. Vandergeest
-
Patent number: 6675297Abstract: The present invention increases the difficulty of reverse engineering sensitive information protected by an encryption algorithm by increasing the difficulty associated with tracing the code that generates the key or the encryption algorithm. This is accomplished by generating the key, used to encrypt and decrypt the sensitive information, as a function of the program instruction values of the procedures used to generate the key and perform the decryption of the sensitive information. Thus, if the key generation code or the decryption code is modified (such as (but without limitation) by placement of a breakpoint, a trace function, or a halt instruction in the code) the resulting key will be different from the key used to encrypt the sensitive information and the decryption attempt will fail.Type: GrantFiled: March 5, 1999Date of Patent: January 6, 2004Assignee: Sigma Designs, Inc.Inventor: Michael Ignaszewski
-
Patent number: 6675298Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed by the CPU with modified op codes. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The modified op codes are provided with surplus bits, causing an increase in op code length, and the output of data results is provided in blocks of several words. The internal allocations of signals and logic gates is made key dependent to further foil the efforts of adversaries who may attempt to understand the program instructions.Type: GrantFiled: August 18, 1999Date of Patent: January 6, 2004Assignee: Sun Microsystems, Inc.Inventor: Alan Folmsbee
-
Patent number: 6675299Abstract: The content of a document is stored in a file system, while the profile of the document is stored in a messaging system. The profile of the document is accessed upon request, and the document content is accessed based upon the content of the profile.Type: GrantFiled: November 30, 1998Date of Patent: January 6, 2004Assignee: iManage, Inc.Inventors: Jack Edward Porter, Geoffrey Leroy Brimhall, William Montgomery Crane, Liam Patrick O'Gorman
-
Patent number: 6675300Abstract: A computer system having a remote controller storing an identification number includes a remote controller generating a remote control signal for performing remote control of the computer system and a remote control signal receiver receiving a remote control signal from the remote controller. An identification number is stored in the remote control signal receiver and the remote controller, respectively. When the two identification numbers are identical to each other, remote control of the computer system in response to the remote control signal from the remote controller is then performed. According to a power state of the computer system, the remote control signal causes remote control corresponding to an appointed key of the remote controller to be performed. The identification number of the computer system is provided for a security function of the computer system, and a user can set it to be identical to that of the remote controller.Type: GrantFiled: March 13, 2000Date of Patent: January 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Duck Jung, Hong-Sam Kim