Abstract: A microcomputer malfunction preventive apparatus that halts supplying of a clock signal to a microcomputer when fluctuations in a supply voltage deviate from an acceptable range, and resumes supplying of the clock signal to the microcomputer when the fluctuations return to the acceptable range.

Abstract: A modular power node comprises modules containing components ultimately connectable to a load to modify power supplied to that load to make the power supplied to the load suitable therefor, the modules being shaped to conform to and contact one another to minimize node size by mutually supporting one another.

Abstract: A power management PC expansion card controller that includes power on reset circuitry to reset power management enable registers during a reset period, thereby ensuring that the PME registers correctly identify the power management capabilities of the controller. Once the PME registers are reset, an instruction may be provided to change the state of the registers from a default reset state to a state that supports advanced power management capabilities, for example wake-up functions. Additionally, the controller includes blocking circuitry to block conventional reset signals from resetting the power management and proprietary registers if the PME register is instructed to change states, thereby preserving the data contained in the power management and proprietary registers against future reset events.

Abstract: A voltage regulator may switch in an extra load when the voltage regulator changes from a higher to a lower output level in response to a processor change of state in a processor-based system. The additional load at the lower voltage level in the processor-based system may decrease the latency in the voltage level transistor, improving processor performance.

Abstract: A method and system for selectively providing a gated clock signal to a control and status register block is provided. The method performs an operation by an application on a CSR block is provided. The operation may be programming a control register or reading a status register. The application detects when the operation is needed. If the operation is to be performed, a gated clock signal is enabled to the control and status register. The application then performs the operation on the control and status register block based on the gated clock signal. The gated clock signal may disabled after the operation has been performed. A system is provided for performing an operation on a control and status register block in a universal serial bus peripheral is provided. Clock gating logic detects when the operation is to be performed and provides a gated clock signal to the control and status register block when the operation is to be performed.

Abstract: An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.

Abstract: A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

Abstract: Methods of determining whether a network interface card entry within the system registry of a Windows™-based operating system pertains to “real” physical hardware or to a “virtual” device. In one embodiment of the present invention, the method includes the steps of: (1) opening the HKEY_LOCAL_MACHINE\System\CurrentControlSet\Services\Class\Net key entry of the system registry; (2) examining each of the sub-keys for the “Net” key, and find one with a “DriverDesc” string value matching a NIC; (3) opening the “Ndi” key under the matching sub-key; (4) getting the “DeviceID” string value under the “Ndi” key; and, (5) searching the “DeviceID” string for a backslash “\” character. If the backslash character is found, then it can be concluded that the network interface card entry is associated with “real” physical hardware.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models.

Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.

Abstract: A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract: A source clock regenerating section (10) comprises an operating section (2) for taking a weighted average value of a plurality of buffer remaining volumes H that have been sequentially detected, multiplying a predetermined sensitivity coefficient A to this weighted average value, and further adding a predetermined offset value, thereby to obtain a control value U for regenerating the source clock; and an operation control section (5) for setting a local clock (14) to a manipulated variable to be used for calculating the control value capable of converging to the source clock at a high speed during a period from when a source clock regeneration operation has started till when the local clock (14) as a regeneration source clock satisfies a predetermined condition for coming closer to a source clock frequency, and for setting the local clock to the manipulated variable capable of stably regenerating the source clock after this predetermined condition has been satisfied.

Abstract: Mechanisms are provided for preserving data wherein one or more nodes in a distributed computing system experiences an error. In one embodiment, when an error occurs, an error event is identified. Based on this error event, a set of identified execution units is suspended and a set of identified data is collected. All suspended execution units are then released, i.e., allowed to continue execution at the point where the units were suspended. The data collected during suspension is then used to diagnose the cause of the error.

Abstract: A method of (and system for) recovering the state of a failed node in a distributed shared memory system, includes directing a flush of data from a failed node, and flushing the data from the failed node to a memory node.

Abstract: A method and system for erasing a drive of a computer system is disclosed. The method and system include scrubbing the drive and writing a message to a portion of the drive such that the message will be provided to a user in response to the drive being booted after scrubbing. The message indicates that the drive has been scrubbed.

Abstract: A storage system is described including a two dimensional array of disk drives having multiple logical rows of drives and multiple logical columns of drives, and at least one drive array controller configured to store data in stripes (e.g., across the logical rows). A given drive array controller calculates and stores: row error correction data for each stripe of data across each one of the logical rows on one of the drives for each row, and column error correction data for column data grouped (i.e., striped) across each one of the logical columns on one of the drives for each column. The drive array controller may respond to a write transaction involving a particular row data stripe by calculating and storing row error correction data for the row data stripe before completing the write transaction.

Abstract: A method and apparatus controls the memory data access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module assemblies that meet the specification of a fully or partially functional assembly.

Abstract: The invention relates to a method and apparatus for synchronizing at least one computer, having at least one monitoring circuit associated with this computer. The synchronization takes place through at least one transmitted signal (WDS) in the form of a double pulse from the computer (&mgr;C) to the peripheral components (PIC1, PIC2), which contain the monitoring circuits. To that end, shortly after the computer (&mgr;C) is started up at system start or after an HW reset, the signal (WDS) is sent to the at least one peripheral component (PIC1, PIC2). After this, the upper and lower limit of the signal sequence (WDS) to be regularly transmitted by the computer for the monitoring circuit are tested and therefore the function of the monitoring circuits is tested. As with the synchronization, the testing takes place with a reaction of the monitoring circuits by means of at least one acknowledgement signal (IRS1, IRS2, R).

Abstract: A data processing apparatus has a direct access non-volatile memory storage device having a plurality of extent files for storing log records therein; an allocating unit for allocating a current extent file to be used for storing log records; a writing unit for writing log records into the current extent file until the current extent file cannot store any further log records; and a key-pointing unit for performing a key-pointing operation on the written log records when the writing unit has reached the point where no further log records can be stored in the current extent file.

Abstract: A self-test device serves for carrying out a self-test of an integrated circuit. An output of the self-test device is connected to a contact-making point of the circuit, which serves for external contact-making and which is connected to an input of a circuit unit of the integrated circuit to be tested. The self-test device feeds a test signal through the contact-making point to the circuit unit.

Abstract: An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A communication network includes a customer database storing information including a customer identifier and an associated plurality of telephone numbers. The customer database preferably is in communication with both a circuit switch component and a packet switch component using a first protocol. The switch components are further in communication with an error collection computer using a variety of unique protocols. Upon the occurrence of an error in the network, the switch component provides an error message to the error collection computer for analysis. An interconnecting datalink is also provided between the customer database and the error collection computer communicating using a second protocol. This interconnecting datalink allows additional information to be passed without changing the SS7 protocol or the variety of unique protocols from each of the network components.

Abstract: A receiver unit for receiving asynchronous digital data signals.

Abstract: A communications system includes a first device comprising a plurality of electrical-to-transmission medium converters, and a second device comprising a plurality of transmission medium-to-electrical converters to be connected to respective ones of the electrical-to-transmission medium converters via at least one transmission medium and defining parallel communications channels between the first and second devices, and wherein deskewing is provided. More particularly, the first device may include a string-based framing coder for determining and appending a string-based framing code to each information symbol string of information symbol strings to be transmitted in parallel over respective parallel communications channels. Each string-based framing code is based upon at least some of the information symbols in the respective information symbol string. The second device preferably comprises a deskewer for aligning received information symbol strings based upon the string-based framing codes.

Abstract: A computer network includes a transmitter, a receiver, and a communication channel system interconnecting the transmitter and receiver. All components in the system may be physical equipment or may be models having predefined operational characteristics. The predefined operational characteristics may be monitored or modified to obtain benchmarking and error rates for the computer network.

Abstract: An internal memory in an ASIC device which is capable of allowing timing constraints to control signals in an asynchronous two-port RAM is disclosed. The present internal memory includes delays which synchronizes the timing of the read and write signals. Also, a method for easily and accurately testing a two-port RAM is disclosed, allowing a stable implementation of an internal memory in an ASIC device.

Abstract: Method and apparatus for testing the operation of an integrated circuit (IC) while maintaining the supply input to the IC constantly active during the test. A logic indication signal that provides a first logic level indicating the active state of the supply input and a second logic level indicating the inactive state of the supply input, is generated. The inactive state of the supply input is simulated by processing the first logic level and by generating a third logic level that is essentially similar, or identical, to the second logic level. The third logic level is applied to one or more signal-carrying contacts within the IC and these, or other, signal-carrying contacts within the IC are accessed and their corresponding signal values responsive to the applied third logic level are read. One or more read signal values are compared with the one or more values expected for such readings.

Abstract: A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Abstract: A communication LSI device includes a state machine section and a test control section. The state machine section carries out a configuration operation in an idle state in response to a first reset signal. The state machine section changes to the idle state after completion of the configuration operation. The state machine section outputs a flag signal after a predetermined time since the state machine section changes to the idle state. The test control section outputs one the first reset signal to the state machine section in a test mode in response to the flag signal or a second reset signal externally supplied.

Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.

Abstract: A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction register and at least one data register for supporting testing and emulating a memory subsystem with different types of physical memory in a microprocessor based system.

Abstract: A method and arrangement for testing different types of external memories that can be coupled to a network interface controller. The network interface controller interprets the results of the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.

Abstract: A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit.

Abstract: Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A system and method for using forward error correction (FEC) to improve transmission reliability for data packets transmitted over packetized data networks, such as voice packets transmitted over an Internet Protocol (IP) network is disclosed. Packets containing error data are transmitted separately from corresponding voice packets. The error packets are transmitted a predetermined number of frames before the voice packets, to increase the probability that either the voice packet or error packet will be received. The error packets are preferably created using a Reed-Solomon algorithmn. The amount of error correction transmitted may be adaptively adjusted based on the reliability of the network connection.

Abstract: An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.

Abstract: A direct comparison adaptive halting turbo decoder computes the sum of the a priori and the extrinsic information sequences at each iteration step. The sum sequences are coded so as to be simple binary sequences. New sum sequences are generated during each iteration and used to estimate the state of the convergence without resorting to use of transmitted error detection codes. The adaptive halting turbo decoder is halted when the sum sequences generated in a single iteration step produce identical binary sequences, i.e. a change in the sum sequence is observed during the iteration and when there is no more change, the iteration is halted.

Abstract: A code error correcting and detecting apparatus includes a controller that repetitively processes error correction and detection of encoded CD-ROM data, thereby relieving a control microprocessor of a CD-ROM system of the burden associated with such repetitive processing. The apparatus includes an error correction circuit that performs code error correction on digital data, such as digital data read from a CD, using an error-correcting code (ECC). An error detection circuit performs error detection on the error-corrected digital data using an error-detecting code (EDC) and determines whether there is an error. A control circuit causes the error-correction circuit to repeat its error-correction processing in accordance with the detection of an error by the error detection circuit.

Abstract: A method and an apparatus are used to maximize available transmission bandwidth by using multiple error correcting code (ECC) schemes. A transaction between components in a computer system may involve the transmission of header information in a header packet. One or more separate data packets may then be used to transmit other data, depending on the particular transaction and the transmission bandwidth. Using a multiple ECC scheme, the header packet and transactions with a small number of data packets may be protected using one type of ECC. The data packets part of a large transaction with a large number of data packets may be protected by another compact ECC, thus significantly reducing the ECC overhead, and improving transmission bandwidth. To reduce data latency, parity bits may be distributed with each of the data packets, with the remaining ECC bits included in the last data packet.

Abstract: A method and apparatus for processing data read from a DVD media containing stored data is described. The apparatus includes a DVD media reader for reading data and error information stored on a DVD media, an error processor for determining the number of errors in the read data, and a display means for displaying the number of errors. The method includes reading actual data from a DVD media, computing a first correction code for the actual data, reading a second correction code from the DVD media, the second correction code pertaining directly to said stored data, and comparing the first and second correction codes to determine whether said actual data needs to be corrected. The method further includes determining whether the number of errors in the actual data exceeds the maximum number of errors that can be corrected, correcting the actual data if possible, counting the number of errors that are corrected, and indicating if errors in a given row or column cannot be corrected.

Abstract: In a code transmission scheme for a communication system using error correcting codes, the transmitting side generates at least one transmitting side syndrome value by carrying out a syndrome calculation for the information to be transmitted, and transmits to a receiving side at least one information packet containing the information to be transmitted and at least one redundant packet containing the transmitting side syndrome value.

Abstract: Techniques for puncturing symbols in a communications system are disclosed. S symbols are received for a frame having a capacity of N symbols, with S being greater than N. P symbols need to be punctured so that remaining symbols fit into the frame. A number of puncture distances, D1 through DN, are computed based on S and P. A particular number of symbol punctures is determined for each computed puncture distance. P1 through PN symbol punctures are then performed at the distances of D1 through DN, respectively. For a more even distribution of the symbol punctures, each of the distances D1 through DN can be selected to be greater than or equal to a minimum puncture distance Dmin defined as Dmin=└S/P┘, where └ ┘ denotes a floor operator. The symbol punctures at each computed distance can be performed together or distributed with symbol punctures at other distances.

Abstract: An encoder, decoder, method of encoding, and method of decoding which preserves the turbo coder performance in the waterfall region, while improving upon performance in the error asymptote region, by applying a parser or other similar element to the input bit stream. The parser assigns input bits to a subset of constituent encoders in a pseudo-random fashion. The parsing strategy breaks up input sequences producing low Hamming weight error events, thereby improving the weight spectrum and asymptotic performance of the code, while not impacting waterfall region performance. The parser or other similar element may also strengthen the weight spectrum without adversely affecting convergence of a corresponding decoder.

Abstract: Advantage is taken of the presence of ordinary parity check bits occurring in the data flow in a computer or other information-handling system to improve error correction capability while at the same time providing simpler decoding. More particularly, the encoding and decoding system, methods, and devices herein include the capability of separating error correction in data bits and in parity check bits. In this regard, it is noted that the present invention therefore provides an improved memory system in which the parity check bits do not have to be stripped off prior to storage of data into a memory system with error correction coding redundancy built in. Instead of these parity check bits being stripped off, they are incorporated into a generalized and generalizable error correction system which produces a significantly simple decoding and error correction structure.

Abstract: A system is described for collecting and displaying summary information from disparate sources. The system provides for user customization of data acquisition parameters for locating articles to be summarized, user customization of parameters for parsing the located source material so as to extract headlines, and user organization of extracted headlines into groups.