Abstract: The mask inspecting apparatus is incorporated into an electron beam proximity exposure apparatus in which a mask is arranged in proximity to a wafer, and a mask pattern formed on the mask is transferred onto a resist layer on the wafer by scanning the mask with an electron beam. The mask inspecting apparatus comprises a scanning electron microscope (SEM) arranged on a wafer stage, and a stage drive device which shifts the wafer stage so that an electron detector of the SEM can receive electrons originating from the electron beam transmitting through the mask pattern of the mask in an inspection of the mask. The SEM thereby captures an image of the mask pattern on the lower face of the mask. Thus, the mask inspection can be performed using an electron beam intended for use in proximity exposure in the electron beam proximity exposure apparatus.

Abstract: Articles, including fabrics and film layers, are disclosed which can protect against multiple hazards, including radiation, chemical, biological agents, metal projectiles and fire hazards. In some embodiments, the fabrics and films of the present invention are used to produce garments having protection against multiple hazards and superior heat dissipating properties. A radiation protective compound is preferably created by mixing a radiopaque material, such as barium, bismuth, tungsten or their compounds, with powdered polymer, pelletized polymer or a liquid solution, emulsion or suspension of a polymer in solvent or water. This radiation protective mixture can then be laminated or otherwise adhered to other types of protective films or fabric, such as the protective polymer films or fabrics used for chemical protective garments, biological protective garments, bullet proof vests or fire retardant garments.

Abstract: A reflective sensor for detecting the presence or absence of the subject to be detected at the detecting position. The reflective sensor is provided with a sensor portion and a filter. The sensor portion includes a light-emitting element that emits light at the detecting position and a light-receiving element that receives light reflected on the subject and generates an electrical signal corresponding to a quantity of received light. The filter is disposed between the sensor portion and the detecting position. The filter is made of a light-transmitting material capable of transmitting light heading to the detecting position from the light-emitting element and light heading to the light-receiving element from the subject, and prevents intrusion of dust into the sensor portion.

Abstract: A device and method for reading out information stored in a storage layer using a receiving device for receiving emission radiation that has been emitted from the storage layer. In this connection the storage layer is supported on a support surface that is defined by an x-y plane and a relative movement is generated between the receiving device and the storage layer in the x direction. The receiving device or the storage layer is guided during the generation of the relative movement by a guide system, on a guide surface that is independent of the storage layer. When guiding the receiving device, the level of the guide surface in a z direction coincides with the level of the support surface in the z direction.

Abstract: A flow control device comprises an inlet port through which fluid is supplied, an outlet port through which the fluid is delivered, a valve body which is arranged in a passage between the inlet port and the outlet port so as to open and close the passage, the flow control device further comprising a valve body guide means which urges downwardly and pulls upwardly the valve body so as to allow the fluid in the passage to flow at a flow rate which is lower than a basic control rate of the flow control device.

Abstract: An apparatus for flow control in an environment that has independent units includes a flow system for carrying a flow with a controller in one of the units. The apparatus operates the controller from at least one location outside the one of the units in response to a supply of power with a terminal for positioning at the location, a connector for connecting the terminal to the controller, and a power supply for supplying power from the terminal through the connector to the controller when the power supply is connected to the terminal and operating the controller therewith.

Abstract: The valve device includes a valve body and a bonnet with a fitting clamped therebetween and extending within body and bonnet bores. The fitting and valve body have bore portions with a valve stem extended therein and through a valve seat and having opposite end portions of the same diameters and in fluid sealing relationship with the above bore portions axially opposite the valve seat. The body has inlet and outlet passages opening to the fitting and body bores axially opposite the valve seat and axially intermediate the stem end portions. A sensor is connected to the valve stem and is movable against spring action to move the valve stem to its open position. An actuator, for example an electric motor, is mounted to the bonnet and operable for forcing the sensor to move the valve stem to its valve open position.

Abstract: A valve comprises a cylindrical body made of a metal material, a screw section formed on a first attachment hole in the body, a first seal member provided on an upper surface of the body, a third seal member attached to an upper surface of the first attachment hole, a valve plug arranged in a second attachment hole for being seated on a valve seat, a flange section curved outwardly from an outer circumferential surface of the body, and a spring interposed between the valve plug and a spring-receiving member provided in the second attachment hole.

Abstract: The invention provides a valve that one may use to finely adjust the amount of fluid that flows to a device such as a portable gas burner. The valve includes a receiver through which fluid flows when the valve is open, a metering groove operable to form a metering passage in the receiver to limit the flow of fluid through the receiver, and a stem positionable relative to the receiver to form the metering passage from different portions of the metering groove to adjust the amount of fluid that may flow through the receiver. The metering groove includes a groove axis that extends the length of the metering groove and cross-sectional areas oriented perpendicular to the groove axis that differ according to their location along the axis. The metering passage is formed from all or a portion of the metering groove, and limits the flow of fluid through the receiver with the smallest cross-sectional area of the metering groove portion that forms the metering passage.

Abstract: The valve with an improved junk ring structure is composed of a main body, a valve disk, a washer and a junk ring. The main body has on one side thereof a stepped surface of which the outermost end has a screw thread portion on the inner wall thereof; the main body has on an inner wall thereof a protrusion. An upper and a lower pivotally connecting block are provided on the valve disk, and are movably connected by an axle provided on the main body. The junk ring has on the outer wall of the periphery thereof a screw thread portion mating with the screw thread portion of the main body. The washer is placed between the main body and the junk ring.

Abstract: A valve stem and gasket apparatus and method includes a gasket that may be made of PEEK. A tool block set can be used to install the gasket over a flange on the stem.

Abstract: Composition spray applied on fabrics to de-wrinkle and refresh while protecting colors which leaves no discernable residue. Quality water, one or more alcohol(s) and one or more surfactant(s) penetrate the fabric weave. One or more acids lower pH to stabilize sensitive dyes, thus ensuring color-safeness. Alcohols hasten drying and fragrances mask alcohol odor and help consumers identify the product. Mechanical action(s) by the user enhances wrinkle removal or imparts shape. Optional malodor-eliminating compounds keep fabrics fresh longer, or refresh malodorous garments. Optional specific quaternary ammonium compound reduces static cling but does not significantly increase residues. The composition de-wrinkles commercial fabrics, and clothing from casual to fine, spray applied using a pre-compression sprayer. The composition is environmentally friendly, safe for use on all types of fabrics, and safe for use at home or commercially.

Abstract: The present invention provides a difluoromethyl ether derivative which shows various suitable physical properties as a liquid crystal compound, a liquid crystal composition comprising the compound and a liquid crystal display element containing the composition, and also provides a simple and efficient process for producing the difluoromethyl ether derivative.

Abstract: It is acknowledged that an electric double layer capacitor is markedly superior in power density and cycle characteristics to a secondary battery. However, a higher energy density is required to apply it to a power supply of hybrid vehicle, electric vehicle or the like. The present inventors have found that a carbonaceous material containing copper or a compound of copper exhibits excellent characteristics as an electrode material for capacitor and can realize a capacitor having a large capacity. In the electrode material and the capacitor, copper or a compound of copper exists in the amount of 0.8 to 30 parts by weight calculated on the metal basis based on 100 parts by weight of the carbonaceous material, particularly preferably.

Abstract: This invention provides a low-temperature sintering conductive paste for high density circuit printing which can form a fine circuit having good adhesive force, a smooth surface and low resistance when applied on a substrate and then baked; the conductive paste of the invention uses, as conductive media, in combination with metal fillers having an average particle diameter of 0.

Abstract: A fencing for preventing insects to enter an open air area comprising a substantially upright structure with a height suitable to prevent low flying insects to enter said open air area. The structure of the fencing is impregnated with an insecticide.

Abstract: A casting form suspendable from a form support and reinforcement member erected on a substrate for forming a cast-in-place columnar member. The form includes a pliable tubular segment open at each of its two ends, an aperture formed annularly through the pliable tubular segment. The pliable tubular segment is positionable about the form support and reinforcement member. A form suspension assembly is attachable to the form support and reinforcement member and the pliable tubular segment and the structural support member for suspending the pliable tubular segment is attachable to the form suspension assembly.

Abstract: The present invention comprises a new nanoscale metal-semiconductor, semiconductor-semiconductor, or metal-metal junction, designed by introducing topological or chemical defects in the atomic structure of the nanotube. Nanotubes comprising adjacent sections having differing electrical properties are described. These nanotubes can be constructed from combinations of carbon, boron, nitrogen and other elements. The nanotube can be designed having different indices on either side of a junction point in a continuous tube so that the electrical properties on either side of the junction vary in a useful fashion. For example, the inventive nanotube may be electrically conducting on one side of a junction and semiconducting on the other side. An example of a semiconductor-metal junction is a Schottky barrier. Alternatively, the nanotube may exhibit different semiconductor properties on either side of the junction.

Abstract: An organic field effect transistor utilizes a bifunctional contact-enhancing agent at various interfaces to improve carrier mobility through the organic semiconductor layer, to improve carrier injection, and to enhance adhesion via a bifunctional mechanism. The contact-enhancing agent can be situated between the gate electrode (2) and the dielectric layer (3) to form a chemical or physical bond between the gate electrode and the dielectric layer. It can also be situated between the dielectric layer and the organic semiconducting layer (4), or between the source and drain electrodes (5, 6) and the organic semiconducting layer.

Abstract: A light emitting device having a plastic substrate is capable of preventing the substrate from deterioration with the transmission of oxygen or moisture content can be obtained. The light emitting device has light emitting elements formed between a lamination layer and an inorganic compound layer that transmits visual light, where the lamination layer is constructed of one unit or two or more units, and each unit is a laminated structure of a metal layer and an organic compound layer. Alternatively, the light emitting device has light emitting elements formed between a lamination layer and an inorganic compound layer that transmits visual light, where the lamination layer is constructed of one unit or two or more units, and each unit is a laminated structure of a metal layer and an organic compound layer, wherein the inorganic compound layer is formed so as to cover the end face of the lamination layer.

Abstract: A vertical organic transistor comprises a substrate, a first electrode positioned over the substrate, a first semiconductor layer formed over the first electrode, a second electrode formed on the first semiconductor layer and shaped into a prescribed pattern, a second semiconductor layer formed over the second electrode and the first semiconductor layer, and a third electrode formed over the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: A semiconductor opto-electronic device according to the present invention has a grating disposed at an electrically passive wafer bonded interface. The device has p and n contacts, and current path between the contacts that does not traverse the wafer bonded interface. The absence of current injection across defective interfaces leads to a device with improved reliability relative to prior art regrowth approaches. The present invention can be combined with vertical and lateral wafer bonding to create grating-based devices with an active/passive transition, such as tunable lasers.

Abstract: Transistor capacitance Cdtr inevitably generated between the gate and the drain of a second TFT is increased. Accordingly, an operation test of a first TFT and the second TFT can be conducted by turning on the first TFT to charge the transistor capacitance Cdtr and detecting the stored charges.

Abstract: A polycrystalline silicon thin film used in a thin film transistor (TFT) and a device fabricated by using the same, in which the uniformity of the TFT and device are improved by providing a polycrystalline silicon thin film of a TFT characterized in that probabilities P1 and P2 in which the maximum number of respective primary crystal grain boundaries for transistors TR1 and TR2 that are arranged perpendicularly to each other can be contained in active channel regions represented as in the following expressions, respectively, and the probability P1 or P2 is not 0.5, and a device using the polycrystalline silicon thin film for the TFT.

Abstract: In a thin film transistor having a semiconductor film provided above a substrate, a gate insulating film covering the semiconductor film, a gate electrode formed on the gate insulating film, and an interlayer insulating film covering the gate electrode, the gate electrode has a tapered shape wherein the width becomes wider from the side of the interlayer insulating film towards the gate insulating film. With this structure, the characteristics are stabilized. The electrode having a tapered shape can be formed through a first etching step wherein etching is applied to an electrode material layer to a degree where at least a portion of the electrode material layer remains and a second etching step wherein etching is applied to the electrode material layer while the mask is being ashed.

Abstract: An electro-optical device includes a TFT, a data line, a scanning line, and a pixel electrode, which are provided above a substrate, a semiconductor layer which constitutes the TFT being connected to the pixel electrode through a relay film. A light-shielding conductive film provided between the data line and the relay film is electrically connected to a capacitor electrode which consists of the same film as the scanning line provided between the relay film and the semiconductor layer at a constant potential, thereby forming a storage capacitor between the films. Therefore, in an electro-optical device of a type in which a light-shielding film against incident light is provided above pixel switching TFT, and a light-shielding film against returned light is provided below the TFT, the pixel aperture ratio can be increased, and the storage capacitor can be enlarged.

Abstract: A thin film transistor includes a substrate having an upper side; a plurality of parallel-connected active layers supported on the upper side of the substrate; spaces defined between the substrate and the active layers; a first insulating layer on the plurality of active layers; a gate electrode on the first insulating layer over the plurality of active layers; and source and drain electrodes contacting the plurality of the active layers. The active layers of the thin film transistor are laser annealled to polycrystalline silicon. The spaces result in large polysilicon grains that result in good electrical characteristics.

Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.

Abstract: An active matrix organic electro luminescence display panel device includes a substrate, at least one low refractive thin film formed on the substrate, and an organic electro luminescence diode formed on the low refractive thin film to selectively emit light. Also, a method of fabricating an active matrix organic electro luminescence display panel device includes the steps of forming at least one low refractive thin film on a substrate, and forming an organic electro luminescence diode on the low refractive thin film to selectively emit light.

Abstract: A light emitting diode and manufacturing method thereof. The light emitting diode comprises a n-type semiconductor layer formed on a substrate, an active layer formed on the n-type semiconductor layer, a p-type cladding layer formed on the active layer, and a hydrogen-adsorbing layer formed on the p-type cladding layer. The hydrogen-adsorbing layer adsorbs the hydrogen atoms near the interface to the p-type cladding layer, thereby enhancing the doping concentration of p-type cladding layer, and forming a low-resist ohmic contact by which the performance and reliability of opto-electronic devices is improved.

Abstract: Recesses interrupt an active layer on a semiconductor chip to improve the coupling out of light. As a result, side faces of the active layer appear, as seen from a light-generating point, at a large solid angle and the paths of light in the active layer are shortened.

Abstract: A unit according to the present invention includes a substrate and an IC chip used for driving a light-emitting device. A relay terminal is provided at a region spaced from peripheral areas of the substrate so as to connect the light-emitting device with the IC chip. The relay terminal is connected with a corresponding terminal of the IC chip via a connecting channel such as wire-bonding. The light-emitting device is supported by the substrate such that a terminal of the light-emitting device is electrically connected with the relay terminal. A length of a wiring line between the light-emitting device for an optical pick-up and the unit used for driving the light-emitting device is decreased.

Abstract: The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for undersized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.

Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

Abstract: Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of a heavily doped P+ contact area residing in an N well region on a P substrate and electrically connected to the input pad of active integrated field effect transistor devices. NFET devices with floating gates and drains to reduce capacitance are located in the substrate near the N-well. The NFET source elements as well as the substrate are connected to ground. The NFETs are isolated from the N-well and associate P+ contact area by shallow trench isolation (STI) structures that reduce the NFET drain to substrate and N-well to substrate junction boundary area with a subsequent reduction in the junction capacitance. A voltage pulse from an ESD event will cause the SCR structure and associated parasitic bipolar transistors to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of word lines and a plurality of bit lines for the row by row and column by column driving of a matrix of switching elements. In this case, a plurality of electrically conductive connection strips for connecting source and drain regions in the active region to the respective bit lines are formed between the word lines such that they directly make contact with the source and drain regions at the surface of the semiconductor substrate in the active region. In this way, a particularly compact cell area is obtained in conjunction with very simple lithographic conditions.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a disposable gate on a semiconductor substrate in a region where a gate electrode is to be formed, forming a sidewall spacer on a sidewall of the disposable gate, forming a source and drain in the semiconductor substrate using the disposable gate and the sidewall spacer as a mask, forming an interlevel insulating film on the semiconductor substrate so as to cover the disposable gate, planarizing an upper surface of the interlevel insulating film to expose upper surfaces of the disposable gate and the sidewall spacer, removing the disposable gate to form a trench portion having a side surface formed from the sidewall spacer and a bottom surface formed from the semiconductor substrate, depositing a gate insulating film on the semiconductor substrate so as to cover the bottom surface and side surface of the trench portion, forming a gate electrode buried in the trench portion, and removing the sidewall spacer and the gate insulating

Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.

Abstract: A three-dimensional semiconductor device includes a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits to control a portion of the circuit blocks.

Abstract: The semiconductor memory device comprises a glue layer defining a cylinder shell, a bottom electrode made of a material of the platinum group and covering the inner face and the outer face of the cylinder shell, a dielectric layer formed over the bottom electrode, and a top electrode positioned over the dielectric layer. The bottom electrode, the dielectric layer, and the top electrode comprise a cell capacitor.

Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

Abstract: A metal film formed of a first metal having relatively high oxygen absorption properties on a silicon region, and then depositing a high dielectric constant film formed of an oxide of a second metal having relatively low oxygen absorption properties on the metal film. Thereafter, a conductive film is formed on the high dielectric constant film and then the conductive film is patterned, thereby forming an electrode.

Abstract: The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer.