Abstract: Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.

Abstract: A semiconductor integrated circuit apparatus having a planar capacitor can use a plurality of source voltages therein. According to the semiconductor integrated circuit apparatus, it is possible to not only control thresholds of individual MOS transistors but also reduce the threshold voltage of the planar capacitor without any additional fabrication process. The semiconductor integrated circuit apparatus includes a p-channel memory transistor and a capacitor in a first n-type element region, an n-channel low-voltage MOS transistor in a second p-type element region, and an n-channel high-voltage MOS transistor in a third p-type element region. A channel region of the second MOS transistor is doped under a high density profile by using a p-type impurity element. At the same time, the p-type impurity element is imported in a capacitor region of the first element region under the substantially same profile.

Abstract: Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Abstract: The semiconductor device comprises an intermediate layer formed on a semiconductor substrate 6, the intermediate layer 12 being formed of an oxide containing a first element which is either of a III group element and a V group element, an insulation film formed on the intermediate layer, the insulation film being formed of an oxide of a second element which is the other of the III group element and the V group element, and an electrode 16 formed on the insulation film. Because the intermediate layer of the oxide containing the first element is formed, even when the gate insulation film is formed of Al2O3 or others, the interface state density can be depressed to be low. Thus, the semiconductor device can have low interface state density and small flat band voltage shift even when Al2O3, etc. is used as a material of the insulation film.

Abstract: A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.

Abstract: A switching device for integrated circuit applications is disclosed. A first switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. Said first and second devices are constructed as complementary Gated-FET devices, wherein the conductive path of a Gated-FET comprises a resistive channel of the same dopant type as source and drain regions. A second switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. The conductive paths of said first and second devices are comprised of a single geometry of a semiconductor material.

Abstract: In a silicon-on-insulator (SOI) wafer and a method of manufacturing the same, the SOI wafer includes a first semiconductor wafer including an isolation insulating film formed to define an active region; a well region and a buried layer formed in the active region of the first semiconductor wafer; and a second semiconductor wafer bonded with the first semiconductor wafer, wherein an SOI insulating film, which contacts a lower portion of the isolation insulating film and electrically insulates a lower portion of the active region, is formed.

Abstract: The sources or drains 14 of transistors and photodiodes 13, which constitute shaded pixels covered with a shading layer 16, are formed on a surface of a highly doped well 20 provided on a lowly doped substrate 11. Therefore, a potential barrier &Dgr;V is formed extended from the lowly doped substrate 11 toward the highly doped well 20. Even if intense spot light is made incident on some of light-receiving pixels and part of light 17 reaches a neutral region of the lowly doped substrate 11, part of diffused charges 18 photoelectrically converted there cannot intrude into the highly doped well 20. Therefore, an output signal level of the shaded pixels does not change, and a black reference level can be maintained.

Abstract: There is provided a semiconductor device able to prevent performance degradation of an inductor element provided thereon. A high resistance region is provided below the inductor element formed on the semiconductor substrate. The high resistance region is formed deeper than the well regions of the p-channel and n-channel MOS transistors, thus preventing induction of an eddy current by the magnetic flux generated from the inductor element.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Abstract: A p−−-type impurity layer is provided at a position located below n−-type impurity layers which are to become the drain of a MOSFET. Although the p−−-type impurity layer is of the same conductivity type as a semiconductor substrate, the p−−-type impurity layer is lower in doping level than the semiconductor substrate. The p−−-type impurity layer is formed so as to be joined to an n−-type impurity layer and such that the dosage of p-type impurity (i.e., the amount of included impurity) becomes higher with increasing distance from the thus-formed junction. The dosage of the area located in the vicinity of the junction is made lower, thereby rendering a depletion layer easy to spread when a drain voltage is applied. Thus, capacitance Cds developing between the drain and the substrate is reduced, and the operating speed of the MOSFET increases.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: A method of forming a dual-implanted gate and a structure formed by the same. Stack structures comprising a polysilicon layer, a sacrificial layer and a mask layer are formed over a substrate with a gate oxide layer thereon. A dielectric layer is formed over the substrate covering the stack structures. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure. The mask layer is removed to form a plurality of trenches. The stack structures are selectively implanted using ions having different electrical states. The sacrificial layer is removed. Thereafter, a barrier layer is formed over the interior surface of the trenches. A metallic layer is formed over the substrate completely filling the trenches. The dielectric layer is removed to form a plurality of gate structures. Spacers may on the sidewalls of the gate structures as well.

Abstract: Disclosed herein is a magneto-resistive device which has a high reproducing output and is suitable for use as CPP-GMR. The magneto-resistive device has a first magnetic layer, a second magnetic layer, and a non-magnetic spacer formed between said first and second magnetic layers, such that said first magnetic layer contains a magnetic material whose conduction electrons belong to a first energy band and said second magnetic layer contains a magnetic material whose conduction electrons belong to a second energy band, with said first and second energy bands being attributable to orbitals of the same kind, thereby increasing the ratio of change in magnetoresistance and adjusts electric resistance.

Abstract: Semiconductor devices formed in fully or partially compensated semiconductor, (substrate or epi-layer), including minimal current flow voltage switching devices with at least one junction which is rectifying when the semiconductor is caused to be N or P-type by the presence of applied gate voltage field induced carriers, such as inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems.

Abstract: An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a manner spatially isolated from the source electrode zone. The particular integration structure of the MOS power transistor avoids a parasitic drain-bulk diode, a parasitic body diode and a substrate diode and thereby achieves an area-saving protection against over-currents in the event of reverse voltage polarity between drain and source.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: Flash memory devices are provided including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a).

Abstract: Disclosed is a programmable element including a semiconductor material doped with a dopant that alters the resistance of the element when exposed to actinic radiation. Rather than producing a mechanical deformation, the radiation rearranges the bonding configuration of the dopant in the element, allowing it to be placed on a chip in close proximity to other device structures without risking damage to those structures. After formation, the programmable element is subjected to a laser anneal process in which the dopant is electrically activated. The activation process allows the dopant to donate a charge carrier to the crystal structure. Rapid cooling following laser anneal preserves the desired bonding configuration of the dopant produced in the programmable element. Laser anneals have been shown to reduce the resistivity of a programmable element by at least a factor of two.

Abstract: Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods.

Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

Abstract: A vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The transistor includes a heterostructure alloy region positioned in the substrate and comprised of a heterostructure alloy of silicon and germanium. A base region is positioned in the substrate above the first conducting region and doped with P-type impurities. A first dielectric layer is positioned on, and directly contacts, the heterostructure alloy region, and defines a first window directly above the heterostructure alloy region. The transistor also includes an emitter positioned in the heterostructure alloy region and between the first window and the base region. The emitter is comprised of the heterostructure alloy doped with impurities of the first type and directly contacts the first dielectric layer.

Abstract: The semiconductor substrate comprises a silicon substrate 10, a silicon germanium layer 12 formed on the silicon substrate; and a silicon layer 14 formed on the silicon germanium layer. At least one of an isotope composition ratio of one Si isotope and an isotope composition ratio of a Ge isotope of at least one of the silicon substrate, the silicon germanium layer and the silicon layer is above 95%. In at least one of the silicon substrate, the silicon germanium layer and the silicon layer, at lest one of an isotope composition ratio of one Si isotope and an isotope composition ratio of one Ge isotope is set higher, whereby the heat can be scattered in the direction horizontal to the substrate plane. Thus, the semiconductor substrate can have higher heat radiation.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (110a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (110a) increases the number of interconnections between the metal area (110a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: The invention includes a semiconductor device, and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit. A semiconductor wafer 50 is etched using a potassium iodide or ammonium iodide solution. By the etching, a barrier metal layer 48 is removed while the upper face of a bump 10 is simultaneously roughened and many prominences 12 are formed. The formation of the prominences 12 increases the surface area of the upper face of the bump 10 and improves the bonding between the bump 10 of the semiconductor chip and the lead of the film tape carrier.

Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink for removal following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract: A lead-frame-based semiconductor package and a fabrication method thereof are proposed. The semiconductor package includes: a lead frame having a plurality of first and second leads, wherein each first lead is formed with an extending portion smaller in thickness than the first lead in a manner that, an upper surface of the extending portion is flush with an upper surface of the first lead, and a lower surface of the extending portion forms a height difference with respect to a lower surface of the first lead; a chip mounted over the upper surfaces of the extending portions, and electrically connected to the leads by bonding wires; an encapsulant for encapsulating the upper surfaces of leads, upper surfaces of extending portions, chip and bonding wires; and a non-conductive material applied over the lower surfaces of extending portions, wherein the lower surfaces of leads are exposed to outside of the non-conductive material.

Abstract: An optical apparatus includes an optical semiconductor device and a lens assembly mounted on opposite surfaces of a substrate. The height of a surrounding wall and the thickness of a cover member of a semiconductor package of the optical semiconductor device are selected so that, when the cover member and the lens assembly abut directly against the opposite surfaces of the substrate, an optimum optical distance will be formed between a lens set of the lens assembly and a light-sensing portion of an optical semiconductor chip in the semiconductor package. A method for making the optical apparatus is also disclosed.

Abstract: A semiconductor package with a reinforced substrate and a fabrication method of the substrate are provided. The substrate is formed of a metal core layer with relatively high rigidity, and an insulating layer is coated on at least a surface of the core layer. At least a ground via is formed through the insulating layer, allowing a chip mounted on the substrate to be electrically connected and grounded to the substrate by the ground via. The reinforced substrate provides the semiconductor package with sufficient mechanical strength, and can be reduced in thickness in favor of package profile miniaturization. Moreover, the substrate made of the metal core layer and insulating layer has a relatively small dielectric constant to facilitate electron transmission velocity, thereby improving electrical quality of the semiconductor package. Furthermore, the metal core layer is made of a thermally-conductive metallic material, and enhances heat dissipating efficiency of the semiconductor package.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.

Abstract: There is provided a semiconductor device that is capable of reducing wring density of the wiring pattern on a mounting board on which it is mounted, thereby facilitating routing of the wiring pattern. Pads are formed which are connected to pads on a bare chip by bonding wires. There are formed vias extending from the respective pads to a bottom surface of a package, and vias extending from the respective pads to a top surface of the package. This makes it possible to connect the mounting boards to the top and bottom surfaces of the package, thereby enabling reduction of the wiring density of wiring patterns on the mounting boards, thereby facilitating routing of the wiring patterns on the mounting boards.

Abstract: A semiconductor package with a heat sink is provided, wherein a substrate is formed with a metal core layer and at least an opening that penetrates through the substrate. At least a semiconductor chip is mounted on the substrate, with bond pads formed on the semiconductor chip being exposed to the opening, so as to allow the semiconductor chip to be electrically connected to the substrate by a plurality of gold wires that are bonded to the bond pads and formed through the opening. The metal core layer of the substrate provides a grounding plane to improve electrical quality of the semiconductor package, and acts as a heat sink to enhance heat-dissipating efficiency of the semiconductor package. Moreover, an encapsulant for encapsulating the semiconductor chip contains a plurality of thermally conductive metal particles to further facilitate dissipation of heat produced from the semiconductor chip.

Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.

Abstract: A first conductive film is first deposited on an insulating film on a substrate as a seed layer, wetting layer, adhesive layer or the like. The first conductive film is formed from a first copper alloy having oxidation resistance. A second conductive film is then formed on the first conductive film. The second conductive film is formed from copper or a second copper alloy. Thereafter, the first and second conductive films are integrated into a third conductive film, which will results in a wiring.

Abstract: A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film (102) and a copper containing metallic film (103) can be formed within an insulating film (101). An interlayer insulating film (104 or 104a and 104b) can be formed thereon. An upper layer wiring made from a barrier metal film (106 or 106a and 106b) and a copper containing metallic film (111 or 111a and 111b) is formed within the interlayer insulating film (104 or 104a and 104b). A silver containing metallic protective film (108a and 108b) can be formed on surfaces of the lower layer wiring and upper layer wiring.

Abstract: Methods of forming a contact to a gate electrode or substrate despite misalignment of the contact opening due to lithographic techniques, and a semiconductor having such a contact. Silicide can be created on the gate and/or diffusion using the invention.

Abstract: First semiconductor chip is die-bonded on mount substrate, a plurality of high bumps and a plurality of low bumps are formed on second semiconductor chip, and the second semiconductor chip is face-down bonded on the mount substrate and the first semiconductor chip.

Abstract: An IC chip/substrate assembly bonded together by a non-conductive adhesive and a method for forming the assembly. The assembly consists of an IC chip that has bumps formed on an active surface, a substrate that has bond pads formed on a top surface, wherein at least one of the IC chip and the substrate has dummy bumps formed in-between the bumps or the bond pads, and a non-conductive adhesive disposed in between and bonding the IC chip and the substrate together in a face-to-face relationship with the bumps in electrical communication with the bond pads.

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract: An apparatus and method for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff therebetween. Wire bonds may then be formed between bond pads on the semiconductor die and conductive pads or terminals on the carrier substrate. With this arrangement, a dielectric filler material is disposed in the gap or standoff to form a permanent bonding agent between the semiconductor die and the carrier substrate. By applying the dielectric filler material after forming the wire bonds, the dielectric filler material coats at least a portion of the wire bonds to stabilize the wire bonds and prevent wire sweep in an encapsulation process, such as transfer molding, performed thereafter.