Abstract: An array substrate for a transflective liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line, the gate line and the data line defining a pixel region having a transmissive portion and a reflective portion; a gate electrode connected to the gate line; source and drain electrode spaced apart from each other over the gate electrode, the source and drain electrode being spaced apart from each other, the source electrode being connected to the data line; a reflective layer having the same layer as the source and drain electrodes, the reflective layer being disposed in the pixel region and having a transmissive hole corresponding to the transmissive portion; and a pixel electrode connected to the drain electrode, the pixel electrode being disposed in the pixel region, wherein the source and drain electrodes and the reflective layer have multiple layers of metal, wherein a top layer of the multiple layers includes a reflective metallic material.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate; a plurality of storage conductors formed on the substrate, each storage conductor including a plurality of branches; a gate insulating layer formed on the gate line and the storage conductor; a semiconductor layer formed on the gate insulating layer; a data conductor formed on the semiconductor layer; a passivation layer formed on the data conductor; and a pixel electrode formed on the passivation layer, wherein at most one of the branches of each storage conductor has an isolated end.

Abstract: An object of the present invention is to provide a semiconductor device using a cheap glass substrate, capable of corresponding to the increase of the amount of information and further, having a high performance and an integrated circuit capable of operating at a high rate. A variety of circuits configuring an integrated circuit are formed on a plurality of glass substrates, the transmission of a signal between the respective glass substrates is performed by what is called an optical interconnect using an optical signal. Concretely, alight emitting element is provided on the output side of a circuit disposed on the upper stage formed on one glass substrate, and a photo-detecting element is formed so as to oppose to the relevant light emitting element on the input side of a circuit disposed on the rear stage formed on another glass substrate.

Abstract: In a light-emitting semiconductor component having a thin-film stack (30) having an active layer (34) and front- and rear-side contact regions (40, 42), which are formed on a front side (60) and a rear side (62) of the thin-film stack (30) and serve for impressing current into the active layer (34), the thin-film stack (30) has a light generation region (50), in which photons are generated by recombination of charge carriers, and has a light coupling-out region (54), in which light is coupled out from the component. The light generation region (50) and the light coupling-out region (54) are at least partly separated from one another in the plane of the thin-film stack (30).

Abstract: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1−X−Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite to the first conductivity type.

Abstract: The invention provides a semiconductor integrated circuit which allows a plurality of devices to be integrated compactly, that is, with high density; a signal transmitting device; an electro-optical device; and an electronic apparatus. A semiconductor integrated circuit includes tile-shaped microelements that are superimposed upon and adhered to the top surface of a substrate with an adhesive.

Abstract: A novelty light assembly includes a transparent substrate, a light source embedded in the substrate and configured to emit light that propagates through the substrate, an object embedded in the substrate and configured to modify light propagating through the substrate, and a light control circuit embedded in the substrate and configured to control the light source. The circuit alters the wavelength and/or intensity of the each light source independently of the other light sources. A method of making the light assembly is also provided.

Abstract: An apparatus in which a device electrode pad in an electronic device and a connecting conductor pattern in a substrate are connected to each other through a plurality of wire thin lines which differ from one another in mechanical characteristic frequencies. Even if the frequency of vibration applied to the apparatus from the exterior coincides with the characteristic frequency of the given wire thin line so that the wire thin line is broken, it does not coincide with the characteristic frequency of the other wire thin line. Accordingly, no resonance phenomenon occurs in the other wire thin line, thereby reducing a probability that the wire thin line is broken.

Abstract: An apparatus comprising (i) an input circuit configured to provide a predetermined voltage tolerance in response to a plurality of control signals and (ii) a control circuit configured to generate the plurality of control signals in response to one or more input signals.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: When a current mirror circuit is composed of transistors that inevitably form a parasitic photodiode between an epitaxial layer and a substrate layer because of structure of an integrated circuit, a photocurrent increases in proportional to an area of the epitaxial layer. Thus, the area of the epitaxial layer is adjusted in accordance with a current ratio of the current mirror, so as to allow the photocurrent to affect equally on both input and output sides of the current mirror circuit, i.e., so as to cancel the photocurrent. With this, in a current mirror circuit provided in an integrated circuit, it is possible to eliminate the influence of the photocurrent, without considerably increasing an element area or taking special measures to shield light.

Abstract: Semiconductor devices, e.g., heterojunction field effect transistors, fabricated with silicon-germnanium buffer layer and silicon-carbon channel layer structures. The invention provides a method of reducing threading defect density via reducing germanium content in a SiGe relaxed buffer layer on which a strained silicon channel layer is formed, by forming the strained silicon channel layer of a silicon-carbon alloy, e.g., containing less than about 1.5 atomic % C substitutionally incorporated in the Si lattice of the alloy.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

Abstract: A method of forming resistance changing elements with improved operational characteristics for use in memory devices and the resulting structures are disclosed. A chalcogenide glass having the formula (Gex1Se1−x1)1−y1Agy1, wherein 18≦x1≦28, or the formula (Gex2Se1−x2)1−y2Agy2, wherein 39≦x2≦42, and wherein in both the silver is in a concentration which maintains the germanium selenide glass in the glass forming region is used in a memory cell. The glass may also have a glass transition temperature (Tg) near or higher than typical temperatures used for fabricating and packaging memory devices containing the memory cell.

Abstract: A semiconductor memory apparatus that stores data by accumulating charges in its capacitor is provided for allowing itself to be operated at a low potential and at a high speed. In the semiconductor memory apparatus, before performing a precharge by a precharging circuit 10 for the next cycle of read and write, a forced step-down circuit 11 previously lowers the potential of the bit line BL charged on the high side to a level within the range of preventing data of positive charges written and stored in a memory cell MC from being disappeared.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Abstract: A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (“epi”) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

Abstract: A storage capacitor has a double cylinder type structure, with a small cylinder in a lower part thereof and a cylindrical lower electrode structure disposed on the cylindrical contact plug. A method of fabricating the storage capacitor includes: forming a contact hole for exposing an activation region of a transistor; depositing a conductive film to form within the contact hole a contact plug of the storage capacitor having a void therein; opening an upper part of the void of the contact plug; and covering a surface of the device with material to form the storage capacitor electrode, to obtain the storage capacitor electrode having a double cylindrical structure.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.

Abstract: A semiconductor memory device includes a silicon substrate with a gate and contact pads at both sides of the gate, an inter-insulation layer formed on the substrate, including a storage node contact and a bit-line contact exposing a corresponding contact pad, and including a groove-shaped bit-line pattern, a storage node contact plug formed in the storage node contact, and a damascene bit line formed within the bit-line pattern and connected with the exposed corresponding contact pad through the bit-line contact.

Abstract: A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type polysilicon layer, is disposed in the upper trench and insulated from the substrate. A first insulating layer is disposed between the trench capacitor and the control gate. A first doped region is formed in the substrate around the first insulating layer and a second doped region is formed in the substrate around the second conductive layer.

Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.

Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: A triple poly nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector may provide electrons for substrate hot electron injection of electrons onto the floating gate for programming. The select transistor may include a gate formed as a self-aligned sidewall spacer on said sense transistor.

Abstract: A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.

Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

Abstract: A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface coincides with the surface of the drain zone facing the source zone, such that the regions of the first and second conductivity type nested inside each other reach the drain zone.

Abstract: A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.

Abstract: A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.

Abstract: A semiconductor substrate, for forming a circuit pattern of a semiconductor chip, comprised of a substrate, an insulating film formed on the substrate, and a semiconductor layer formed on the insulating film, wherein the semiconductor layer is isolated by the insulating film for every region formed with a circuit pattern of a semiconductor chip, able to be generally used even if a silicon on insulator or semiconductor on insulator (SOI) layer is isolated by an insulating film, and a process of production of an SOI substrate, enabling a reduction of thickness of the SOI layer and able to suppress the manufacturing costs and variation in the thickness of the SOI layer, comprising forming a groove in a first substrate made of a semiconductor, forming a first insulating film in the groove and on the first substrate, injecting hydrogen ions to form a peeling layer, bonding a second substrate, peeling off the first substrate by heat treatment while leaving the semiconductor layer, and polishing the semiconductor la

Abstract: A Semiconductor sensor device for the detection of target molecules and molecular interactions, based on Silicon-on-Insulator (SOI) technology.

Abstract: A semiconductor substrate that suppresses not only auto doping but also warpage can be provided by disposing an oxide film (4) at a position in a semiconductor substrate (1), so as to be apart from a main surface (1a) and a reverse surface (1b).

Abstract: A new device for shunting electrostatic discharge (ESD) energy from a pad of an integrated circuit device has been achieved. The device comprises, first, a substrate of a first dopant type. A plurality of source junctions of a second dopant type are in the substrate. A silicide layer overlies all of each of the source junctions and this silicide layer is in contact with a first conductive layer that is a ground reference. A plurality of drain junctions of the second dopant type are in the substrate. The silicide layer overlies all of each of the drain junction and this part of the silicide layer is in contact with a second conductive layer that is connected to the pad. Finally, a gate comprising a third conductive layer overlies the substrate between each of the source junctions and the drain junctions with an insulating layer therebetween. The gate is connected to the ground reference.

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

Abstract: A semiconductor device includes an element separating insulating film provided on a semiconductor substrate to separate an element region. A gate electrode is arranged above the element region. Source/drain regions are formed in the semiconductor substrate to sandwich a region below the gate electrode. A silicide film is provided on the source/drain regions, extending onto the element separating insulating film. A contact hole extends through the interlayer insulating film, which is provided on the element separating insulating film and the silicide film, and reaches the silicide film. Ends of the contact hole are positioned on the silicide film and on the element separating insulating film. The contact hole includes a trench portion whose one end contacts with the edge of the silicide film in the bottom of the contact hole and in an upper portion of the element separating insulating film. A wiring layer is arranged in the contact hole.

Abstract: The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

Abstract: CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.

Abstract: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A hydrogen concentration and a nitrogen concentration in the film can be increased by the increase of the flow rate of H2. Besides, the hydrogen concentration and the nitrogen concentration in the film can be decreased to heighten an oxygen concentration by the increase of the flow rate of N2O. The gate insulating film ensures the stability and reliability of the characteristics of the TFT, such as the threshold voltage (Vth) and sub-threshold constant (S value) thereof.

Abstract: The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of S, Te and Se. A second layer is over the first layer. The second layer comprises M and A, where M is a transition metal and A is one or more of O, S, Te and Se. A third layer is over the second layer, and comprises Ge and one or more of S, Te and Se. The first, second and third layers are together incorporated into an assembly displaying differential negative resistance. Additionally, the invention includes methodology for forming assemblies displaying differential negative resistance, such as tunnel diode assemblies.

Abstract: An integrated sensor and electronics package wherein a micro-electromechanical sensor die is bonded to one side of the package substrate, one or more electronic chips are bonded to an opposite side of the package substrate, internal electrical connections run from the sensor die, through the package substrate, and to the one or more electronic chips, and input/output connections on the package substrate are electrically connected to one or more of the electronic chips.

Abstract: The invention includes a magnetoresistive memory device having a conductive core, and a first magnetic layer extending at least partially around the conductive core. A non-magnetic material is over at least a portion of the first magnetic layer and separated from the conductive core by at least the first magnetic layer. A second magnetic layer is over the non-magnetic material, and separated from the first magnetic layer by at least the non-magnetic material. The invention also includes methods of forming magnetoresistive memory devices.

Abstract: An active matrix substrate forms a liquid crystal display panel together with a counter substrate and liquid crystal filling a gap therebetween, and color filters are covered with an overcoat layer of photo-sensitive acrylic resin, wherein column spacers of the photo-sensitive acrylic resin project from the overcoat layer so that the column spacers are hardly separated from the overcoat layer in a rubbing for producing an orientation layer.

Abstract: There is disclosed a photoelectric conversion device which is manufactured by depositing numerous crystalline semiconductor particles of one conductivity type on a substrate having an electrode of one side to join the crystalline semiconductor particles to the substrate, interposing an insulator among the crystalline semiconductor particles, forming a semiconductor layer of the opposite conductivity type over the crystalline semiconductor particles, and connecting an electrode to the semiconductor layer of the opposite conductivity type, in which the insulator comprises a mixture or reaction product of polysiloxane and polycarbosilane. The insulator interposed among the crystalline semiconductor particles is free from defects such as cracking and peeling, so that a low cost photoelectric conversion device with high reliability can be provided.