Abstract: A system that enables a memory controller to control data transfers with memory modules, such as DIMMs (double in-line memory modules), of either a “by 4” (×4) type or a non-by-4 type (non-×4). Both ×4 and non-×4 DIMMs may be used in the system simultaneously, and the memory controller dynamically adjusts its enable and other signals as needed. Data strobe signals are provided to and from DIMMs over a data strobe transfer circuits which in the case of a non-×4 DIMM handles data strobes for an entire byte of data, while in the case of ×4 DIMM the data transfer circuit handles data strobes for one nibble (four bits) of a byte of data. A hybrid data mask/data strobe transfer circuit handles the other nibble of a byte of data in the case of data transfers for ×4 DIMMs, and handles data mask signals for write operations for non-×4 DIMMs.

Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.

Abstract: In a storage system, a logical volume is divided into a plurality of small areas called logical storage devices and only such an area designated by a user is made an object of remote copying or migratory copying. Also, there is provided a unit for forming a logical volume from any logical storage device of any RAID group. Thereby, the reduction of the deterioration in performance at the time of remote copying, the reduction of a storage area to be assigned to a secondary site as a copy destination, the shortening of a time required for migratory copying and the assignment of any area of a logical volume on any RAID group are enabled.

Abstract: A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

Abstract: In a system with hardware main memory compression, the method of this invention monitors the physical memory utilization and if physical memory is near exhaustion it forces memory to be paged out, thus freeing up real memory pages. These pages are then zeroed, thus they are highly compressible and therefore reduce the physical memory utilization. Pages that have been forced out due to high physical memory utilization are not made available for allocation. In systems where operating system changes are permitted, this invention dynamically controls the minimum size of the free page pool and zeros pages upon freeing. When the physical memory utilization falls below a critical threshold the mechanism reduces the minimum size of the free pool to allow further allocation. In systems where operating system changes are not possible, pages are allocated by a module (e.g. Device driver) and then zeroed.

Abstract: Methods and apparatus for enabling an efficient generational scavenging garbage collection to be performed on a managed memory area are disclosed. According to one aspect of the present invention, a method for reclaiming memory space uses a managed memory area that includes a first area and a second area. The first area is arranged to store recently allocated objects, while the second area being arranged to store older objects. The method includes determining when a first section of the first area in which new objects are to be allocated is substantially filled. When it is determined that the first section is substantially filled, a garbage collection is performed on a second section of the first. After the garbage collection, the second section is set to support new object allocation such that new objects are allocated in the second section, while the first section is reset such that it is no longer arranged to support new object allocation.

Abstract: The present invention is directed to a method and system for expanding volume capacity. A method of expanding volume capacity on a storage device may include receiving a request to expand capacity of a target volume by a requested amount. A first hierarchy is queried for unused capacity, wherein if unused capacity is at least one of greater than or equal to the requested amount, the unused capacity is positioned within the target volume. If unused capacity is less than the requested amount, at least one successive hierarchy is queried to locate unused capacity, which is at least one of greater than or equal to the requested amount, the successive hierarchy located at a logic block address further from a target volume logic block address than a first hierarchy logic block address. The unused capacity is then positioned to be included with the target volume.

Abstract: A method of block formatting a first data storage medium in or to be added to an array of data storage media to a desired block format is provided comprising the steps of sensing a current block format of the first data storage medium that is different from the desired block format, flagging the first data storage medium with the current block format different from the desired block format, and block formatting the flagged data storage media, wherein at least one of the step of sensing a current block format and the step of block formatting the flagged data storage media is based on a criteria.

Abstract: A method and apparatus is provided for measuring and optimizing the orientation of data access of an electronic storage device according to data access characteristics. Monitoring storage access activity in an area of storage space is performed to gather data pertaining to one or more storage access characteristics. Measuring is performed of the characteristics of the storage access activity of at least two individual portions of the storage space. The portions are then combined in a manner to more judiciously utilize storage space. Depending on their homogeneity of access characteristics, the individual portions may then be left alone, merged with other similar portions, or further subdivided into sub-portions, which may be further merged, divided or left alone. At each merger or division determinations can then be made of whether the characteristics of storage access activity of one individual portion or sub-portion are similar to that of another portion according to predetermined criteria.

Abstract: A storage management system in which a plurality of volume providers maps logical storage volumes onto one or more storage devices within a stand-alone computer or within a storage network. A common volume manager executing on a computer within the storage network selectively communicates commands to one or more of the volume providers in order to control the storage devices. The inventive storage management system seamlessly integrates management of the vendor-specific volume providers. The common volume manager provides a common application programming interface (API) by which applications are able to control and monitor hardware and software volume providers without requiring detailed knowledge of the volume providers or the underlying storage devices. The common volume manager aggregates response information from the volume providers and communicates the aggregated information to the software application that issued the storage management request.

Abstract: A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.

Abstract: In an address translation buffer, multiple content-addressable memories of a first memory array store previous process identifiers for comparing them with a new process identifier to produce a first output signal when a coincidence is detected and a second output signal when a coincidence is not detected. Multiple drivers are associated respectively with the memories of the first memory array. Power saving of the drivers is achieved by having each driver pull up its output line as an indication of a match only when the first output signal of the associated memory coincides with a precharge signal and pull down its output line in response to a discharge signal when the associated memory subsequently produces the second output signal. Multiple content-addressable memories of a second memory array correspond respectively to the drivers.

Abstract: In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.

Abstract: This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.

Abstract: An apparatus and method to provide ordering when an advanced load address table is used for advanced loads. An advanced load address table (ALAT) is used to retain an entry associated with a location accessed by an advanced load instruction. The entry is utilized to determine if an intervening access to the location is performed by another instruction prior to the execution of a corresponding checking instruction. Ordering is maintained to ensure validity of the entry in the ALAT, when the advanced load instruction is boosted past an ordering setting boundary.

Abstract: One embodiment of the present invention provides a system that prefetches instructions by using an assist processor to perform prefetch operations in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version of the executable code executes more quickly than the executable code, and performs prefetch operations for the primary processor in advance of when the primary processor requires the instructions. The system also stores the prefetched instructions into a cache that is accessible by the primary processor so that the primary processor is able to access the prefetched instructions without having to retrieve the prefetched instructions from a main memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into executable code for the primary processor.

Abstract: A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions.

Abstract: Causality-based memory ordering in a multiprocessing environment. A disclosed embodiment includes a plurality of processors and arbitration logic coupled to the plurality of processors. The processors and arbitration logic maintain processor consistency yet allow stores generated in a first order by any two or more of the processors to be observed consistent with a different order of stores by at least one of the other processors. Causality monitoring logic coupled to the arbitration logic monitors any causal relationships with respect to observed stores.

Abstract: A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.

Abstract: Methods for emulating an instruction set extension, comprising providing data to be operated upon, executing a first instruction with respect to a first portion of the data without committing the results of the first executed instruction, if no unmasked exceptions occur with respect to the first portion of the data, executing a second instruction with respect to a second portion of the data, and if no unmasked exceptions occur with respect to the second portion of the data, committing the results of the second executed instruction and again executing the first instruction with respect to the first portion of the data. If the first instruction is executed again, its results are committed. A handler is invoked if an unmasked exception occurs.

Abstract: A method for automatically installing an initial software configuration on at least one target computer in an installation system. The at least one target computer is booted from a boot storage medium. Identification data associated with the hardware configuration of the target computer is automatically retrieved from the memory of the at least one target computer. Data representative of software component modules is automatically transferred from a library of software component modules stored on a library storage medium to the memory of the target computer based on the retrieved identification data associated with the hardware configuration of the target computer. The transferred software component modules are automatically installed onto the memory of the target computer.

Abstract: A machine having a non-volatile storage medium interface such as a CDROM drive and a local hard drive is configured for execution of an application process from a non-volatile storage medium such as a CDROM. The method of configuring the machine includes first loading into the machine, from a removable non-volatile storage medium in communication with the non-volatile storage medium interface, an operating system environment. The local hard drive is accessed to determine if the machine has a signature indicating that the machine had been configured previously. In response to a determination that the machine was not previously configured, a network connection to a server is established to access configuration files for use by the operating system environment and/or the application process. A local file system is loaded from the removable non-volatile storage medium onto the local hard drive, based on the accessed configuration files.

Abstract: The HKEY_LOCAL_MACHINE\SYSTEM\DISK\Information Windows NT registry key contains disk layout information, such as disk letter assignments. During repartitioning of a hard drive, this key needs to be modified to reflect the new partitions. In order to accomplish this, while in Win32 mode, the modified disk layout information is stored in a temporary registry key. Then, while in Windows NT boot mode, direct reads and writes are performed on the registry files (e.g., “system” and “system.alt”) that contain the “Information” registry key and the temporary registry key to replace the “Information” registry key with the temporary registry key.

Abstract: In accordance with a first aspect, a remote server receives video programming in a first encrypted form and stores the video programming. After the remote server receives a request from a subscriber station for transmission of the video programming, the remote server decrypts the video programming, re-encrypts the video programming into a second encrypted form, and then transmits the video programming to the subscriber station. In accordance with a second aspect, a remote server receives video programming in a first encrypted form, decrypts the video programming, re-encrypts the video programming into a second encrypted form, and then stores the video programming. After the remote server receives a request from a subscriber station, the remote server simply transmits the video programming. In accordance with a third aspect, a remote server receives video programming in a first encrypted form and stores the video programming.

Abstract: A server broker configured for use in a secure communication network, such as the Internet. The broker is configured to broker client transactions received over a secure network link, such as a secure socket layer (SSL) link, for distribution among one or more of a plurality of fulfillment servers. In one embodiment, the broker establishes a non-secure link with the one or more fulfillment servers. In another embodiment, the broker establishes a secure SSL link with the one or more fulfillment servers. The fulfillment server executes client transactions and sends response packets for delivery to the client.

Abstract: A system and method for authenticating a digital ID can utilize a central switch to transmit data between a network connected to a service provider and a network connected to a digital ID issuer. The system can be configured to provide a “yes/no” authorization or a validation at a selected validation level. The system can receive an encrypted authorization request message, and can generate an encrypted authorization response message. The authorization response message can be used by the service provider to decide whether to provide a service to a digital ID holder.

Abstract: Apparatus, method and computer program product are provided for performing integrity checking of a relocated executable module loaded within memory by an operating system loader. A repeatable digital signature is generated by determining the load address of the executable module in memory, normalizing at least some content of the executable module in memory employing the load address of the module, and then performing integrity analysis on a digital section of the module's content, including the normalized content, thereby deriving the repeatable digital signature.

Abstract: Aspects for a heterogeneous computer network system with unobtrusive cross-platform user access are described. In an exemplary system aspect, the system includes a plurality of computer systems coupled in a network, each of the plurality of computer systems operating according to one of a plurality of operating system platforms, each operating system platform having an associated security mechanism. The system further includes an enterprise directory included on at least one server system of the plurality of computer systems, the enterprise directory configured for security interception to allow an authorized user access among the services of the plurality of computer systems without affecting the associated security mechanisms of the plurality of operating system platforms.

Abstract: A real-time approach for detecting aberrant modes of system behavior induced by abnormal and unauthorized system activities that are indicative of an intrusive, undesired access of the system. This detection methodology is based on behavioral information obtained from a suitably instrumented computer program as it is executing. The theoretical foundation for the present invention is founded on a study of the internal behavior of the software system. As a software system is executing, it expresses a set of its many functionalities as sequential events. Each of these functionalities has a characteristic set of modules that is executed to implement the functionality. These module sets execute with clearly defined and measurable execution profiles, which change as the executed functionalities change. Over time, the normal behavior of the system will be defined by the boundary of the profiles.

Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

Abstract: A portable computer using a stylus for power control comprises a main body of the computer contained in a housing and provided with a stylus-holding means, a stylus for inputting data, and a means for detecting the combination and separation of the stylus and for controlling power supply to a system unit. The detecting and controlling means consists of a signal-generating unit and a power control unit. The signal-generating unit is positioned in the main body so as to detect the combination and separation of the stylus and generate a signal. The power control unit controls power supply to the system unit in response to the signal.

Abstract: A flexible magnetic disk drive with a built-in USB interface is disclosed. A disk sensor produces an output that, in the event of a change from one disk to another during a SUSPEND state of a SUSPEND/RESUME signal, remains indicative of disk absence from the moment said one disk was unloaded to, at the earliest, the moment the SUSPEND/RESUME signal subsequently gains a RESUME state, for power-saving purposes. In order to enable the computer to know the occurrence of the disk change immediately upon resumption of disk drive operation, the disk sensor output is sampled approximately at the beginning and end of each SUSPEND state, and immediately after the beginning of each RESUME state, of the SUSPEND/RESUME signal. Six different possible histories of disk loading and unloading past each SUSPEND state are ascertainable from every three disk sensor output samples. Each such renewable history datum is stored on a memory in the interface, for delivery to the computer on demand.

Abstract: An apparatus and method for power plane control/management for a printed circuit board is provided. A single voltage regulator has an input terminal to receive a main voltage supply and has a drive terminal. First and second transistors, such as field effect transistors (FETs), have first terminals coupled to the drive terminal of the voltage regulator and second terminals coupleable to a first power plane. The first transistor has a third terminal coupleable to an auxiliary voltage supply, and the second transistor has a third terminal coupleable to a second power plane. During a first power mode, such as a full power mode, the drive terminal of the voltage regulator is coupled to turn off the first transistor and to turn on the second transistor, thereby providing regulated voltage from the main voltage supply to the first power plane and to the second power plane through the turned-on second transistor.

Abstract: The CPU operates at the highest speed in start processing of an operating system. When a power-saving driver receives a start completion message from the operating system, the power-saving driver waits for a predetermined period until user operation to a computer system is enabled, and then sets the processing speed of the CPU to a user-designated speed. When the power-saving driver receives from the OS an OS termination start message representing the start of shutdown processing, the power-saving driver cancels setting of the user-designated speed, and returns the CPU to, e.g., the highest speed. Hence, start processing/shutdown processing can be executed at a high speed regardless of the set value of the user-designated speed.

Abstract: An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an address is to be loaded into the address register. A control circuit is coupled to receive the signal and to generate a second signal responsive to the address register being loaded. A shadow register, clocked by the clock signal of the integrated circuit, is coupled to receive the second signal and to load a value from the control/status register addressed by the address loaded into the address register responsive to the second signal. In this manner, a valid value from the addressed register is synchronized in the clock domain of the addressed register. The value for the shadow register may subsequently be synchronized into the clock domain of the TAP, and subsequently transferred out of the integrated circuit via the test interface.

Abstract: Methods and systems for reducing signal skew caused by dielectric material variations within one or more module substrates are described. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e.g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e.g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew.

Abstract: Structure and method for efficient failover and failback techniques in a data storage system utilizing a dual-active controller configuration for minimizing a delay in responding to I/O requests from a host system following a controller failure is described. A stripe lock data structure is defined to maintain reservation status or stripe locks of cache lines within data extents that are part of a logical unit or storage volume. When a controller fails, dirty cache line data of a failed controller is taken over by a survivor controller. The stripe lock data structure is used to process I/O requests from a host system, by the failed controller. The data storage system functions in a single-active configuration until the dirty cache line data is flushed to one or more storage volumes, by the survivor controller. The inventive structure and method provide utilize a storage volume reservation system. The stripe lock data structure is defined in memory within each of the two or more caching controllers.

Abstract: A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Abstract: A device for debugging a program includes a memory unit for storing a program having a hierarchical structure to be debugged; a display unit for displaying the program stored in the memory; a display state control unit for controlling the display unit to display statements included in the program in selected one of first and second states; and a step-execution unit for performing a step-execution of the program to be debugged in accordance with the selected one of the first and second states.

Abstract: The present invention relates to an application for automatically diagnosing problems with an object via problem representation data that is substantially accurate, complete and language independent. The application may process the problem representation data via pattern matching problem representation data against known problems and may generate at least one of diagnostic information and solution information relating to the problem representation data. The present invention may also update a store of known problems and the diagnostic rules, diagnostic messages and solution messages associated with such known problems.

Abstract: A method, apparatus, and a program product to protect against thread loss in a multithreaded computer processor. The processor may experience the failure of one or more threads; in accordance with the invention, a functional test can be run to determine which thread is experiencing the failure. If the thread failure results the failure of a register/array that is uniquely associated with the thread, then the invention will disable access to those register/arrays. Each thread may have its own set of register/arrays or it may be uniquely assigned to one of a plurality of storage elements in a multithreaded register/array. Using this invention, a processor may continue processing other threads and the instructions and data associated with the disabled or defective thread can be rerouted.

Abstract: A digital processing system comprises a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various processing tasks; a direct memory access (DMA) controller; a memory management unit (MMU) programmed to translate virtual memory addresses to physical memory addresses; and a plurality of memory blocks for storing digital words in registers having physical addresses; wherein the DMA controller is governed by the CPU and is operable in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU which translates the virtual source and destination memory addresses received from the DMA controller to corresponding source and destination physical addresses of the memory. Also disclosed is a method of operating the digital processing system.

Abstract: A method for testing a keyboard complied with a language code table comprises the steps of reading an embedded language code of the keyboard to be tested through a central processing unit (CPU), comparing the read language code with the language code table stored in memory in order to determine whether there is a matched one, reading an application program interface (API) function from the keyboard to be tested by the CPU, identifying a type of the keyboard to be tested by a “Get Keyboard Type” of the API function, reading exchange codes of special keys from the keyboard to be tested by the CPU, identifying a model of the keyboard to be tested, selecting a keyboard test software corresponding to the language code, the type, and the model of the keyboard to be tested from a test software database stored in memory, and performing a test on each key on the keyboard by the selected keyboard test software.

Abstract: A system and method is provided for generating a summary dump file from a system or application crash dump or core dump file without the need for referencing a large symbol table file. A crash dump file with a referencing portion containing references to certain pertinent information (e.g., data structures) including references conventionally not found in crash dump files. The data structures referenced in the referencing portion have been found to be optimal for analyzing faults residing in a crash dump file. The crash dump file may be a complete crash dump file of an operating system or a kernel memory dump. Alternatively, the crash dump file may be a crash dump file of an application program. A stand alone extraction tool is also provided for extracting pertinent information from the crash dump or core dump file by utilizing information in the referencing portion. The stand alone tool generates a summary or mini dump file of the crash dump file.

Abstract: Each agent unit gets status information indicating the state of each of network printers connected by a LAN from the network printers every first time period. Whenever each agent unit gets the status information from the network printer, it overwrites a status log data file with the gotten status information. Each agent unit converts all status information stored in the status log data file into status mail of electronic mail and transmits the status mail to a mail server every second time period longer than the first time period. On the other hand, a console unit accesses the mail server and reads the status mail in a proper time period to the console unit.

Abstract: A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.