Abstract: A magnetic ferrite composition including at least one of Mg, Ni, Cu, Zn, Mn, and Li and having a content of carbon within a predetermined range, for example, over 9.7 weight ppm to less than 96 weight ppm. The composition may be used as the magnetic core for an inductor, transformer, coil, etc. used for radios, televisions, communication devices, office automation equipment, switching power sources, and other electronic apparatuses or magnetic heads for video apparatuses or magnetic disk drives or other electronic components.

Abstract: There is described an electrorheological fluid comprising particles of a composite material suspended in an electrically insulating hydrophobic liquid. The composite particles are metal salts of the form M1xM22-2xTiO(C2O4)2 where M1 is selected from the group consisting of Ba, Sr and Ca and wherein M2 is selected from the group consisting of Rb, Li, Na and K, and the composite particles further include a promoter selected from the group consisting of urea, butyramide and acetamide.

Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.

Abstract: The present invention relates a reactive tertiary amine catalyst used in a phenolic urethane cold box process. Through the use of a reactive tertiary amine, the problems associated with vaporous amine waste streams can be eliminated. Some typical reactive tertiary amine catalysts that are useful in the present invention include 1-dimethylamino-2-propanol (DMA-2P), monoethanolamine and dimethylaminopropylamine (DMAPA).

Abstract: A compression molded product of quick-dissolving chlorinated isocyanuric acid, comprising:

Abstract: The invention is a method and composition for producing carbon dioxide that is based on the reaction or activation of at least one carbon-containing compound with protons. The carbon-containing compound can be in the form of a powder, an impregnated carrier (e.g. zeolite crystals) or an aqueous solution and is preferably selected from the group consisting of carbonates, bicarbonates or sesquicarbonates. The protons are preferably provided by a proton-generating species such as an acid or metal salt. The method and composition can further include a water-retaining substance and/or a chlorine dioxide-producing compound in accordance with the invention.

Abstract: An indicating desiccant comprises a silica-based material having impregnated thereon a source of copper and a source of bromide, the source of copper being present in an amount up to 0.5 per cent by weight, calculated as Cu with respect to weight of the silica-based material, and the source of bromide being present in an amount such that the weight ration of Br to Cu is at least 5:1. Optionally, the indicating desiccant also comprises a dye or other coloured material.

Abstract: The present invention relates generally to a static dissipative textile having an electrically conductive surface achieved by coating the textile with an electrically conductive coating in a variety of patterns. The electrically conductive coating is comprised of a conducting agent and a binding agent, and optionally a dispersing agent and/or a thickening agent. The static dissipative textile generally comprises a fabric which may be screen printed or otherwise coated with a conductive coating on the backside of the fabric so that the conductive coating does not interfere with the appearance of the face of the fabric. The economically produced fabric exhibits relatively permanent static dissipation properties and conducts electric charge at virtually any humidity, while the conductive coating does not detrimentally affect the overall appearance or tactile properties of the fabric.

Abstract: Disclosed are polymer-based coatings and materials comprising (i) a polymeric composition including a polymer having side chains along a backbone forming the polymer, at least two of the side chains being substituted with a heteroatom selected from oxygen, nitrogen, sulfur, and phosphorus and combinations thereof; and (ii) a plurality of metal species distributed within the polymer. At least a portion of the heteroatoms may form part of a chelation complex with some or all of the metal species. In many embodiments, the metal species are present in a sufficient concentration to provide a conductive material, e.g., as a conductive coating on a substrate. The conductive materials may be useful as the thin film conducting or semi-conducting layers in organic electronic devices such as organic electroluminescent devices and organic thin film transistors.

Abstract: Disclosed herein is a water-dispersible powder consisting essentially of polymers T comprising recurring thiophene units and at least one further polyanionic polymer P and process for preparing and using the same.

Abstract: When the entire amount of conductive metal mixed powder made of copper, manganese, and germanium is 100 parts by weight, the metal mixed powder is formed by mixing 4.0 to 13.0 parts manganese by weight, 0.2 to 1.4 parts germanium by weight, and 85.6 to 95.8 parts copper by weight, and 0 to 10 parts glass powder by weight and 0 to 10 parts copper-oxide powder by weight are mixed relative to the entire amount (100 parts by weight) of these metal components. The obtained resistive paste is then baked, and the resistive composition having the low resistance value and low TCR may be obtained. In addition, a resistor is made by forming the resistive element upon a substrate.

Abstract: Improved fire retardants that include guanylurea phosphate [(H2N—C(NH)—NH—C(O)—NH2).H3PO4] (GUP) and boric acid, materials such as wood and composite wood products that include these fire retardants, and methods of making and using same.

Abstract: The invention relates to a fire-protection coating which forms an insulating layer and is based on substances which, in the event of a fire, form a foam layer and form carbon, on film-forming binders, on blowing agents, and on conventional auxiliaries and additives, which comprises a phosphinic salt of the formula (I) and/or a diphosphinic salt of the formula (II), and/or their polymers, 1

Abstract: The invention relates to mixtures of phosphonite (component A) and/or an ester and/or salt of a long-chain fatty acid (component B), and/or a carboxylic ester, and/or carboxylic amide (component C), and also to their use in polyamides or in polyesters.

Abstract: A motorcycle lift [100] comprises two lift arms [103A, 103B] attached to a cross bar [105]. Support sleeves [109A, 109B] attached to the ends of the lift arms surround the foot pegs [150A, 150B] of the motorcycle [301] to securely engage the vehicle. Clamps [125A, 125B] provide a means to adjust the width between the support sleeves for engagement to the foot pegs. A lever [107] attached to the cross bar raises and lowers the motorcycle. Replaceable sleeves [109A, 109B] allow relatively tight diametrical clearance with various foot peg designs to provide stable support. The design allows stable support even with foot pegs of folding designs.

Abstract: A two-wheeled vehicle uprighting device having a support bar with a stabilizing base on one end and a ratcheting mechanism on another end, a cable sling adapted for attachment to a lower portion of the two-wheeled vehicle, and a flexible lifting member with a first end adapted for attachment to the cable sling and a second end for engaging relationship about a spindle of said ratchet mechanism.

Abstract: A lift, a system and a method for elevating a trailer are provided. The lift may have an “A” frame for supporting the trailer. The trailer may be placed on the lift and secured to the lift. A cable attached to the lift is used to pull the lift and the trailer towards a wall. The cable, with the use of a pulley system, pulls the trailer in an upward direction towards the wall such that the lift and the trailer may be elevated in a vertical direction. The lift with the trailer may be attached to the bracket on the wall and locked into place. The lift and the trailer may be removed from the wall by releasing a lock.

Abstract: A deck railing section comprises synthetic posts held spaced from one another by top and bottom rail members. Each of the rail members has a multiple piece construction including first and second interlocking synthetic rail pieces and a metallic reinforcing insert. The insert has holes at post attachment locations along the insert. Each post has screw ports to opposite ends of the post. Rail members are secured to the posts by threaded attachment members passing through the holes in the inserts and into the screw ports of the posts. The first rail pieces are trapped between the posts and the inserts. The second rail pieces lock onto the first rail pieces hiding the reinforcing inserts internally of the rail members.

Abstract: A fence assembly includes a plurality of spaced, elongated hollow post members. Each of the plurality of elongated post members has an outer wall. The outer wall has a generally H-shaped cross-section. The elongated post member includes a first side and a second side. The first and second sides are oriented opposite each other. One or more inner rib is attached to an inner surface of the outer wall and extends between the first side and the second side to define a middle chamber of the elongated hollow post member. One or more reinforcing member may be positioned in the middle chamber of one or more of the plurality of elongated hollow members to provide support. A plurality of fence panels is fastened between adjacent pairs of the plurality of spaced, elongated post members.

Abstract: Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.

Abstract: A thin film Zener diode, comprising:

Abstract: An organic electroluminescent device including at least one organic thin film layer interposed between an anode and a cathode, the at least one organic thin film layer including a luminescent zone having at least one luminescent layer, wherein the organic thin film layer contains a compound represented by one of the following general formulae [I], [II], and [III]:

Abstract: The invention provides a method and apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.

Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.

Abstract: A method of forming a storage capacitor in an IPS liquid crystal display device is proposed, and a technique of forming a pixel region having a high aperture ratio is provided. An anodic oxidation process at an applied voltage/voltage supply time ratio of 11 V/min is performed for insulating films used in each circuit of an electro-optical device, typically an IPS method LCD, in particular for the surface of a common electrode formed on a resin film. The amount of formation of the extra anodic oxide film can be reduced by covering with an anodic oxide film, and a liquid crystal display device with high reliability and having an electrode with superior adhesion can be manufactured.

Abstract: LDD regions can be properly formed even when a gate insulation film is thin, and an impurity can be properly activated. After forming a gate electrode, an n-type impurity is implanted in a high density using a resist mask for etching the gate insulation film as a mask. A SiO2 film is formed as a first interlayer insulation film, and activation is thereafter performed using a laser. By implanting the impurity with the resist mask for etching left in place, the problem of excessive implantation of the n-type impurity in the LDD regions can be avoided without adding a photolithographic process even when the gate insulation film is thin.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode.

Abstract: A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a &dgr; doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration &dgr; doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

Abstract: A nitride semiconductor light-emitting device includes an emission layer (103) formed on a substrate (100), and the emission layer includes a quantum well layer of GaN1−x-y−zAsxPySbz (0<x+y+z≦0.3) containing Al.

Abstract: A light-emitting diode (1) has a lens body (3) that is fabricated from an inorganic solid. Fastened on the lens body (3) are semiconductor chips (2) that emit light beams (18). Furthermore, the light-emitting diode (1) is provided with a housing (20) that can be screwed into a conventional lamp holder via a thread (21).

Abstract: In a nitride semiconductor device having an active layer 12 between a first electrically conductive type of layer and a second electrically conductive type of layer, a quantum well structure is adopted in which an active layer 12 has at least a well layer 11 formed of a nitride semiconductor containing In and Al and a barrier layer 2 formed of a nitride semiconductor containing Al, whereby a laser device excellent in emitting efficacy at a short wavelength region is obtained. It is particularly preferable that said well layer 1 is formed of AlxInyGa1-x-yN (0<x≦1<0<y≦1, x+y<1) and said barrier layer 2 is formed of AluInvGa1-x-vN (0<u≦1, 0≦v≦1, u+v<1).

Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a first cladding layer of a Group III nitride, a second cladding layer of a Group III nitride, and an active layer of a Group III nitride that is positioned between the first and second cladding layers, and whose bandgap is smaller than the respective bandgaps of the first and second cladding layers. The semiconductor structure is characterized by the absence of gallium in one or more of these structural layers.

Abstract: A light emitting device 1 has a light emitting layer portion in which a p-type cladding layer 2, an active layer 33 and an n-type cladding layer 34 are stacked in this order, and the p-type cladding layer 2 is composed of a p-type MgxZn1-xO (where, 0<x≦1) layer. By forming these layers by the MOVPE process, oxygen deficiency during the film formation is effectively prevented from occurring, and a p-type MgxZn1-xO layer having desirable characteristics can be obtained.

Abstract: Disclosed are a semiconductor light emitting device capable of enhancing a light emergence efficiency at a lower light emergence plane of the device by forming an electrode on a halfway area of a tilt crystal plane and a fabrication method thereof. According to this light emitting device, since light emitted by a light emitting region can be efficiently, totally reflected and a current can be injected only in a good crystalline region for the reason that the halfway area, on which the electrode is formed, of the tilt crystal plane is better in crystallinity than other regions of the tilt crystal plane, it is possible to enhance both a light emergence efficiency and a luminous efficiency, and hence to enhance the light emergence efficiency by an input current.

Abstract: The light emitting device has a light emitting diode which is made of a nitride semiconductor and a phosphor which absorbs a part of lights emitted from the light emitting diode and emits different lights with wavelengths other than those of the absorbed lights. The phosphor is made of alkaline earth metal silicate fluorescent material activated with europium.

Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

Abstract: The tunnel junction structure comprises a p-type tunnel junction layer of a first semiconductor material, an n-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. At least one of the semiconductor materials includes gallium (Ga), arsenic (As) and either nitrogen (N) or antimony (Sb). The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer.

Abstract: A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

Abstract: The invention concerns a structure for protecting a first zone of a semiconductor wafer comprising a substrate (11) having a first type of conductivity against high frequency disturbances liable to be injected from components formed in the upper part of a second zone of the wafer, comprising a highly-doped wall of the first type of conductivity having substantially the depth of said upper part. The invention is characterised in that said wall is divided into three highly-doped strips (21) of the first type of conductivity separated and enclosed by moderately-doped intermediate strips (23) of the first type of conductivity, the distance between the highly-doped end strips being of the order of magnitude of the substrate thickness.

Abstract: Contact bump construction (27) and method for the production of a contact bump construction for the formation of elevated contact sites on connecting surfaces (22) of a substrate (21), particularly chip connecting surfaces, with a spacer metallization (28) for the attainment of a defined height of the contact bump construction, wherein the spacer metallization (28) consists at least partly of annealed copper.

Abstract: The present invention generally relates to methods used for fabricating integrated circuits (“ICs”), using Ruthenium (“Ru”) and its oxides and/or Iridium (“Ir”) and its oxides as the diffusion barrier to contain and control copper (“Cu”) interconnects. The invention also covers ICs incorporating such materials in the diffusion barrier to contain and control the Cu interconnects. The present invention advantageously provides better integration and fabrication of advanced IC chips with sub-micron features.

Abstract: A method is provided for forming semiconductor devices using a semiconductor substrate having first and second opposed sides, and at least one device layer on the second side of the substrate, the at least one device layer including first and second device portions. A first trench is formed in the first side of the substrate between the first and second device portions. A second trench is formed in the second side of the substrate between the first and second device portions.

Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.

Abstract: A semiconductor device can include a low resistance wiring layer (13) formed in, and extending along a base material. A number of element regions (14) are formed separate from one another, each in contact with wiring layer (13). A circuit element can be formed in each element region (14). A metal is preferably used for wiring layer (13). In the above arrangement, metal-oxide-semiconductor (MOS) type transistors can be provided in a silicon-on-insulator (SOI) substrate that can have different potentials applied to a source/drain region with respect to a channel region.

Abstract: A read circuit in a semiconductor device includes a circuit for determining whether data that have been read from a plurality of circuit blocks are to be supplied as output to the outside, and a discharging circuit that is inserted in cascade connection in data lines that are shared with a succeeding circuit blocks. If the output data that are to be transferred are at a low level, the discharging circuit is set to a conductive state and the data line that is shared with the succeeding circuit block is discharged, and if at a high level, the shared data line is precharged by a precharging circuit. This control operation is successively repeated as far as the lowest-order circuit block to supply, as output, data of a logic level that corresponds to the output data.

Abstract: The semiconductor integrated circuit (RF IC) for a mobile telephone capable of transmitting/receiving the signals of plural bands reduces the DC offsets of the amplifiers located in the following stages of the mixers that demodulate or down-convert the reception signals. The invention scrambles the signal lines to transmit the outputs of the plural mixers that demodulate or down-convert the reception signals of different bands, so as to avoid the adjacent signal lines from making the same combination from the starting ends to the finishing ends.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: Shift register electrodes are formed in an imaging area and a peripheral area through use of a single layer of conductive film, and a thick insulating film is deposited over those electrodes and planarized. The thick insulating film overlying the shift register electrodes in the peripheral area is kept as it is and on the other hand, the thick insulating film overlying the shift register electrodes is etched to just fill gaps between the shift register electrodes with the film, thereby allowing a light shielding metal layer overlying the shift register electrodes in the peripheral area and insulating films sandwiched therebetween to be formed without discontinuity. Since metal interconnect lines in the peripheral area have a thick and planarized insulating film formed thereunder, parasitic capacitance between diffusion layers/electrodes and the metal interconnect lines can be reduced, leading to reduction in power consumption of image sensor.