Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.

Abstract: Compositionally engineered CeXMnYO3 (Cerium Manganate) and electronic devices based thereon When the proportion of cerium to manganese in CeXMnYO3 is altered, a number of the electrical properties of the material are affected, among them are the ferroelectric and dielectric constant. By adjusting the proportion of cerium to manganese the deposited material can be either dielectric or ferroelectric. A silicon based transistor having a gate of ferroelectric CeXMnYO3 forms a single transistor non volatile memory cell, which does not require additional layers and thus greatly reduces architecture complexity and utilizes the standard operating voltage of a DRAM. A silicon based device having a capacitor, inductor or resistor made of dielectric CeXMnYO3 forms a passive structure which does not require additional layers and thus greatly reduce architecture complexity.

Abstract: A semiconductor device without any peel off from the insulation film and without any fracture that becomes the cause of a short circuit is obtained even if a metal such as Ru is employed for the storage node. On the semiconductor substrate are provided an underlying interlayer insulation film located over both a capacitor region and a peripheral region, an interlayer insulation film located above the underlying interlayer insulation film, and a tubular metal film having a bottom end portion in contact with the underlying interlayer insulation film, and piercing the interlayer insulation film with the opening side located at the upper side in the capacitor region and the peripheral region. The opening side of the tubular metal film is formed only of a portion extending along the sidewall of a throughhole in the interlayer insulation film.

Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: There is provided a semiconductor device having a storage node free of defect in geometry and capable of preventing a cylinder from collapsing, protecting an interface with an SC's polycrystalline silicon barrier metal against oxidation, and furthermore reducing current leakage. The device includes a storage node contact insulation film disposed on a semiconductor substrate and provided with a storage node, a storage node insulation film and the storage node penetrating the storage node insulation film and positioned to extend from the storage node insulation film upward, and a storage node contact is recessed toward a bottom of the storage node and the storage node's bottom has a protruding geometry embedded in the recess.

Abstract: A semiconductor device is obtained that can prevent occurrence of a shape defect of a capacitor electrode in the semiconductor device or operation failure of the semiconductor device. A semiconductor device with the capacitor includes a second interlayer insulation film, an SC poly plug, a barrier metal and an SN electrode. The second interlayer insulation film has a through hole. The SC poly plug is formed within the through hole of the second interlayer insulation film. The barrier metal is formed on the SC poly plug. The SN electrode is formed on the barrier metal. The SN electrode is electrically connected to the SC poly plug with the barrier metal interposed therebetween. The barrier metal is a multilayer film including three layers of a tantalum nitride (TaN) film, a titanium nitride (TiN) film and a titanium (Ti) film.

Abstract: The present invention provides a method for making an integrated circuit capacitor having a Ta2O5 dielectric which includes a high-temperature nitrogen anneal and a low-temperature ozone anneal of the dielectric.

Abstract: A nonvolatile semiconductor memory device, including: a group of memory cells formed in X and Y directions in and on a semiconductor substrate, the X and Y directions crossing each other, each memory cell including source and drain regions formed in the substrate, a first insulating film formed on a surface of the substrate between the source and drain regions, a floating gate formed on the first insulating film, and a control gate formed above the floating gate via a second insulating film; a plurality of wordlines each connected to the control gates of the memory cells in the X direction; a plurality of sub-bit lines, each sub-bit line connected to a predetermined number of source and drain regions of the memory cells in the Y direction; a plurality of main-bit lines extending in the Y direction, each main-bit line being connected to the sub-bit line in the Y direction, and a plurality of dielectric layers laminated on the sub-bit lines, wherein each main-bit line is formed on any one of the plurality of di

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Abstract: A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.

Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Abstract: A semiconductor device has a depletion type MIS transistor, a transistor forming a masked ROM, and a submicron CMOS integrated on a single or common semiconductor substrate, while minimizing the steps of manufacturing the depletion type MIS transistor. During implantation of ions for changing an enhancement type transistor into a depletion type transistor, impurity ions can be implanted to change the transistor forming the masked ROM into resistance, so that the depletion type transistor, the transistor constituting the mark ROM, and a submicron CMOS can be integrated on a single or common semiconductor substrate.

Abstract: A MOSFET with low leakage current and method. The MOSFET has a substrate, a channel region, a source/drain region, a gate oxide layer and a conductive layer. The channel region in the substrate has a first region and a second region. The first region has a first threshold voltage and the second region has a second threshold voltage, respectively. The second region is located between the first region and the source/drain region. The first threshold voltage is smaller than the second threshold voltage. The leakage current of the MOSFET has an appropriate reduction by increasing the second threshold voltage of the second region. Significantly, by adjusting the size and position of the second region of the channel region, both the leakage current and the drain current of the MOSFET are readily optimized.

Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.

Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material.

Abstract: A lateral semiconductor device (10) has a semiconductor layer (15) on an insulating substrate (16). The semiconductor layer (15) has a first region (12) of a first conduction type and a second region (13) of a second conduction type with a drift region (14) therebetween. The drift region (14) is provided by a third region (14″) of the first conduction type and a fourth region (14′) of the second conduction type.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region.

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Abstract: The semiconductor device is inserted between a power source and a load. A current flowing between an external drain terminal D and an external source terminal S is controlled in accordance with a control voltage applied between an external gate terminal G and the external source terminal S. In addition, the semiconductor device has a main MOSFET 1 and a detecting MOSFET 2 each of which is inserted between the external drain terminal D and the external source terminal S, a protective circuit 3 which protects the main MOSFET 1 by a protective transistor 5 when the abnormality is detected thereby, and an impedance element 4 inserted between the protective MOSFET 5, and a junction connecting the external gate terminal G to a gate electrode of the detecting MOSFET 2.

Abstract: An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger drain coupled to a pad, a plurality of voltage drop elements, each of which is coupled between one of the finger sources and a power line to detect a transient current flowing through one of the finger gates, and a plurality of feedback circuits, each of which is coupled between a base and an emitter respectively of a first and second parasitic BJT, and activates the first BJT to bypass ESD current during an ESD event.

Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n≧2) number of bits (X1, X2, . . . Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4×1018 cm−3±40%.

Abstract: A semiconductor device comprising a silicon substrate and an insulating film adjacent thereto and which operates by applying a voltage to an electrode opposed to the silicon substrate with the insulating film interposed between; wherein an intermediate film is contained that is located between the silicon substrate and the insulating film and has a thickness of 0.2-1 nm. A method for manufacturing such a semiconductor device is also disclosed.

Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

Abstract: Microfluidic apparatus including integrated porous substrate/sensors that may be used for detecting targeted biological and chemical molecules and compounds. In one aspect, upper and lower microfluidic channels are defined in respective halves of a substrate, which are sandwiched around a porous membrane upon assembly. In another aspect, the upper and lower channels are formed such that a portion of the lower channel passes beneath a portion of the upper channel to form a cross-channel area, wherein the membrane is disposed between the two channels. In various embodiments, one or more porous membranes are disposed proximate to corresponding cross-channel areas defined by one or more upper and lower channels. The porous membrane may also have sensing characteristics, such that it produces a change in an optical and/or electronic characteristic.

Abstract: The present invention relates to a fingerprints detection apparatus by a capacitance detection method. The fingerprints detection apparatus of the present invention includes a sensor portion in which an insulating protection film is formed so as to cover detection electrodes arranged like an array, and the detection electrodes and the wiring beneath the detection electrodes are formed of a refractory metal or a compound of the refractory metal. This structure heightens the Vickers hardness of the detection electrodes and the wiring. This makes it possible to provide a highly reliable fingerprints detection apparatus in which a tolerance to cracks of the insulating protection film in the sensor portion is improved.

Abstract: A Micro Electro-Mechanical System (MEMS) varactor (100, 200) having a bottom electrode (116) formed over a substrate (112) and a dielectric material (130) disposed over the bottom electrode (116). A pull-down electrode (122) is formed over spacer (120) and the dielectric material (130). The MEMS varactor (100, 200) is adapted to operate in a stiction mode, with at least a portion of pull-down electrode (122) in contact with dielectric material (130). The MEMS varactor (100, 200) has a high Q, large tuning range, and high sensitivity.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A semiconductor substrate is provided including an isolation region buried insulating material in a trench formed in the semiconductor substrate, a plurality of films in at least one part of a bounded area between the semiconductor substrate and the isolation region, wherein the plurality of films comprises a silicon thin film and a silicon oxide film or a silicon oxynitridefilm, and the silicon thin film is nearer to the substrate than the silicon oxide film or the silicon oxynitridefilm.

Abstract: A semiconductor device comprises an embedded insulation layer 101 formed on a semiconductor substrate 100, plural power semiconductor elements 2, 3 formed on a semiconductor substrate 100 on the embedded insulation layer, a trench 4 formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator 5 insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements 2, 3 such as transistors can be used, being connected each other in series.

Abstract: A non-volatile memory, which comprises an insulating substrate (11) that has a first electrode (18) that extends through the substrate from the front surface to the rear surface thereof; a second electrode (13) that is formed on one side of the insulating substrate (11); and a recording layer (12) that is clamped between the first electrode (18) and the second electrode (13) and whose resistance value varies when an electric pulse is applied across the first electrode (18) and the second electrode (13); wherein the insulating substrate (11) has a layered structure composed of an organic dielectric thin film (112) and an inorganic dielectric layer (111) that is thinner than the organic dielectric thin film (112); with the recording layer (12) being formed on the side on which the inorganic dielectric layer is formed. Use of this non-volatile memory increases the possible number of data writing cycles while saving power.

Abstract: As disclosed herein, a structure and method is provided for forming an integrated circuit including a reduced programming voltage antifuse on a semiconductor substrate. The method includes doping a portion of a semiconductor substrate with nitrogen and a charge carrier dopant source, and forming a thin dielectric over the doped portion of the semiconductor substrate, wherein the thin dielectric is subject to breakdown upon application of a breakdown voltage. The method further includes forming a first conductor separated from the semiconductor substrate by the thin dielectric, and forming a second conductor conductively coupled to the doped portion of the semiconductor substrate.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.

Abstract: A recessed p-type region cap layer avalanche photodiode (12) is provided. The photodiode (12) includes a semiconductor substrate (30) and a semiconductor stack (32), which is electrically coupled to the substrate (30). A cap layer (34) is electrically coupled to the stack (32) and includes a recessed p-type region (36). The recessed p-type region (36) forms a p-n junction (38) with the stack (32). A method of forming the photodiode (12) is also provided. The method includes forming the substrate (30), the stack (32), and the cap layer (34). The cap layer (34) is selectively etched to expose the stack (32) and form a cap layer opening (42). Dopant is diffused through the cap layer opening (42) into the stack (32) to form the p-n junction (38).

Abstract: A shielding line system reduces or eliminates crosstalk between conductive lines in an integrated circuit. The shielding line system has first conductive line and one or more second conductive lines. A shielding line conduit radially encloses the first conductive line. An electromagnetic field also radially encloses the first conductive line.

Abstract: A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate 5 supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a 2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.

Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: In a multi-chip package having vertically stacked semiconductor integrated circuits (chips), a heat transmitting conductive plate (5) can be interposed between a lower layer semiconductor chip (3) and an upper layer semiconductor chip (4) and connected to a ground wiring of a substrate (2) through a bonding wire (9). A heating transmitting conductive plate (5) at the ground potential can block propagation of noise between the lower layer semiconductor chip (3) and upper layer semiconductor chip (4). Thus, the addition of noise to signals of an analog circuit in the upper layer semiconductor chip (4) can be avoided, reducing noise induced malfunctions. Furthermore, heat generated by the lower layer semiconductor chip (3) and upper layer semiconductor chip (4) can be transmitted through contact points with the heat transmitting conductive plate (5) for dissipation therefrom. This can improve heat dissipating capabilities of the semiconductor device (1) contributing to more stable operation.

Abstract: A surface mountable electronic device includes a body with a first surface for mounting the device. The first surface has recessed portions therein. Electrical contacts are provided in the first surface. The electrical contacts include first portions that form at least a portion of at least one inner surface of said recessed portions.

Abstract: (1) A thermal enhanced type of BGA package, in which a metal heat sink is joined to one side of a plastic circuit board which has a cutout space in the central portion, comprised of a clamping member joining the plastic circuit board and the heat sink. A caulking member, a rivet, a screw, an eyelet, or a tubular rivet could be used as the clamping member. It is preferable that a dam member is definitely attached by the clamping member.

Abstract: A high frequency interconnect packaging and assembly system (FIG. 25).

Abstract: The invention relates to an electronic device and a semiconductor wafer and also to a method for producing the device and wafer. The electronic device comprises at least one semiconductor chip obtained from corresponding chip positions of a semiconductor wafer constructed according the invention. In this case, the semiconductor chip has two topmost metallization layers that have area-covering voltage supply structures, insulation layers arranged in between, and passage contacts to module regions of an integrated circuit. The voltage supply structure has a grid of supply interconnects arranged parallel to one another. This grid is rotated with respect to a grid of a subsequent metallization layer.