Abstract: An eddy current inspection probe provides multiple interchangeable configurations for enabling an inspector to reach most or all portions of most or all turbine blades within a combustion turbine by inserting the probe through an inspection port, without disassembling the turbine. The probe shaft contains the electronic signal wire for the inspection tip and a port for a video probe, thereby facilitating use of the video probe and protecting these components. The inspection tip connector at the end of the main shaft is pivotally secured to the shaft, and may be set at any desired angle by using a semirigid or rigid member passing through the shaft, and connected to lever within the handle. Any one of a plurality of probe tips and shaft extensions may be selected to configure the inspection probe to reach a desired location within the turbine.

Abstract: A parallel Magnetic Resonance Imaging (MRI) system is provided for reconstructing images, to enable accelerated MRI with minimal artifacts. The MRI system comprises an array of magnetic resonance (MR) coils arranged in an array for detecting a plurality of MR signals, each coil having a corresponding spatial sensitivity profile and a processing means for processing the plurality of MR signals with at least one filter bank to reconstruct at least one image.

Abstract: A magnetic resonance imaging “MRI” method and apparatus for lengthening the usable echo-train duration and reducing the power deposition for imaging is provided. The method explicitly considers the t1 and t2 relaxation times for the tissues of interest, and permits the desired image contrast to be incorporated into the tissue signal evolutions corresponding to the long echo train. The method provides a means to shorten image acquisition times and/or increase spatial resolution for widely-used spin-echo train magnetic resonance techniques, and enables high-field imaging within the safety guidelines established by the Food and Drug Administration for power deposition in human MRI.

Abstract: A method for decreasing entropy of a quantum system of at least two subsystems, a first subsystem comprising elements with a first relaxation time (hereinafter—computation elements) and a second subsystem comprising elements with a second relaxation time (hereinafter—reset elements). The second relaxation time is shorter than the first relaxation time.

Abstract: A method and apparatus for producing an image from an extended volume of interest within a subject using a Magnetic Resonance Imaging (MRI) system are provided. The method comprises translating the volume using a positioning device along an axis of the MRI system. A plurality of MR signals are detected from at least one radiofrequency (RF) coil array for a given field-of-view within the MRI system as the positioning device is translated. The plurality of MR signals are sent to a plurality of receivers wherein the receivers are each adapted to adjust their respective center frequencies at a rate commensurate with a rate of translation of the positioning device. A plurality of respective sub-images corresponding to the plurality MR signals for each of the plurality of receivers are combined to form a composite image of the volume of interest.

Abstract: A Magnetic Resonance Imaging (MRI) magnet field instability simulator (80) is provided. The simulator includes a rigid body motion generator (82) that simulates motion of one or more MRI system components. An eddy current analyzer (84) generates a magnetic stiffness and damping signal and an electromagnetic transfer function in response to the motions and a cryostat material properties signal. A mechanical model generator (86) generates a mechanical disturbance signal and a mechanical model of one or more MRI system components in response to the motions and the magnetic stiffness and damping signal. A structural analyzer (88) generates a motion signal in response to the mechanical model. A field instability calculator (90) generates a field instability signal in response to the electromagnetic transfer function and the motion signal. A method of performing the same is also provided.

Abstract: A resistivity logging apparatus has an array of electrodes projecting from imaging pads. The electrodes penetrate nonconductive mud lining the borehole wall. Some of the electrodes are moveable in and out of the pad while others of the electrodes can be fixed. The electrodes, which are arranged in an array along a circumferential portion of the borehole wall, are able to make contact with the borehole wall. Sequencing electronics causes one electrode to be a source, another to be a measuring electrode, with the measurements of source electrode and measuring electrode moving along the array in order to log a circumferential portion of the borehole wall.

Abstract: An electronic battery tester, comprising first and second connectors configured to electrically couple to terminals of the battery, a microprocessor configured to test the battery using the first and second connectors, a memory containing a set of locked instructions for the microprocessor, an input configured to receive a software unlocking key, and the microprocessor configured to execute the set of locked instructions in response to the software unlocking key corresponding a predetermined software unlocking key.

Abstract: The present invention is directed toward a handheld battery tester that automatically determines and displays to the user a nominal battery rating (e.g., CCA rating) in response to the user entering certain vehicle information, e.g., the make and model of the vehicle. This eliminates the need to read the battery CCA rating from the battery and eliminates the need to check a secondary reference to be sure that the battery in the vehicle is rated high enough for that vehicle. Preferably, the battery tester is a processor-based battery tester that automatically uses the determined nominal CCA rating rather than making the user enter the displayed value.

Abstract: A battery cell voltages are read in parallel to a capacitor for each battery block of a battery pack by the use of analog switches. The stored voltages of the capacitors are A/D-converted sequentially through the analog switches. Thereby, each cell voltage is measured with suppression of measurement error by the use of the simple flying capacitor type circuit structure, while the circuit safety is secured by providing the current limitation resistor having a large resistance value between each cell and the analog switch. A noise reduction circuit having a pair of capacitors is provided.

Abstract: A gas analyzing apparatus including a reactor for decomposing a target substance contained in a gas to produce a product gas containing a decomposition product, a contacting chamber connected to the reactor and having a quartz oscillator disposed therewithin. The quartz oscillator has opposing surfaces each provided with an electrode, at least one of the electrodes being reactable with the decomposition product so that the decomposition product when contacted with the reactable electrode is reacted with the reactable electrode to cause a frequency deviation which is detected by a frequency measuring device.

Abstract: A coaxial radio frequency adapter and method are disclosed. An adapter has a tapered signal pin and a tapered ground sleeve to maintain a consistent impedance and minimize reflections while connecting two elements having different dimensions. A method employs an adapter to characterize losses in a system for evaluating a device under test.

Abstract: A method of inspecting insulators such as spark plug insulators for defects, whereby a plurality of insulators are inspected concurrently by being disposed with a plurality of first electrodes engaged in respective apertures in the insulators, and with apertures formed in a second electrode being disposed to peripherally enclose respective insulators. With the insulators and electrodes set in a closed chamber under high air pressure, and high voltage applied between the first and second electrodes, any defect is detected based on a level of leakage current which then flows.

Abstract: A method and system of calibrating first and second adapters comprises the steps of calibrating coaxial ports of a vector network analyzer to traceable standards and connecting a symmetrical through circuit path between the coaxial ports. The through circuit path comprises a cascaded combination of the first and second adapters. The first adapter is passive and substantially identical to the second adapter and uncascaded first and second adapters comprise a measurement device path. The through circuit path and the measurement device path have substantially equivalent S-parameters. S-parameters of the through circuit path are measured and then the first and second adapters are characterized based upon the measured S-parameters. The method and system may be applied to two port adapters and devices under test and may also be scaled for multi-port adapters and devices under test.

Abstract: A resonant sensor for determining structural property changes, in particular for detecting the presence of chemical or biological species, comprises a structure (2) mounted to be capable of resonating and having a cyclically symmetrical configuration with two independent degenerative modes of vibration of a common natural frequency (f), and means (24,26,28,30,32,34,36,38) for exciting the structure (2) to resonate according to the two degenerative modes, regions (8,12,16,20) of the structure (2) being modified such that, on changes in the structural properties of the modified regions (8,12,16,20), for example by the addition or subtraction of mass, the natural frequencies (f1, f2) of the two modes of vibration become different, the difference in frequencies (?f) being proportional to the change in structural properties.

Abstract: A condition sensor for a fabric treating apparatus, such as a clothes dryer. A condition sensor is connected to a base wherein the condition sensor is operative to sense a condition such as moisture content for a multi-layered load placed within the dryer. The condition sensor comprises at least one support connected to the base wherein the at least one support has at least one extension attached thereto. A pair of capacitance sensors are attached to the at least one extension with the pair of capacitance sensors being arranged to build up charge through the condition sensor based on the moisture of the load content positioned in the dryer. A circuit is arranged to receive, read and generate signals in response to the charge of the capacitance sensors.

Abstract: A contact structure having contactors formed on a flexible cable establishes electrical connection with contact targets. The contact structure includes a probe card having a plurality of contact pads and signal patterns, a plurality of contactors mounted on a contactor carrier, a flexible cable having a plurality of signal patterns for transmitting electrical signals therethrough. A first end of the flexible cable has a small pitch of the signal patterns while a second end of the flexible cable has a pitch of signal lines which is substantially larger than that of the first end. The first end of the flexible cable is connected to the contactors and the second end of the flexible cable is connected to the probe card.

Abstract: A scanning probe microscope detects or induces changes in a probe-sample interaction. In imaging mode, the probe 54 is brought into a contact distance of the sample 12 and the strength of the interaction measured as the probe 54 and sample surface are scanned relative to each other. Image collection is rapidly performed by carrying out a relative translation of the sample 12 and probe 54 whilst one or other is oscillated at or near its resonant frequency. In a preferred embodiment the interaction is monitored by means of capacitance developed at an interface between a metallic probe and the sample. In lithographic mode, an atomic force microscope is adapted to write information to a sample surface.

Abstract: A plunge mechanism includes an elongated, hollow probe that vacuum grips at its free end, and carries, without relative movement therebetween, an electronic device under test (DUT) to a test site on a board, or socket, of a test circuit. A reciprocating drive plunges the DUT in a first direction to a test site where the leads of the DUT each align with and connect electrically to an associated electrical contact. The drive uses a high-precision linear slide to maintain the alignment of the probe with the test site during the plunging movement. The probe materials and dimensions provide sufficient stiffness to resist a shift of the IC out of alignment due to the weight of the gripped DUT, vibrations, or contact forces between the DUT and the board or socket. The diameter of the probe is preferably smaller than the x-y dimensions of the DUT. No DUT alignment members are used on the test board or socket that limit the physical proximity of the DUT to its preferred test position with respect to the test circuit.

Abstract: A die carrier is disclosed which is specifically designed for use in a TSOP socket. More specifically, the die carrier has a carrier substrate with carrier contacts thereon that are dimensioned specifically to match the positioning of the upper and lower socket contacts. The carrier substrate, being 145 microns thick, can also fit between the upper and lower socket contacts. A carrier base support component is located below a portion only of the carrier substrate, and does not impair insertion of the carrier substrate into the relatively small spacing between the upper and lower socket contacts. Damage to the carrier substrate is avoided by clamping edges of the carrier substrate from opposing sides between the upper and lower socket contacts. There are no screws or nuts within the carrier base support component that may increase its size and prevent it from being inserted into the socket. A double-sided, robust electrical connection is made by each respective pair of upper and lower socket contacts.

Abstract: A semiconductor burn-in thermal management system for providing an effective thermal management system capable of maintaining a desired semiconductor temperature during a burn-in cycle. The semiconductor burn-in thermal management system includes a reservoir for storing a volume of fluid, a pump fluidly connected to the reservoir, and a plurality of spray units fluidly connected to the pump. The spray units dispense the fluid upon the surface of the semiconductor during burn-in thereby maintaining a relatively constant surface temperature. Each of the spray units preferably includes a stationary first portion with a second portion movably positioned within the first portion in a biased manner. When burning in semiconductors without an integrated heat sink that are deeply recessed within the sockets of a burn-in board, the fluid pressure to the second portion is increased thereby extending the second portion from the first portion thereby reducing the effective distance from the surface of the semiconductor.

Abstract: An improved vertical pin probing device is constructed with a housing with spaced upper and lower spacers of Invar®, each having a thin sheet of silicon nitride ceramic material held in a window in the spacer of adhesive. The Invar spacers may be composed of Invar foils adhered to one another in a laminated structure. The sheets of silicon nitride have laser-drilled matching patterns of holes supporting probe pins and insulating the probe pins from the housing. The Invar spacers and silicon nitride ceramic sheets have coefficients of thermal expansion closely matching that of the silicon chip being probed, so that the probing device compensates for temperature variations over a large range of probing temperatures.

Abstract: A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.

Abstract: A first test circuit is supplied with test signals to test an operation of a first semiconductor storage circuit. The test signals include a test input signal, a test output signal, and a test sync signal. A second test circuit receives the test signals from the first test circuit to test an operation of a second semiconductor storage circuit. The first test circuit uses the test input signal as information to operate the first semiconductor storage circuit in synchronization with the test sync signal and supplies the test input signal to the second test circuit. The first test circuit also synchronizes a signal, which is determined by performing a logical operation between the output of the first semiconductor storage circuit and the test output signal supplied thereto, with the test sync signal and supplies the signal to the second test circuit as a test output signal.

Abstract: A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode.

Abstract: A semiconductor die isolation system electrically disconnects the semiconductor die from a routing mechanism when an isolation block is activated. The semiconductor die is tested through a routing mechanism connection with a testing device on a semiconductor wafer. The isolation block is activated when the testing is completed.

Abstract: A method for accurately delivering a voltage to a circuit node of an integrated circuit having analog buses and transmission gates selectively connecting the circuit node to the buses, comprises sensing the voltage on the circuit node via a first of the buses under control of a first periodic signal; applying a first stimulus voltage to the circuit node via a second bus under control of a second periodic signal; and applying a second stimulus voltage to the circuit node under control of a third periodic signal which is inverted with respect to the second periodic signal so that the circuit node is driven alternately to the first stimulus voltage and to the second stimulus voltage.

Abstract: There has been no appropriate means to test connections between two integrated circuits packaged in a single semiconductor package.

Abstract: Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation.

Abstract: An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: In a semiconductor device, an input buffer for buffering an input signal to provide an internal signal includes a reference voltage adjusting unit configured to receive a reference voltage and to output a first reference signal having a potential level higher than that of the reference voltage and a second reference signal having a potential level lower than that of the reference voltage, a multiplexing unit configured to selectively output one of the first and second reference signals as a newly selected reference signal in response to the internal signal, a differential amplification unit configured to amplify the input signal by comparing the input signal with the newly selected reference signal outputted to generate an amplified input signal, and an internal buffer configured to output the internal signal by buffering the amplified input signal.

Abstract: A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

Abstract: Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT1, OUT2 therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT 1 and OUT 2 are combined in-phase.

Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

Abstract: An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

Abstract: A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.

Abstract: A comparator and method for detecting a signal using a reference derived from a differential data signal pair improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel comparator circuit provides the comparison, using a voltage or current level of the single-ended signal to determine states of the differential data signal pair.

Abstract: A sensing apparatus having a fluxgate and a control method capable of reducing current applied to drive the fluxgate are disclosed, the sensing apparatus including a driving coil for exciting a magnetic substance core with current, a current amplifier for applying the current to first and second ends of the driving coil, a fluxgate having a pulse generator for generating a pulse to turn on/off the current amplifier, an A/D converter for converting an analog signal from the fluxgate into a digital signal, and a pulse controller for outputting a control signal allowing the pulse to be applied to the current amplifier until it is determined that the conversion of the analog signal into the digital signal by the A/D converter is completed.

Abstract: A skew-free dual rail bus driver is provided. The dual rail bus driver includes a first driver outputting first dual signals of the same level, and outputting second dual signals of different levels when a level of a clock changes; a decoder receiving the second dual signals and outputting a single signal; a dual signal controller being triggered due to a change in the level of the second dual signals and outputting third dual signals of different levels in response to the single signal at the same time; and a second driver inverting the levels of the third dual signals output from the dual signal controller and outputting fourth dual signals in accordance with a change in the level of the clock. Accordingly, it is possible to obtain dual rail bus driving signals in which skew does not occur. Also, changes in the phases of dual signals are detected and used as a trigger signal input to an edge trigger flip-flop which is a dual signal controller.

Abstract: A main driver, in which NPN and PNP bipolar transistors are connected in series, is driven by an output of a pre-driver having a first CMOS circuit driven by an input signal. An assist circuit having a second CMOS circuit driven by the input signal and also having a current limit resistor is provided, and an output of the main driver is assisted by an output of the assist circuit. Therefore, it is possible to reduce a short circuit current in a transistor output circuit, to increase and decrease an output signal to an power-supply potential (upper limit) and a ground potential (lower limit), and to smoothly change the output signal near the power-supply potential and the ground potential. Further, an intensity of electromagnetic noise is reduced and a switching output having a sufficiently large amplitude is supplied.

Abstract: A register controlled DLL is used in generating a delay locked clock synchronized with an external clock, the external clock being used in generating an internal clock.

Abstract: A phase-locked loop having a phase detector for receiving a feedback signal and an input clock signal having an input clock frequency. The phase detector outputs or produces a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The phase-locked loop also has a loop filter coupled to the phase detector to receive the phase error signal and to output an error correction signal which includes an error correction frequency having a value ranging from about [input clock frequency−(input clock frequency×about 0.00015)] to about [input clock frequency+(input clock frequency×about 0.00015)]. A voltage controlled oscillator is coupled to the loop filter for receiving the error correction signal and to generate an output signal of the phase-locked loop which is indicative of the feedback signal.

Abstract: A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line.

Abstract: A delay lock loop circuit includes a reference loop for receiving an external clock signal and for generating a second output signal and a first output signal which includes a plurality of signals having different respective phases. A fine loop receives the external clock signal and the first output signal of the reference loop and generates an internal clock signal. A transition detecting circuit receives the second output signal of the reference loop and generates a protection signal by detecting a transition of the logic state of the second output signal of the reference loop. In response to the protection signal, the delay lock loop circuit in accordance with the present invention protects itself from an external clock signal that has a frequency that is out of the range of operable frequencies of the delay lock loop circuit, for example by diabling the enitre circuit, or a portion of the circuit.

Abstract: A circuit configuration regenerates clock signals. The circuit configuration includes an input differential amplifier, first and second inverters, and an offset compensation circuit. The input differential amplifier generates first and second amplified signals in response to first and second differential input clock signals. The first and second inverters generate a first and a second differential output clock signal. The offset compensation circuit controls the difference between the two output clock signals to zero or to a constant value. As an alternative to or in supplementation of the offset compensation circuit, it is possible to provide a control circuit for driving the two inverters, which shifts the input pulse shapes of the inverters to the optimum switching point of the inverters. The circuit configuration enables a regeneration of clock signals with simultaneous equalization of pulse distortions.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3; M1-M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.