Abstract: A system for the rapid characterization of multi-analyte fluids, in one embodiment, includes a light source, a sensor array, and a detector. The sensor array is formed from a supporting member into which a plurality of cavities may be formed. A series of chemically sensitive particles are, in one embodiment positioned within the cavities. The particles may be configured to produce a signal when a receptor coupled to the particle interacts with the analyte. Using pattern recognition techniques, the analytes within a multi-analyte fluid may be characterized.

Abstract: A method and apparatus are provided for the separation of biological materials from one another. The device includes a separation column that is in flow communication with a collection chamber in a reservoir that includes a collection container and a lid. The separation column is mounted on the lid. The collection container includes a concentration zone at the bottom and the container is adapted for use in further separation steps including centrifuging. The device includes a connector that is in flow communication with the collection chamber and is adapted for connecting it to a source of vacuum to help induce flow of liquid through the separation column.

Abstract: The present invention provides nucleic acid and amino acid sequences of an ATP binding cassette transporter and mutated sequences thereof associated with macular degeneration. Methods of detecting agents that modify ATP-binding cassette transporter comprising combining purified ATP binding cassette transporter and at least one agent suspected of modifying the ATP binding cassette transporter an observing a change in at least one characteristic associated with ATP binding cassette transporter. Methods of detecting macular degeneration is also embodied by the present invention.

Abstract: The present invention is directed to novel artificial T helper cell epitopes (Th epitopes) designed to provide optimum immunogenicity when used in peptide immunogens comprising B cell epitopes or peptide haptens, a target antigenic site of a target antigen for eliciting antibodies thereto. The artificial Th epitopes are covalently linked to the target antigenic site and and optionally an immunostimulatory sequence to provide effective and safe peptide immunogens.

Abstract: Growth differentiation factor-6 (GDF-6) is disclosed along with its polynucleotide sequence and amino acid sequence. Also disclosed are diagnostic and therapeutic methods of using the GDF-6 polypeptide and polynucleotide sequences.

Abstract: The present invention relates to a method for mass propagating the adventitious root of ginseng, camphor ginseng, wild ginseng by tissue culture and improving the saponin content. More specially, the method comprises the steps of: tissue culturing of the leaf, root, stems of ginseng, camphor ginseng, wild ginseng and dissecting the callus; Propagating the adventitious root, which was developed by above dissected callus; Mass culturing of the propagated adventitious root in a bioreactor. Especially, the present invention makes it possible to produce the adventitious root that has enriched saponin content and the ratio of diol saponin and triol saponin being the same level of the natural ginseng, thereby, it can provide more valuable adventitious root in commercial and usefulness.

Abstract: An analytic plate such as a microscope slide or a diagnostic plate and kit having the slide or plate, the slide or plate having a containment border for containing a liquid, histological or other biological sample. The containment border is substantially transparent and is substantially flush with the surface of the slide or plate for containing the liquid, histological or other biological sample disposed thereon and thereby preventing spreading or migration of the sample across the slide or plate. The containment border is preferably comprised of a polysiloxane, siloxane, silicone, a silane, a silicon fluid, or a combination thereof.

Abstract: There are provided membrane-associated polypeptides having the sequence shown in SEQ ID Nos. 1 and 9. Also provided are immunogenic determinants derived from said polypeptides and antibodies raised thereto. The polypeptides, their derived antigenic determinants and the antibodies are useful for the diagnosis and treatment of metastatic potential in tumors.

Abstract: A method for detecting the presence of flunitrazepam in a sample. Flunitrazepam contained within the sample is reduced and hydrolyzed by the addition of a hydrolyzing agent and a reducing agent. A visualizing agent is provided to combine with the reduced and hydrolyzed species corresponding to the flunitrazepam to yield a colored species providing a qualitative colorimetric indication of the presence of flunitrazepam within the sample. The invention is a rugged and dependable method suitable for use in the field.

Abstract: The present invention provides a real-time luminescent piezoelectric detector capable of sensing the presence of biological and chemical agents. This detector includes a free-standing thin film that is driven by a frequency driver to produce light emitted from an edge of the thin film. A surface layer sensitive to the biological or chemical agent to be detected is disposed on the surface of the thin film. In the presence of the biological or chemical agent to be detected, the light emitted from the edge of the thin film structure is altered. A processor capable of determining the presence and/or concentration of the biological or chemical agent in question based on the altered emitted light receives an output representative of the emitted light and outputs the status of the presence and/or concentration of the biological or chemical agent in question.

Abstract: The analytical process utilized in the system of this invention comprises three (3) step distinct steps wherein an analyte of interest in a test sample is initially labeled and subsequently isolated within a porous medium of a test device. Once isolated within the medium, the label is displaced from the analyte, or from the complex with the analyte, and converted, under electrolytic condition, to a metallic species which is caused test to deposit upon a working electrode of the test device. This working electrode is part of an electrode array that is positioned coincident with the porous medium, yet maintained physically remote therefrom. This deposit is then stripped from the working electrode, under anodic stripping conditions, and the current generated within the electrode array monitored. The characteristic response curve that is produced thereby can be correlated with the identity and concentration of the analyte(s) with the test sample.

Abstract: The microarrays of the present invention are prepared by using a separate fiber for each compound being used in the microarray. The fibers are bundled and sectioned to form a thin microarray that is glued to a backing.

Abstract: A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

Abstract: A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the relative positions of the contacts on a subject semiconductor device; calculating from the measurements seating planes 64 formed by tilting the device to one or more of its corners and/or sides such that each said plane comprises contacts at or adjacent to the corners of the device; using the measured relative contact positions and the calculated seating planes to determine the highest deviation from contact coplanarity for the semiconductor device.

Abstract: A method for fabricating field emitters from a conductive or semiconductive substrate. A layer of low work function material may be formed on the substrate. Emission tips that include such a low work function material may have improved performance. An etch mask appropriate for forming emission tips is patterned at desired locations over the substrate and any low work function material thereover. An anisotropic etch of at least the substrate is conducted to form vertical columns therefrom. A sacrificial layer may then be formed over the vertical columns. A facet etch of each vertical column forms an emission tip of the desired shape. If a sacrificial layer was formed over the vertical columns prior to formation of emission tips therefrom, the remaining material of the sacrificial layer may be utilized to facilitate the removal of any redeposition materials formed during the facet etch.

Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.

Abstract: A film bulk acoustic resonator wafer and microelectromechanical switch wafer may be combined together in face-to-face abutment with sealing material between the wafers to define individual modules. Electrical interconnects can be made between the switch and the film bulk acoustic resonator within a hermetically sealed chamber defined between the switch and the film bulk acoustic resonator.

Abstract: A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.

Abstract: A method of making a semiconductor device (100) by attaching a top surface of a first laminate (630) to a bottom surface of a second laminate (650) to form a leadframe (620) and mounting a semiconductor die (102) to the leadframe to form the semiconductor device. The first semiconductor die is encapsulated with a molding compound (108) and material is removed from the first laminate to form a mold lock (120) with the molding compound.

Abstract: A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. A no-clean flux that has a volatilization temperature below the melting point of the solder bumps is utilized to minimize or eliminate the need for a post interconnection de-flux operation.

Abstract: A method of fabricating a semiconductor apparatus includes forming a base member and a conductive layer on a first surface of a semiconductor substrate. The conductive layer has an extended portion that extends onto the base member. A first surface of the semiconductor substrate is placed to face a connection substrate, the extended portion of the conductive layer is then connected to the connection substrate, and a seal member is supplied in a space between the semiconductor substrate and the connection substrate.

Abstract: A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.

Abstract: A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.

Abstract: An image display device which includes a display pixel block and circuit blocks peripheral thereto. Each block has a circuit made of high-performance thin film transistors. The display pixel block and the peripheral circuit blocks including the four corners of the display device are formed on an image display device substrate of circuit-built-in type thin film transistors having a small circuit occupation surface area. A circuit including thin film transistors of a polycrystalline silicon film anisotropically crystal-grown and having crystal grains aligned in its longitudinal direction with a current direction is provided in the whole or partial surface of the display pixel block and circuit blocks. The longitudinal direction is aligned with a horizontal or vertical direction within the block, and blocks aligned in the horizontal and vertical directions can be arranged as mixed when viewed from an identical straight line.

Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.

Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method for manufacturing thin film transistor panels in order to obviate the lowstability of conventional laser annealing processes, and the resultant low quality of the produced polycrystal silicon thin film. According to the method of the invention, form a transparent insulator on the front surface of a silicon substrate. Form a thin film transistor structure and transparent electrode on the upper surface of the transparent insulator. Bond a transparent substrate onto the front surface of the silicon substrate. After that, remove a portion of the silicon substrate by polishing or etching the back of the silicon substrate to obtained a transparent thin film transistor panel. The transparent electrode can also be formed on the bottom surface of the transparent insulator. Also, the transparent substrate can be bonded onto the back of the silicon substrate. Then reduce the thickness of the silicon substrate to generate a crystal silicon thin film.

Abstract: A p channel thin-film transistor (TFT) made of directly deposited microcrystalline silicon (uc-Si). The p TFT is integrated with its n channel counterpart on a single uc-Si film, to form a complementary metal-silicon oxide-silicon (CMOS) inverter of deposited uc-Si. The uc-Si channel material can be grown at lower temperatures by plasma-enhanced chemical vapor deposition in a process similar to the deposition. The p and n channels share the same uc-Si layer. The Figure shows the processing steps of manufacturing the TFT, where (12) represents the uc-Si layer of the device.

Abstract: Method of fabricating TFTs starts with forming a nickel film selectively on a bottom layer which is formed on a substrate. An amorphous silicon film is formed on the nickel film and heated to crystallize it. The crystallized film is irradiated with infrared light to anneal it. Thus, a crystalline silicon film having excellent crystallinity is obtained. TFTs are built, using this crystalline silicon film.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Abstract: The disclosed invention provides a method for fabricating a MOSFET comprising the steps of forming a first insulation layer over a semiconductor substrate; forming a trench which bottoms on the semiconductor substrate in the first insulation layer so that the semiconductor substrate is exposed at the bottom of the trench; injecting impurities selectively under at least one end of the exposed surface of the semiconductor substrate; forming a second insulation layer to cover the bottom surface of the trench by oxidizing the exposed surface of the semiconductor substrate; forming a gate electrode over the second insulation layer inside the trench; removing the first insulation layer; forming a drain region under the surface of the semiconductor substrate so that the drain region contacts with one end of the second insulation layer, the end under which the impurities were injected; and forming a source region under the surface of the semiconductor substrate so that the source region contacts with the other end of

Abstract: An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.

Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in contact with the lower side of the gate electrode side walls, and upper side wall spacers that are composed of silicon nitride films and are in contact with the upper side of the gate electrodes side walls. As a result thereof, a distance is formed between the substrate and the interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurrence of poor contact.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

Abstract: The invention includes a switchable circuit device. The device comprises a first conductive layer and a porous silicon matrix over the first conductive layer. A material is dispersed within pores of the porous silicon matrix, and the material has two stable states. A second conductive layer is formed over the porous silicon matrix. A current flow between the first and second conductive layers is influenced by which of the stable states the material is in.

Abstract: A ferroelectric memory and method for fabricating the same includes a plurality of first gate electrodes and second gate electrodes formed on an active region of a substrate electrically separated form each other, a plurality of first electrodes of first ferroelectric capacitors each connected to the substrate at one side of the first gate electrode, and a plurality of first electrodes of the second ferroelectric capacitors each connected to the substrate at one side of the second gate electrode. Ferroelectric layers respectively formed on the first electrodes, and second electrodes are formed on the ferroelectric layers. A first metal line electrically couples the plurality of first gate electrodes, and a second metal line electrically couples the plurality of second gate electrodes. The ferroelectric memory has a simplified fabrication process and an increased area of the capacitor that is favorable for high density device packing.

Abstract: A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Abstract: The present invention provides a semiconductor device and a manufacturing method capable of preventing penetration of plasma with impurities into an interface between an inter-layer insulation layer and a diffusion barrier, thereby reducing degradation of the capacitor properties and increasing production yield. The inventive semiconductor device, including: a capacitor formed on a top portion of a semiconductor substrate, wherein the capacitor includes a bottom electrode, a dielectric layer and a top electrode; an Iridium (Ir) capping layer formed on the top electrode of the capacitor; an inter-layer insulation layer for covering the capacitor and the Ir capping layer; a Ti layer for preventing plasma with impurities from penetrating into the capacitor through a contact hole, wherein the Ti layer is contacted with the inter-layer insulation layer exposed on lateral sides of the contact hole and the Ir capping layer exposed on a lower side of the contact hole; and a metal line formed on the Ti layer.

Abstract: A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side walls therein, wherein a source and drain region of a drive transistor is formed in two of the four side walls, respectively, a pair of active layers respectively having a source and drain regions of a first load transistor is formed on the substrate adjacent to the side walls, and a gate electrode common to the load transistor is formed on a gate oxide film, whereby the gate electrode of the access transistor is vertically formed toward a direction vertical to the semiconductor substrate instead of being formed on the substrate for thereby decreasing an area to be occupied by transistor.

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin