Abstract: An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoids protocol processing for data transfer over the fast-path, freeing host bus bandwidth, and the data need not cross the I/O bus, freeing I/O bus bandwidth. The storage unit may include RAID or other multiple drive configurations and may be connected to the INIC by a parallel channel such as SCSI or by a serial channel such as Ethernet or Fibre Channel.

Abstract: The information required to configure a device for each network that a device encounters is stored for subsequent retrieval. Thereafter, when the device re-encounters each network, this information is used to automate the configuration of the device to access the encountered network. To uniquely distinguish each network, the network identifier is created via a hierarchical process that combines the network's service set identifier (SSID), the Internet protocol (IP) address, and the access device's MAC address.

Abstract: The disadvantage of the conventional wireless LAN is that it cannot increase the transmission speed until the standard is revised. Even though a proprietary technology can be developed, it would be inconvenient for users because it lacks generality.

Abstract: A method and system providing a client with user interface information are described. An accessibility system for providing user interface information to a client. The accessibility system comprises an accessibility system core including user interface automation services and APIs. The user interface automation tools filter information based on whether the user interface information is interesting to the client. The accessibility system additionally comprises a client side interface including a logical tree for revealing user interface information that is interesting to the client and for hiding user interface information that is not interesting to the client. The accessibility system also comprises a server side interface for facilitating information transfer from a server side regardless of the server side technology.

Abstract: The method includes querying for one or more logical unit numbers (LUNs) pertaining to a small computer system interface device, each LUN representing a potential path from a host to the SCSI device. Response data indicative of multiple devices, with each separate instance representing a different SCSI separate instances of independent SCSI devices, with each separate instance representing a different SCSI device structure. A unique identifier (UID) is calculated for each SCSI device structure, from which a device file is generated based on the UID and contains UID and path information that differentiates between multiple paths from the host to the SCSI device.

Abstract: A data bus width conversion apparatus is provided for receiving N-bit data from a first device having a first bus width and outputting the N-bit data to a second device having a second bus width. The first device divides the N-bit data into a plurality of bit data groups and the plurality of bit data groups are transferred to the apparatus. The apparatus comprises a setting section for setting the total number of transfer operations required for the first device to transfer the plurality of bit data groups, and for setting a division pattern of the N-bit data for dividing the N-bit data into the plurality of bit data groups, a receiving section, and an output section for producing the N-bit data from the received data indicated by each of the plurality of bit data groups and outputting the produced N-bit data to the second device.

Abstract: In the method, a logical unity is queried with a first command requesting first identifier data, to determine whether a unique identifier (UID) for the logical unit can be constructed based on the first identifier data. If a UID cannot be constructed from the first identifier data, the logical unit is queried with a second command requesting second identifier data, to determined if a UID can be constructed based on the second identifier data. If a UID cannot be constructed based on the second identifier data, the logical unit is queried with a third command requesting third identifier data. Information is extracted from the first identifier data and from the third identifier data and a UID is generated based on the extracted information.

Abstract: A system and method for improving the usability of electronic products. Control devices such as keyboards, mice, and switches, for example, are often accompanied by software which allows users to configure the device response to suit their physical abilities, situation and task. The system and method enables automatic configuration of such control devices in real time to match the user's requirements and enables users to achieve accurate control. The system includes a device for monitoring user activity and determining an appropriate device configuration from user activity sequences with that device, and a configurer that implements the appropriate configuration determined by the algorithm. The method further includes optional steps for identifying when a user with different configuration requirements starts to use a device, and for resetting the state of an inference algorithm when such changes are detected. This allows rapid configuration in environments where many individuals may use the same device.

Abstract: An interface converter for functionally connecting external devices having interfaces complying with different standards. The interface converter includes a USB-ATAPI command converter and a USB-ATA command converter. A switching controller checks the type of the interface of each external device and activates one of the command converters in accordance with the result of the checking.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.

Abstract: An atomic memory migration apparatus and method are provided. With the apparatus and method, all active DMA mappings to a given physical page of memory are identified and future mappings/unmappings to the physical page are serialized with migrations of current mappings. The identified DMA mappings are then disabled at the bus level and the physical page is migrated to a new memory page. All existing DMA mappings are also migrated to the new page. After migration is completed, the DMA mappings, which have now been migrated to the new page, are reenabled at the bus level.

Abstract: In one embodiment, the invention provides a method comprising determining information about an input/output device located north of the memory controller; and controlling a response of the memory controller to read/write requests on a processor bus to a bus agent on a system bus south of the memory controller based on the information.

Abstract: The present invention provides an information processing apparatus, a program and a system in which a user sets data about electric power conditions in the information processing apparatus so as to reduce electric power consumption of the input/output device when the user is not in front of the input/output device.

Abstract: A filter driver code arrangement (on a computer-readable medium for use in a system having a bus, a host connected to the bus and one or more devices connected to the bus), which prevents access by the host to any of the devices for which the host does not have respective access permission. Such a filter driver includes: an intercept code portion to intercept a set of data identifying one or more devices connected to the bus, respectively; a determination code portion to determine, based upon the data set and a permission set representing permission relationships between the host and the one or more devices, whether the host has permission to access each of the one or more devices; and a change code portion to change the data set to block access by the host to any of the one or more devices for which the host does not have access permission.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs the parallel data to the main memory. This eliminates the need for the CPU downloading file data from the flash memory to the main memory, allowing connection of a non-volatile memory with a large capacity, without reduction in the processing speed of the system.

Abstract: Data received by a Bluetooth wireless unit is buffered on a DRAM. At this time, a CPU (which operates on the basis of a description of HDD startup control program calculates the data transfer rate of the Bluetooth wireless unit and the free area size of a buffer area on the DRAM, and also calculates the remaining time until the buffer data on the DRAM becomes full of data, on the basis of these values. When the calculated remaining time has reached a required startup time of an HDD indicated by remaining time determination data A stored in a flash memory, the CPU starts up the HDD.

Abstract: A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operation; accessing a leading bit of the set of input data bits from the latch circuit in advance of a read operation; and enabling in a read operation the rest of the input data bits in the latch circuit to be transferred to the shift register to be output with the leading bit.

Abstract: An interface system includes a host interface and a device interface. Both interfaces are provided between a DVD drive and a MPEG2 decoder, which have an ATAPI protocol interface. When the host interface receives ATAPI protocol data from the MPEG2 decoder, it converts the ATAPI protocol data to high speed LAN protocol data, and transmits the converted data to the device interface. When the device interface receives converted data, it converts them to the ATAPI protocol data, and transmits the ATAPI protocol data to the DVD drive.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A code arrangement, for use on a host connected via a bus to one or more, e.g., devices, causes stacks representing one of the devices to be disassembled such that rebuilding the stacks does not require physical disconnection and reconnection of the device(s). Such a stack includes a lower device object (DO) associated with the bus driver and an upper DO in the stack located above the lower DO. The upper DO is recognized as the physical DO (PDO) by a data structure associated with the device in a device tree. Such a code arrangement accomplishes: removal of each DO from the stack located above the lower DO including the PDO, the lower DO associated with the bus driver surviving as a remnant DO; and change of a state of the data structure in the device tree to permit rebuilding of the stack based upon the remnant DO.

Abstract: A memory system (e.g., memory card) that is able to operate internally in accordance with a first protocol while communicating externally in a second protocol is disclosed. In one embodiment, a memory card operates in accordance with a memory card protocol (e.g., MMC) internally and communicates with a host over a bus protocol (e.g., I2C). As a result, communications between the memory card and the host can utilize the bus protocol by having the bus protocol include the memory card protocol. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: A method for disconnecting a channel of a SCSI (small computer system interface) controller from a SCSI bus is disclosed. The method includes receiving a signal that prompts the SCSI controller to assume a mode that the SCSI controller is not configured to accommodate. Further, the method includes disabling a channel of the SCSI controller by entering a state that disconnects the channel of the SCSI controller from the SCSI bus.

Abstract: A circuit generally comprising an interface circuit and an arbitration circuit is disclosed. The interface circuit may be couplable between a peripheral device and a plurality of ports. The arbitration circuit may be coupled to the interface circuit. The arbitration circuit may be configured to (i) store a plurality of associations between a plurality of time slots and the ports, (ii) check the associations in a subset comprising at least two of the time slots in response to receiving an arbitration request from a first requesting port of the ports, and (iii) generate a grant for the first requesting port to communicate with the peripheral device in response to the first requesting port matching at least one of the associations in the subset.

Abstract: A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: The present invention aims at providing efficient bus arbitration. Counters respectively provided for an encoding section and an decoding section are started when there is input of request signal from the respective encoding section and decoding section. The counter values are outputted to respective comparators that compare the counter values with predetermined values to then output the result of comparison to an arbitration controller. The arbitration controller in turn determines priority ranks for the encoding section and the decoding section based on the signals inputted from the comparators and outputs an acknowledgement signal to the module that has the highest priority. The present invention may be applied to LSI's.

Abstract: A method and apparatus for managing the execution on guest processors of a broadcast instruction requiring a corresponding operation on other processors of a guest machine. Each of a plurality of processors on an information handling system is operable either as a host processor under the control of a host program executing on a host machine or as a guest processor under the control of a guest program executing on a guest machine. The guest machine is defined by the host program executing on the host machine and contains a plurality of such guest processors forming a guest multiprocessing configuration. A lock is defined for the guest machine containing an indication of whether it is being held by a host lock holder from the host program and a count of the number of processors holding the lock as guest lock holders. Upon decoding a broadcast instruction executing on a processor operating as a guest processor, the lock is tested to determine whether it is being held by a host lock holder.

Abstract: A memory card converting device mainly has a base with one lateral side thereof formed as an inserting end; from the inserting end to the inner portion of the base, a slot is disposed by overlapping the spaces for receiving memory cards of different standards, such as a smart media card, a multimedia card, a secure digital card and a memory stick card. Those memory cards utilize the sharing slot to convert and read the data signals between the memory card and said converting device. The main feature of the present invention is that a slot is defined in said slot for receiving an XD memory card thereby extending the application of said converting device to support memory cards of different standards.

Abstract: An apparatus and system may include a peripheral device, such as an interrupt controller or Peripheral Component Interconnect (PCI) bridge device, having a memory-mapped legacy register and a PCI dummy register. The legacy register may be accessed by a Basic Input/Output System (BIOS) as part of a power-on initialization sequence for the peripheral device, and the dummy register may be accessed during a hot-plug operation using code executed by an Operating System (OS). An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a method of representing a peripheral device which includes identifying the peripheral device as a legacy device in a name space, such as an Advanced Configuration and Power Interface (ACPI) name space, and identifying the peripheral device as a dummy PCI device capable of being accessed during a hot-plug operation.

Abstract: A laptop computer and mating docking station where the docking station provides power to the laptop computer over power rails of the Universal Serial Bus (USB) interface. The laptop computer has laptop docking logic that both provides power in accordance with standard USB protocol, and also receiving power across the power rails of the USB interface. Likewise, the docking station has a docking station dock logic that establishes communication with the laptop docking logic across the USB power rails. Once positive communication is established, the dock station provides voltages on the USB power rails sufficient to power the laptop computer as well as charge the laptop's battery.

Abstract: A signal processing resource system with multiple sets of coefficients, channel context memories, and configuration control logic sets organized into signal processing personalities which are multiplexed in their use according to input data organization. Adaptable signal processing characteristics, processing suspension, processing resumption and seeding of signal processing context is provided. Control logic allows a data stream to be processed using multiple signal processing characteristics or “personalities” according to associations or groupings of coefficient, channel context, and control logic sets.

Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.

Abstract: A playback apparatus including a playback unit which plays back audio information and the like, an accommodation unit which accommodates a detachable recording medium, and a controller. The controller causes the playback unit to access to the recording medium through the accommodation unit according to a first communication standard (PCMCIA) and causes an external apparatus to access to the recording medium according to a second communication standard (ATA) different from the first communication standard.

Abstract: For an LSI generated on a single semiconductor substrate, a built-in CPU core, a memory controller, an external bus interface that can connect an external CPU chip from outside of the single semiconductor substrate, and a system bus bridge that mutually connects the built-in CPU core, the memory controller and the external bus interface are provided, so that the system structure can flexibly be changed by adding or exchanging an external CPU chip according to required performance.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.

Abstract: An improved backplane with an accelerated graphic port (AGP) in industrial computer for electrically connecting a CPU interface card therein. The backplane has at least a first type bus expansion slot, a second type bus expansion slot, a bus bridge device, and an AGP slot mounted thereon. The bus bridge device is designed as converting different-type bus signals between the first type bus expansion slot and the second type bus expansion slot when the first type bus expansion slot receives the CPU interface card therein. By way of the design of mounting the AGP slot and the bus bridge device on the backplane, the volume of CPU interface card can be reduced and therefore does not occupy the demanded space of other adjacent interface cards, and converts a variety of signals from the backplane.

Abstract: A digital camera (10) includes a shutter button (50). When the shutter button (50) is depressed, a file name and size information “0” is written into a directory entry of a recording medium (44), and a movie file to which a plurality of markers are assigned in a predetermined manner is recorded in a data area of the recording medium (44). Upon completion of recording the movie file, FAT information showing a ring state of the movie file is written into an FAT area of the recording medium (44), and size information of the directory entry is rewritten. The file name of the latest movie file is stored in a non-volatile memory (M), and a CPU (46) detects the size information of the latest movie file from the directory entry based on the file name when a power switch (54) is input. When the detected size information indicates “0”, the FAT information is created based on the marker assigned to the latest movie file.

Abstract: An information recording/reproduction apparatus according to one aspect of this invention includes a first recording/reproduction unit configured to execute recording, reproduction, and deletion of information for a built-in first recording medium, a second recording/reproduction unit configured to execute recording and reproduction of information for a detachable second recording medium, a recording control unit configured to control to record a library information file, that contains a plurality of pieces of library information corresponding to a plurality of contents information recorded on the first and second recording media, on the first recording medium, and a deletion control unit configured to execute a process for deleting all pieces of library information contained in the library information file, and a process for deleting all pieces of contents information recorded on the first recording medium.

Abstract: The present invention relates to an enclosure that protects an operational data storage device (preferably a common disk data storage devices with an IDE interface) from fire, flood or other hazards. The preferred embodiment comprises an enclosure which is water resistant and heat transfer protected to preserve the disk data storage device in the event of disaster involving flood or fire. Insulation, including phase change materials, are used to maintain internal temperature during normal operation and during fire conditions, so as to meet the thermal test portion of UL 72, Class 125, one hour, and the disk data storage device temperature does not exceed 125° C. The enclosure of the preferred embodiment manages humidity to an internal RH at 80% or below.

Abstract: A computer system is provided having a register stack engine to manage data transfers between a backing store and a register stack. The computer system includes a processor and a memory coupled to the processor through a memory channel. The processor includes a register stack to store data from one or more procedures in one or more frames, respectively. The register stack engine monitors activity on the memory channel and transfers data between selected frames of the register stack and a backing store in the memory responsive to the available bandwidth on the memory channel.

Abstract: A control device for preparing redundant data, dividing the data into a plurality of volumes, and distributing and storing volumes in a plurality of storage units scattered through a network includes a route management unit and a storage set management unit. The route management unit computes an evaluation value indicating the preferability of a use target on each of the scattered storage unit based on the bandwidth, the communications cost, the physical distance between a node requesting a write and a storage unit. The storage set management unit selects a plurality of storage units as the optimum storage set from among the above mentioned scattered storage units based on the evaluation value.

Abstract: An improved method of operation for a motor vehicle microcontroller uses flash memory (FM) for storing generic data and emulating an EE memory device. The FM is divided into first and second banks, with the first bank being utilized for generic data and the second bank being utilized for EE data, allowing EE data to be updated while the microcontroller accesses stored generic data. The second bank is partitioned into sectors that are individually erasable, and EE data is updated by storing the updated EE data into an unused sector, flagging the old sector to indicate that it contains invalid data, and later erasing the old sector to make it available for future updates of EE data.

Abstract: Provided is a method of storing data in a non-volatile memory, including generating and storing logs including data to be stored and an address of the non-volatile memory in response to a data-writing request, and comparing addresses of the logs and storing data corresponding to the same page by the unit of page in a corresponding area of the non-volatile memory. The method makes it possible to minimize delay in storing data, reduce the number of accesses to the non-volatile memory and uniformly write data in the whole non-volatile memory, thereby minimizing a response time of the non-volatile memory and increasing the lifetime of the non-volatile memory.

Abstract: A first storage unit is accessed randomly in a unit equal to or greater than a predetermined data unit. The first storage unit stores a target program required to be read randomly in a unit smaller than the data unit to execute. A second storage unit stores a reading program for reading the target program from the first storage unit. A control unit reads the target program from the first storage unit according to the reading program of the second storage unit. The control unit stores the read target program to a third storage unit that can be accessed in a unit smaller than the data unit. The control unit executes the target program stored in the third storage unit to gain access randomly to the first storage unit in a unit smaller than the data unit in a quasi manner.

Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Abstract: In one embodiment, a disk array storage system includes multiple disk drive modules that contain sets of drives and a number of storage controllers. Each storage controller is connected to a group of disk drives from two or more disk drive modules. The number of disk drives from the same disk drive module that are connected to the storage controller does not exceed a predefined number.

Abstract: A data replication system having a redundant configuration including dual Fibre Channel fabric links interconnecting each of the components of two data storage sites, wherein each site comprises a host computer and associated data storage array, with redundant array controllers and adapters. The system employs the grouping of logical units into ‘association sets’, for logging and failover purposes. The concept of association sets allows the system provides for proper ordering of I/O operations during logging across multiple volumes. In addition, association sets are employed by system to provide failure consistency by causing the group of logical units/volumes to all fail at the same time, ensuring a point in time consistency on the remote site.