Abstract: A system and method for strong access control to a network is provided. An access control server and authentication device are provided for controlling access to a network. The access controlled by the access control server may include network protocols, network resources, and electronic devices that may be coupled to the network. Network resources may include data stored on the network. The access control server may grant access to the network to a user based upon a correct response received from an authentication device assigned to the user. The user may be able to access only selected data that may be determined by an access level assigned to the authentication device. Upon authentication, the authentication device must remain active to maintain a network session. The authentication device becomes inactive when it is deactivated, uncoupled from the network, or in any mode in which the device cannot produce a response to the access control server.

Abstract: A method in a system for transferring accounting information, a system for transferring accounting information, a method in a terminal, a terminal, a method in an Extensible Authentication Protocol (EAP) service authorization server, an EAP service authorization server, a computer program, an Extensible Authentication Protocol response (EAP-response) packet, wherein the method:

Abstract: The invention proposes a directory server capable of interacting with entries organized in a tree structure in a directory server system. The entries comprise user entries. The directory server has a password checking function capable of checking the password for a user entry, based on password-related data. The password checking function is responsive to a user entry having extra data associated thereto, and identifying an additional entry, for executing a distinct password checking based on the password related data defined in that additional entry.

Abstract: An apparatus for remotely controlling the power of an information handling system which includes a power supply, an input output (I/O) controller, a power button coupled to the I/O controller and a power management controller coupled to the I/O controller. The power management controller receives a power command signal and generates a remote power signal based upon the power command signal. The remote power signal controls the power supply via the I/O controller.

Abstract: A computer system (200) includes a baseboard (202) having a first side (201) and a second side (203), where the first side and the second side define a first key opening (205) and a second key opening (207). A mezzanine card interface (208) is coupled to the baseboard. A keying mechanism (219) is coupled to interface with the baseboard through the first key opening, where coupling the keying mechanism to the baseboard initiates a first key signal (225), and where the first key signal operates a logic circuit (229) to permit a first operating voltage (218) to power the mezzanine card interface. Alternatively, the keying mechanism can be coupled to interface with the baseboard through the second key opening, where coupling the keying mechanism to the baseboard initiates a second key signal (227), and where the second key signal operates the logic circuit to permit a second operating voltage (220) to power the mezzanine card interface.

Abstract: One embodiment of the present invention provides a system that facilitates controlling the rate at which instructions are executed by a microprocessor. The system starts by receiving a signal indicating the existence of a throttling condition. In response to the throttling condition, the system reduces the rate at which instructions are executed by the microprocessor. In a variation on this embodiment, the throttling condition can include a processor idle state, a processor overheating state, or a power over-consumption state.

Abstract: One data processor (101) is provided with an interface means (119) for realizing connection with the other data processor (100), this interface means is provided with a function for connecting the other data processor as a bus master to an internal bus (108) of one data processor, and the relevant other data processor is capable of operating in direct peripheral functions memory mapped to the internal bus from an external side via said interface means. Accordingly, the data processor can utilize the peripheral functions of the other data processor without intermission of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Abstract: A circuit that enables a safe power-on sequencing is described. The circuit enables a processor to be powered by an internal or external voltage source. The circuit detects for the presence of an external voltage regulator. If an external voltage generator is not providing a valid voltage source to the processor, the circuit enables an internal voltage regulator to provide a stable voltage source.

Abstract: Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge.

Abstract: A method for a fully digitally controlled delay element with wide delay tuning range and small tuning error. The method of one embodiment comprises receiving a set of digital control bits at a delay element. The set of digital control bits is to alter the amount of delay provided from the delay element to an input signal. A driving current through a first driver of the delay element is adjusted with the digital control bits. A capacitance on an output node of the delay element is adjusted with the digital control bits. The output is a delayed version of the input signal based on the driving current and the capacitance.

Abstract: Trigger reception on different instrumentation devices may be synchronized by each instrumentation device generating one or more trigger enable signals and delaying performance of an operation in response to a trigger signal until a transition in a trigger enable signal. An instrumentation system may include several instrumentation devices and a communication medium coupling the instrumentation devices. One of the instrumentation devices may process data in response to a sample clock signal. That instrumentation device may also generate a trigger enable signal and delay performing an operation in response to a trigger signal transmitted via the communication medium until a transition in the trigger enable signal occurs. The trigger enable signal is not the sample clock signal. The trigger enable signal may be synchronized to another trigger enable signal generated by another one of the instrumentation devices.

Abstract: A system and method for switching clock sources is presented. One embodiment of the system comprises a main clock and removable card having normally unused pins. The removable card is configured to host a secondary clock. This embodiment of the system further comprises a clock-selection circuit configured to determine whether or not the removable card is hosting the secondary clock. If the clock-selection circuit determines that the removable card is hosting the secondary clock, then the clock-selection circuit selects the secondary clock and the signal from the secondary clock is relayed through the unused pins. If, on the other hand, the clock-selection circuit determines that the removable card is not hosting the secondary clock, then the clock-selection circuit selects the main clock.

Abstract: A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.

Abstract: A apparatus for controlling in-system programming for repairing a malfunctioned programmable element in an electronic device without disassembling the casing or replacing a new element chip includes an apparatus equipped with an in-system programming chip to connect the programmable element that has faulty program codes or data to another normal computer. By means of the apparatus of the invention, the program codes or data on the programmable element may be reprogrammed to fix the problems or defects of the programs to resume normal operation, and to speed up repairs and reduce waste of manpower.

Abstract: This invention is for updating a straight mapping flag in an optical recording medium having defect table blocks (DTBs) in a detect table (DT). When data that should be recorded in a predetermined block in one data area is later recorded in a replacement block in one spare area because the predetermined block is defective, record associated information in a entry in one DTB, and the entry is marked as recorded and sequentially arranged. Determine an examining sequence of the DTBs with a predetermined block-sequence determination procedure and perform a predetermined block-examining procedure to the DTBs one by one with the determined examining sequence. Examine whether the DTB comprises any recorded entries. Examine the recorded entries with a predetermined entry-examining procedure, to acquire the associated information of the defective blocks in recorded entries and update the corresponding straight mapping flag to be non-straight mapping based on the acquired associated information.

Abstract: In one embodiment of the invention, an environmental condition relating to a first device is monitored. The first device operates in a first performance state. A limit command is generated based on the environmental condition requesting the first device to adjust the first performance state to a second performance state.

Abstract: One embodiment of the present invention provides a system that improves reliability in a compute processor by re-executing instructions. During operation, the system issues an instruction to an execution unit within the computer processor. The execution unit subsequently executes the instruction to produce a first result. If an idle execution slot becomes available, the system reissues the instruction to the execution unit, which causes the instruction to be executed a second time to produce a second result. The system then compares the first result with the second result. If the first result is not identical to the second result, the system flags an error.

Abstract: A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and debug slave signals to debug slave central processing units. An executive master test access port controller responds to the external test signals and controls the test signal multiplexer. A control register loadable via the executive master test access port stores the debug slave signals. A test data output multiplexer connects the test data output line of the selected debug master central processor unit to an external test data output line. The external test signals includes a debug state signal supplied to each central processing unit. This selects either a normal mode or a debug mode at each central processor unit.

Abstract: Filtering trees for selectively notifying subscribers of events are provided, and are constructed with OR nodes to substantially reduce their size. The filtering trees have nodes representing event variables that ultimately branch to leaf nodes thereunder, and the leaf nodes identify which of a set of queries are satisfied by an actual event. A mechanism recursively merges nodes of trees into a single tree, and uses OR nodes when nodes cannot be combined, to essentially add a parallel path in the resulting tree to traverse. Nodes that can be combined are those that represent the same event variable, and may have data points that are merged into a combined node. Threshold gains in efficiency may be evaluated to determine whether the original trees should be kept instead of the resulting tree.

Abstract: An event subscription and publication system for dynamically notifying user level applications of kernel level events. The kernel level events may include hardware and software events as well as system level errors that occur in the kernel. User level applications that need information on these kernel level events subscribe to the event monitoring and publication framework of the present invention and are notified of these kernel level events when they occur. Upon notification of an event, the user application also is provided with specific information classifying the nature and details of the event. The kernel event monitoring and publication system of the present invention allows user level applications to be dynamically notified of kernel level events without requiring the user level application to interrupt the normal processing states to identify these events when the events occur.

Abstract: Methods, systems and computer program products are provided for evaluating performance of a network that supports packetized communications. A network test protocol that is associated with the packetized communication is initiated and network performance data is obtained based on the initiated network test protocol. An overall network quality rating is generated based on the obtained performance data and a network impairment indicator is calculated based on the overall network quality rating.

Abstract: EEH methods are used during the boot process to actively disable a defective PCI adapter, thereby allowing the system boot to continue without disruption. This allows faulty adapters to be present in the machine without interrupting the boot process. The slots appear to be empty and the devices/adapters residing therein can be actively “hot swapped” out without altering the rest of the machine state.

Abstract: An interactive multimedia system for remote diagnostics of, maintenance of, and assistance pertaining to a multifunction peripheral preferably includes a multifunction peripheral, a remote service endpoint, and a network system over which the multifunction peripheral communicates with the remote service endpoint. An audio/visual capture device and a display are preferably communicatively associated with the multifunction peripheral communication entity. The remote service endpoint provides assistance based on the audio/video data over the display in such exemplary forms as text, images, multimedia presentation, audio presentations, video presentations, or live interactive communications. The present invention is also directed to a method performed by a multifunction peripheral that provides interactive multimedia for remote diagnostics of, maintenance of, and assistance regarding a multifunction peripheral.

Abstract: In a semiconductor chip having a plurality of processing unit fabricated thereon, each of the processing units is provided switches having input terminals coupled to selected nodes of the processing unit. A debug port is provided for all of the processing units. The output terminals of a switch in each processing unit is to an output terminal of the debug port. The trace signals applied to the output terminals of the debug port are selectable thereby permitting any combination of states determined by the processing units to be applied to the output terminals. The output terminals of the debug port can have any combination of trace signals, trace clock signals, a high impedance states, and other functions applied thereto.

Abstract: JTAG operations are carried out remotely over a network interface. The host processor includes a JTAG interpreter and a host side JTAG driver. A target device includes a target side JTAG driver. The interpreter processes and translates JTAG design files. The host side JTAG driver generates messages for the target side JTAG driver based on the translation. The host JTAG driver delivers the messages to a host network interface. The host network interface is connected via a network link to a target network interface. The target network interface is connected to the target side JTAG driver. The target side JTAG driver communicates with a target boundary scan chain. The target side JTAG driver and host side JTAG driver communicate over the network link. Network overhead is reduced by buffering messages until a message requiring a return of test data is ready for transmission.

Abstract: A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

Abstract: A method for improving data accuracy and data flow of a disc servo system to read data on a disk. First of all, a read mode of the disc servo system is determined. If the read mode is an audio/video play mode, a first read procedure to read the data on the disk is executed. If the read mode is a document read mode, a second read procedure to read the data on the disk is executed. The second read procedure is different from the first read procedure. Finally, the data is output to further processes.

Abstract: A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Abstract: It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.

Abstract: A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.

Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

Abstract: A system (5) for testing and failure analysis of an integrated circuit (10) is provided using failure analysis tools (40, 50, 60). An analysis module (30) having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools (40, 50, 60) to be used. The rest of the integrated circuit contains function modules (20) arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module (30) using the failure analysis tools (40, 50, 60), physical parameters of the integrated circuit (10) are obtained and used in subsequent testing of the function modules (20) by the failure analysis tools (40, 50, 60), thus simplifying the testing of the integrated circuit (10) and reducing the time taken to perform a failure analysis procedure.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: The invention relates to a method for correcting errors by de-embedding dispersion parameters of a measuring object associated with measuring gates (11), said parameters being measured by a vectorial network analyst comprising n measuring gates. The aim of the invention is to create a universal, precise and fast means of correcting errors of dispersion parameters. To this end, the method comprises the following steps: formula (1) two-port calibrations are carried out on different calibrating standards in any order in the active state between the measuring gates (11), as a basis for a first error correction; the reflection parameters of at least one part of the n measuring gates (11) are determined in the inactive state, by means of the results of two-port measurements carried out on at least one calibrating standard switched in the active and/or inactive state on measuring gates (11), as a basis for a second error correction.

Abstract: A system and method are provided for a transmitter to delay message retransmission in a noise environment, where a communications network uses a shared channel. The method comprises: transmitting a message on a shared channel, such as a ac powerline medium; failing to receive a received message acknowledgement; deciding that the transmission error is due to a noise; postponing the retransmission of the message; and, following the channel noise transmission error decision, releasing the channel for use by other transmitters. Deciding that the transmission error is due to channel noise includes: monitoring received signals; and, distinguishing between transmission collisions and noise.

Abstract: A method transforms a generalized parity check matrix representing a linear block binary code. First, an input generalized parity check matrix is defined for the linear block binary code. Auxiliary sets are formed from the input generalized parity check matrix and organized into a partially ordered set. The subsets of each auxiliary set are ordered in a list, and parity check equations are constructed from the list of ordered subsets. The parity check equations are translated into an output generalized parity check matrix, which can be used to decode a message encoded according to the linear block binary code.

Abstract: The Turbo decoding architecture has a first soft-input soft-output (SISO) device having a complex trellis structure and a Turbo decoder loop with a second SISO device having a simpler trellis structure. Coded information from a channel is processed by the first SISO device to generate a soft-output based on the coded information. The soft-output is then processed in an iterative loop using the second SISO device. The second SISO device interacts with a decoder device to produce a value representative of the transmitted information.

Abstract: In a decoder, the BER is calculated during a decode operation of the decoder. Access to decoder components for obtaining signal data for use in calculating the BER is provided during the decode operation when the components are not used by the decoder. An HDA early termination signal is used to confirm an accurate BER calculation.

Abstract: A system for soft-decoding of Reed-Muller coded information has one or more rows of decoding blocks, each decoding block having a soft-output device and a Reed-Muller message passing device. A first soft-output device of a first decoding block processes a coded signal and a zero value probability vector. Each subsequent soft-output device processes the coded information and a non-zero value probability vector. The system for soft-decoding Reed-Muller coded information decodes a code-bit reliability vector from a soft-output device to generate an updated codeword reliability vector, which is used by a next decoding block in a sequence of decoding blocks to reprocess the coded information using the updated reliability vector. The reliability vector is updated through processing in each decoding block to optimize the reliability vector for extraction of the transmitted information from the received information.

Abstract: A maximum likelihood decoder includes metric generators for generating metrics based on a plurality of partial responses and a Viterbi decoder for realizing maximum likelihood decoding by using a synthetic metric generated by synthesizing the metrics. A first partial response is an original partial response. A second partial response is a differential response generated by subtraction by shifting the first partial response by 1 clock. Alternatively, the differential response may be generated by subtraction by shifting the first partial response by 2 clocks. The second partial response may be a response generated by addition by shifting the first partial response by 2 clocks. Alternatively, the second partial response may be an integration response generated by adding all previous samples of the first partial response.

Abstract: In the Viterbi decoder for decoding a trellis-coded modulated signal of this invention, a path memory is constructed of a general RAM, whereby the circuit size and power consumption are reduced. A trace-back section traces back path select signals stored in a trace-back memory by a predetermined length. Using the number of a node through which a most likely path passes obtained by the tracing back and in accordance with a trellis diagram, a subset number generator section outputs coding bits relating to transition to the node concerned and a subset number. A selector section selectively outputs a noncoding bit relating to the transition to the node based on the subset number.

Abstract: A novel and useful interleaver/de-interleaver mechanism for reducing the latency of transmitted interleaved codewords. The interleaver/de-interleaver mechanism utilizes a shortened first codeword which functions to offset the interleaving and transmission of subsequent codewords so as to achieve reduced latency depending on the degree of shortening applied. The interleaver/de-interleaver mechanism is particularly useful in power line carrier based systems to reduce the exposure to burst errors by providing interleaving with minimal latency penalty.

Abstract: The present application describes systems and methods for composing documents using a digital pointing instrument. In further configurations, a user utilizes a pen to partially fill in a form and provide destination data whereby a forms processor adds additionally required information to the form in order to compose a complete form that is sent to the destination.

Abstract: In a document management system including a plurality of document storing devices storing document information, respectively, a recording device records progress status information of an operation of each document storing device. A retrieving device checks, when the document management system is activated, the recorded progress status information of an operation of each document storing device to retrieve a document storing device that cannot be activated. A progress status information acquiring device acquires from the recording device progress status information of an operation of the retrieved document storing device. A fault recovery process content acquiring device acquires a content of a fault recovery process relative to the retrieved document storing device based upon the acquired progress status information of an operation of the retrieved document storing device.

Abstract: An object of the present invention is to provide a multi-function peripheral which is easy for a user to operate. To achieve the object, according to the present invention, there is provided a peripheral connected to an information processing apparatus, which inputs and analyzes a job script constituted of packet data from the information processing apparatus, and subsequently generates an appropriate job file in accordance with the content of the job script.

Abstract: A workflow creating apparatus stores rules (311) for creating workflows and environmental information (312) relating to execution of each process constituting the workflow in advance in an auxiliary storage. When output requirements (310) constituted by attribute values for an image recording media such as film, press plates, or printed matter etc. taken as finally resulting matter are designated by user operations, the processes required to make an image recording media satisfying the output requirements (310) are decided upon and the parameter values for each of the required processes are set by applying workflow creation rules (311) to each of the attribute values of the output requirements (310). A workflow is then created taking into consideration environmental information (312) based on results of applying these rules and tickets (321 to 323) corresponding to this workflow is created.

Abstract: The present application describes systems and methods for composing documents using a digital pointing instrument. In further configurations, a user utilizes a pen to trace a form serial number that is utilized to identify a form template that is used to process input data from a digital pen.

Abstract: A system and method for generating source code that creates an XML document is presented. Processing identifies tags within an HTML file and generates a hierarchical file that includes an element for each tag using a Jtree Java class. A developer enters general attribute values and validation attribute values corresponding to each element. A code generator generates a source code file that includes code for each element. The source code file is input into a Java Virtual Machine (JVM). The JVM receives data values from the HTML file, validates the data values, and generates the XML document.

Abstract: A system and method for generating an invoice. An Internet Markup Language (IML) file includes a first set of IML tags defined by a document type definition that are used to select data for inclusion in the invoice and a second set of IML tags defined by the document type definition that are used to specify a layout for the invoice including the selected data. An invoice generating application accesses a database of a service provider to collect data according to the first set of tags and uses the collected data and the second set of tags to generate an invoice output file. The invoice output file may then be provided to an output device to generate the invoice.