Abstract: A chromene compound typically represented by the following formula, 1

Abstract: A mechanical assembly for pulling the form work away from a concrete structure after the concrete structure has cured. The form work is typically wood or steel and requires a large mechanically force to free it from the concrete structure. The form puller assembly includes a lever assembly, a fulcrum assembly, and a form pulling assembly. The user pulls down on the opposite end of the lever assembly generating a mechanical force sufficient to free the form work from the concrete structure. Also, the mechanical assembly may include at least one embedded element extracting assembly for removing vertically oriented elements embedded in the soil and/or concrete.

Abstract: The invention relates to a photocathode having a structure that permits a decrease in the radiant sensitivity at low temperatures is suppressed so that the S/N ratio is improved. In the photocathode, a light absorbing layer is formed on the upper layer of a substrate. An electron emitting layer is formed on the upper layer of the light absorbing layer. A contact layer having a striped-shape is formed on the upper layer of the electron emitting layer. A surface electrode composed of metal is formed on the surface of the contact layer. The interval between bars in the contact layer is adjusted so as to become 0.2 &mgr;m or more but 2 &mgr;m or less.

Abstract: Disclosed is a III-nitride compound semiconductor nanophase opto-electronic cell, comprising a silicon substrate (100), and an amorphous silicon nitride layer (base) (200) formed on the substrate and including III-nitride compound semiconductor nano grains (230) spontaneously formed therein. The nitride semiconductor nanophase opto-electronic cell and the fabrication method thereof according to the present invention are free from the problems of the conventional III-nitride compound semiconductor thin film growth on silicon substrates. Accordingly, a high-quality III-nitride compound semiconductor nanophase opto-electronic cell having no crystalline defect can be provided. Furthermore, the opto-electronic cell according to the present invention does not require a p-type GaN thin film so that there is no possibility of causing crack that is a problem in the conventional method of fabricating a III-nitride compound semiconductor opto-electronic cell using III-nitride thin films grown on silicon substrates.

Abstract: The invention relates to a wavelength-converting reaction resin compound (5) into which a wavelength-converting luminescent material (6) and a thixotroping agent are mixed, wherein the luminescent material contains inorganic luminescent particles. The thixotroping agent is present, at least in part, in the form of nanoparticles. Methods of producing the reaction resin compound and light-emitting diode elements having such reaction resin compounds are indicated.

Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.

Abstract: A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A dielectric layer for use in electronic devices can be obtained from a polymerizable mixture containing at least one organic amine derivative, which is capable of forming a crosslinked polymer with itself and/or with at least one multifunctional compound, and/or its crosslinked polymer product obtainable by crosslinking said amine derivative with itself or with at least one multifunctional compound. Thus, the polymerizable amine mixture can advantageously be used in a process for the manufacture of a dielectric layer of an electronic device.

Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a. . . 301h, 302a. . . 302h), each pair of nested serpentine lines having a shared pad between them (312a. . . 312h).

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: The invention provides an active matrix type electro-optical device and an electronic apparatus using the same capable of preventing interference of light due to contact holes and interference of reflecting light from light-reflecting film. In a thin film transistor (TFT) array substrate of a reflective active matrix type electro-optical device, a light-reflecting film can be formed in a contact hole, but positions of the contact holes for electrically connecting a pixel electrode to a drain electrode, and irregular pattern for scattering light formed on the surface of the reflection film by a lower side irregularity-formation film are different in each of pixels formed in a matrix.

Abstract: A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same insulating substrate. A semiconductor display device includes a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Abstract: A semiconductor device comprises a first insulating film provided over a substrate and heat-treated, a second insulating film provided over the first insulating film, and a semiconductor film provided over the second insulating film, the second insulating film and the semiconductor film being formed successively without exposing them to the atmosphere.

Abstract: The invention provides methods for the production of full-color, subpixellated organic electroluminescent (EL) devices. Substrates used in the methods of the invention for production of EL devices comprise wells wherein the walls of the wells do not require surface treatment prior to deposition of electroluminescent material. Also provided are EL devices produced by the methods described herein.

Abstract: The present invention is generally directed to electroluminescent Ir(III) compounds, the substituted 2-phenylpyridines, phenylpyrimidines, and phenylquinolines that are used to make the Ir(III) compounds, and devices that are made with the Ir(III) compounds.

Abstract: A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device such as a light-emitting device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. Typically, the integrated circuit drives the semiconductor device. The two thin semiconductor films are formed separately from the substrate. The first thin semiconductor film may include an array of semiconductor devices. The first and second thin semiconductor films may be replicated as arrays bonded to the same substrate. Compared with conventional semiconductor apparatus comprising an array chip and a separate driver chip, the invented apparatus is smaller and has a reduced material cost.

Abstract: The invention relates to a device with at least two organic electronic components that comprise at least one organic functional layer, as well as to a method for producing the same. Unlike conventional devices, the inventive device comprises at least two components from organic material and is therefore substantially less expensive and less complicated to produce than known devices that require a combination of organic with conventional electronic components. The inventive device completely eliminates, under certain circumstances, the need for conventional silicon semiconductor technology.

Abstract: Disclosed are a GaN based compound semiconductor light emitting diode (LED) and a manufacturing method therefore. In the LED, a multi-layer epitaxial structure including an active layer is formed over a substrate, and a light transmissive impurity doped metal oxide which may be formed over a Ni/Au layer is used as a light extraction layer while the Ni/Au layer is taken as an ohmic contact layer between the light extraction layer and the multi-layer epitaxial structure. Then, an n-type metal electrode is disposed over an exposing region of an n-type semiconductor and a p-type metal electrode over the light extraction layer. The LED is thus formed.

Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Abstract: A light-emitting device includes: a semiconductor structure formed on one side of a substrate, the semiconductor structure having a plurality of semiconductor layers and an active region within the layers; and first and second conductive electrodes contacting respectively different semiconductor layers of the structure; the substrate comprising a material having a refractive index n>2.0 and light absorption coefficient &agr;, at the emission wavelength of the active region, of &agr;>3 cm−1. In a preferred embodiment, the substrate material has a refractive index n>2.3, and the light absorption coefficient, &agr;, of the substrate material is &agr;<1 cm−1.

Abstract: The Dual Carrier Field Effect Transistor is characterized by implementing different N-doped and P-doped regions to form channels with narrow cross-sectional area at z=Lz. The placement of the source terminal, the drain terminal and the contact terminal is of a two dimensional structure. This invention overcomes the restriction due to lithographic technology and the effective channel length can be reduced to as short as 5 nm even when presently standard semiconductor technology is used. The supply voltage can be decreased to 0.65V, and each transistor can be designed to have 3 to 12 channels to form Dual Carrier Field Effect Transistor complementary inverters and matrix system-on-a-chip with output current as high as 10 amperes. These devices can also be designed to form complicated, high speed and low power dissipation logic circuits as well as high frequency, low power dissipation microwave circuits and system-on-a-chip.

Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region.

Abstract: A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an etch chemistry based on chlorine or bromine performs a highly selective etch for silicon. During a second step, the etch chemistry is based on SiF4 and O2 which rather equally etches polysilicon and the collar isolation. On top of the wafer, the deposition of silicon oxide on the hard mask predominates and avoids an erosion of the hard mask. On the bottom of the trench the conformal etching of polysilicon and collar isolation predominates. The method provides an economic process flow and is suitable for small feature sizes.

Abstract: An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

Abstract: Noise of a low frequency band, generated inside a logic circuit, is remarkably reduced. A semiconductor integrated circuit device is provided with: a high voltage supply circuit generating, from a high voltage external power supply that is externally input, a high voltage internal power supply having a certain voltage level; and a low voltage supply circuit generating, from a low voltage external power supply that is externally input, a low voltage internal power supply having a certain voltage level. In inputting/outputting a signal between a logic circuit block and an I/O unit, a signal level is shifted through a level shifter unit. Since the logic circuit block is operated by the high voltage internal power supply and the low voltage internal power supply, the inductance in the semiconductor integrated circuit device is not subjected directly to DC fluctuation in consumed currents. Therefore, the characteristic impedance of power supply becomes equivalently smaller, thereby reducing low frequency noise.

Abstract: An amplifier circuit (R/A) conducts the first stage of ordering of whether to output data of four data bus pairs at the first half (first or second) or at the last half (third or fourth) based on the value of a signal EZORG1 reflecting the value of the least significant second bit of an externally applied column address. A switch circuit conducts the second stage of ordering to determine which is to be the first and the second of the two data output as the first half and to determine which is to be the third and the fourth of the two data output as the last half based on the value of a signal EZORG0 reflecting the value of the least significant bit in the externally applied column address.

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract: An embodiment of the invention is a CMOS transistor where the cap layer 9 of the sidewall spacer structure 7, 8, 9, 10, and 11 is comprised of a high dielectric constant material.

Abstract: The present invention relates to a complementary metal-oxide semiconductor (CMOS) image sensor. Particularly, the present invention provides effects of suppressing electrical and optical interferences and improving light sensitivity in a unit pixel of a highly integrated and low power consuming CMOS image sensor. In order to achieve these effects, a red pixel is two-dimensionally encompassed by a green pixel and a blue pixel formed with an additional p-type ion implantation region for suppressing the interference between the pixels. Also, in addition to the above-described structure, a photodiode optimized to the blue pixel is formed further to enhance the light sensitivity.

Abstract: A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The barrier implanted region is formed by conducting a plurality of deep implants at different energies and doping levels below the isolation region. The deep implants reduce surface leakage and dark current and increase the capacitance of the photodiode by acting as a reflective barrier to electrons generated by light in the doped region of the second conductivity type of the photodiode.

Abstract: Various embodiments of a magnetic memory element, including a storage layer and a reference layer, are disclosed. The storage layer includes two conjugate magnetic domain segments having opposing helicities. The reference layer is permanently magnetized. A nonmagnetic layer is interposed between the two magnetic layers. The boundaries of the two conjugate magnetic domain segments of the storage layer define domain walls along the radial direction thereof. The magnetic moment direction of one domain wall points inward and the magnetic moment direction of the other domain wall points outward. The two domain walls always attract each other, leaving one segment significantly larger than the other. These two different conditions (each longer the other) define two binary data states. By sending a vertical current through the magnetic memory element, transitions between the memory states can be achieved. Also disclosed are a memory cell, a memory device, and a computing device.

Abstract: A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Abstract: Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Abstract: A semiconductor device includes a MOS transistor, an interlayer insulating film, a contact plug, a capacitor lower electrode, a ferroelectric film and two capacitor upper electrodes. The MOS transistor is formed on a semiconductor substrate. The interlayer insulating film covers the MOS transistor. The contact plug is connected to an impurity diffusion layer of the MOS transistor. The capacitor lower electrode is formed on the contact plug. The two capacitor upper electrodes are formed on the capacitor lower electrode with the ferroelectric film interposed therebetween. A contact area between the contact plug and the capacitor lower electrode is greater than a contact area between each of the two capacitor upper electrodes and the ferroelectric film. At least a part of a gate electrode of the MOS transistor is located just below a region of the contact plug, which region is in contact with the capacitor lower electrode.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

Abstract: A semiconductor memory device comprises a first conductivity type semiconductor region, a second conductivity type source and drain regions provided in the semiconductor region, a gate insulating film structure provided on the semiconductor region between the source region and drain region and including a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films, a control gate electrode provided on the second insulating film, a gate sidewall provided on a side of the control gate electrode and having a thickness thinner than that of the second insulating film in the center of the control gate electrode, a third insulating film provided above the control gate electrode, and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film.

Abstract: A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized common-drain conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Abstract: The self-aligned floating-gate structure with a high coupling ratio being formed by one masking photoresist step is disclosed by the present invention, which comprises a first conductive layer over a tunneling-dielectric layer being formed over a semiconductor substrate in an active region and two extended second conductive layers being separately formed over etched-back field-oxide layers in nearby STI regions. Each of the extended second conductive layers is defined by a sidewall dielectric spacer being formed over each sidewall of the active region for forming a first-type self-aligned floating-gate structure and is formed by a sidewall conductive spacer being formed over each sidewall of the active region for forming a second-type self-aligned floating-gate structure, wherein thin sidewall conductive spacers are formed over sidewalls of the extended second conductive layers to alleviate the corner field-emission effects.

Abstract: A semiconductor device having a multi-layered spacer and a method of manufacturing the semiconductor device include gate electrodes each comprising a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor substrate, a gate polyoxide layer formed on sidewalls of the gate conductive layer and the gate oxide layer and being in contact with a predetermined portion of the semiconductor substrate, a silicon nitride layer being in contact with sidewalls of the capping dielectric layer and the gate polyoxide layer, an oxide layer being in contact with the silicon nitride layer, and an external spacer being in contact with the oxide layer.

Abstract: The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.

Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.

Abstract: A gate electrode <13> is provided to fill up a trench <300> while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode <13> located upward beyond a P-type base layer <4> and an N+-type emitter diffusion layer <51>, WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench <300> and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film <11> and the P-type base layer <4> and an end surface of the gate electrode <13> located upward beyond the trench <300> in a section of the trench <300>, relation of either WG≧1.3·WT or WC≧0.2 &mgr;m holds between these dimensions.

Abstract: A high voltage semiconductor device, including: a high concentration collector area of a first conductive type; a low concentration collector area of a first conductive type formed on the high concentration collector area; a base area of a second conductive type formed on the low concentration collector area and having a trench perforating the low concentration collector area in a vertical direction at the edge of the trench; a high concentration emitter area of a first conductive type formed on a predetermined upper surface of the base area; and an emitter electrode, a base electrode, and a collector electrode isolated from one another and connected to the emitter area, the base area, and the collector area, respectively. High breakdown voltage can be obtained with a narrow junction termination area due to the trench.

Abstract: A ferromagnetic semiconductor structure is provided. The structure includes a monocrystalline semiconductor substrate and a doped titanium oxide anatase layer overlying the semiconductor substrate.

Abstract: A highly-integrated, high speed semiconductor device includes a device isolation film defining an active region at a SOI wafer having a stacked structure of a first silicon layer, a filled insulating film and a second silicon layer—the second silicon layer being the active region between the device isolation film with an intervening first silicide layer; the first silicide layer formed on a gate electrode on the active region and an impurity junction region; and a second silicide layer intervening at the interface of a device isolation film and a second silicon layer and connected to the first silicide layer. Thus, operating characteristics of the device are improved by minimizing the resistance of an impurity junction region and reducing the manufacturing cost.