Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

Abstract: An aspect of the present invention includes a first MOSFET having a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate, a first channel region formed immediately below the first gate electrode in the first semiconductor layer, a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer, a first epitaxial layer formed on the first diffusion layer, and a first silicide layer formed on the first epitaxial layer, and a second MOSFET having a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate, a second channel region formed immediately below the second gate electrode in the second semiconductor layer, a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer, and a second silicide layer formed on the second diffusion layer.

Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a substrate. The seed layer is formed by removing hydrogen from the substrate, depositing a seed layer precursor and exposing the precursor to excited atoms to form a seed layer on the substrate. In addition to serving as a template for the growth of a high K dielectric layer, the seed layer retards the undesirable oxidation of the silicon surface thereby improving the performance of active devices that include the insulating layer.

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: A semiconductor device according to the invention includes: a semiconductor layer (10-15); a gate insulator (16) provided on the semiconductor layer; a gate electrode (17) provided on the gate insulator; a source region (20a) and a drain region (20b), which are of a first conductivity type and are provided in the semiconductor layer on both sides of the gate electrode in plan view; a cap layer (25), a channel region (24), and an under-channel region (23,22), which are of a second conductivity type and are provided in the semiconductor layer between the source region and the drain region in a descending order from an interface with the gate insulator; and a bias electrode member (Vbs) for applying a voltage to the under-channel region, wherein the channel region is formed of a first semiconductor, the cap layer and the under-channel region are formed of a second semiconductor and a third semiconductor, respectively, each of which has a larger band gap than the first semiconductor, the bias electrode member is

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen.

Abstract: A capacitance type dynamical quantity sensor includes a semiconductor substrate, a weight portion being displaced in accordance with a dynamical quantity, a movable electrode integrated with the weight portion, and a fixed electrode facing the movable electrode. The movable electrode and the fixed electrode provide a capacitor having a capacitance. The movable electrode is movable in accordance with the dynamical quantity. The capacitance of capacitor is changed in accordance with a displacement of the movable electrode so that the dynamical quantity as the capacitance change is measured with an outer circuit. The facing surface of the movable electrode facing the fixed electrode has a substantially rectangular shape, and an aspect ratio of the facing surface is in a range between 0.1 and 10.

Abstract: A radio frequency (RF) micro electro-mechanical system (MEMS) device and method of making same are provided, the device including an RF circuit substrate and an RF conducting path disposed on the RF circuit substrate, a piezoelectric thin film actuator, and a conducting path electrode. The piezoelectric thin film actuator has a proximal end that is fixed relative to the RF circuit substrate and a cantilever end that is spaced from the RF circuit substrate. The conducting path electrode is disposed on the cantilever end of the piezoelectric thin film actuator. The cantilever end of the piezoelectric thin film actuator is movable between a first position whereat the conducting path electrode is spaced from the RF path electrode and a second position whereat the conducting path electrode is spaced from the RF path electrode a second distance, wherein the second distance is less than the first distance. The RF MEMS device is particularly useful as a tunable capacitor.

Abstract: In a semiconductor photo-detector of the present invention, a first semiconductor layer, a second semiconductor layer having, and a photo-absorption part composed of a photo-absorption layer sandwiched between these layers are disposed on a substrate, at least the photo-absorption layer is formed at a position apart inwardly by a finite length from an end surface of the substrate, an end surface of the second semiconductor layer and the substrate or the end surface of the substrate is provided with a light incident facet angled inwardly as it separates from the surface of the second semiconductor or the surface of the substrate.

Abstract: To provide a photo-interrupter which can anchor a light-emitting device and a light-receiving device to a concave case in an expensive configuration.

Abstract: A rectifier device, based on a novel operation principle completely different from that of conventional molecular electronic devices, is made by coupling two or more molecules or molecule arrays (11) at certain joints. By making use of the phenomenon that transfer of an excited state or exciton from one molecule or molecule array to another molecule or molecule array coupled thereto progresses asymmetrically due to spatial asymmetry at the joint, a rectifying function related to the transfer of the excited state of exciton is obtained. Additionally, by controlling the rectification property in addition to the rectification function, an ion sensor device or a switching device is made. A resistor device may be inserted in the rectifier device.

Abstract: A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.

Abstract: A semiconductor integrated circuit device includes a circuit block with a plurality of components. At least one of the components is supplied with a voltage having a value different from that supplied to the other components. This allows reduction in power consumption in the semiconductor integrated circuit device.

Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Abstract: A low substrate loss inductor has a substrate, a plurality of p type doping areas and a plurality of n type doping areas formed alternatively inside the substrate, an insulating layer formed on the substrate, and a metal coil formed on the insulation layer. The insulation layer isolates the metal coil from the p type doping areas and n type doping areas. The doping areas are arranged orthogonal to the metal coil.

Abstract: In a bipolar transistor including a base layer made of SiGe, a non-did SiGe layer and a non-doped Si layer are provided between the base layer and an emitter layer. The composition ratio of Ge in the emitter side of SiGe base layer is decreased with increasing proximity to the emitter side, and the composition ratio of Ge in the non-doped SiGe layer is a smaller than the composition ratio of Ge at the emitter layer-side end of the SiGe base layer. In this manner, restriction is put on the diffusion of boron from the base layer to the emitter side, and the base-emitter junction capacitance CBE reduced. Furthermore, the direct-current gain &bgr; can be improved by increasing the composition of Ge at the emitter end of the SiGe base layer to more than or equal to a predetermined value.

Abstract: An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is made of highly doped well terminal regions having a deep depth, for example formed as collector deep implantation regions. This reduces the series resistance of the tunable capacitance. The integrated, tunable capacitance can be used for example in integrated voltage-controlled oscillator circuits in which a high quality factor is demanded.

Abstract: An image sensor module (S) includes a substrate (4) having a projecting portion (41) projecting sideways from a frame (3). The projecting portion (41) has an end (4b) provided with a plurality of terminals (81) electrically connected to an image sensor chip (5). The image sensor module (X) can be easily connected to another apparatus by inserting the end (4b) of the projecting portion (41) into a socket type connector.

Abstract: A leadframe packaging apparatus including a die, at least two separated die pads each connected to a corresponding voltage level thereof, a plurality of leadfingers, and at least one passive component having two ends each connected to one of the two separated die pads. A packaging method for the leadframe apparatus is further provided, wherein the method prepares at least one die pad disposed in separated fashion, integrated circuit dies adhered to separated die pads, and passive components having two ends connected with separated die pads before forming the molding compound, thereby placing the passive components within the molding compound.

Abstract: A leadframe to be used in a semiconductor device comprises a plurality of parallel first leads and a plurality of parallel second leads. The pitch of the first leads is different from that of the second leads, and the first leads are joined end-to-end with the second leads. To obtain a leadframe for DIP packages, the first leads are encapsulated in a package and the second leads are allowed to project from the package. To obtain a leadframe for SOP packages, the first leads and the second leads are allowed to project from a package and the second leads are cut off later.

Abstract: A multi-chip circuit component comprising first and second substrate members, each of which are formed of an electrically-nonconductive material. Each substrate member has oppositely-disposed first and second surfaces, with an outer layer of thermally-conductive material on the first surface thereof and electrically-conductive areas on the second surface thereof. At least two circuit devices are present between the first and second substrate members, with each circuit device having a first surface electrically contacting at least one of the electrically-conductive areas of the first substrate member, and each circuit device having a second surface electrically contacting a corresponding one of the electrically-conductive areas of the second substrate member. First lead members are electrically coupled to the electrically-conductive areas of the first substrate member, and second lead members are electrically coupled to the electrically-conductive areas of the second substrate member.

Abstract: A leadframe includes: a frame rail; a die pad, disposed inside the frame rail, for mounting a semiconductor chip thereon; and a plurality of internal inner leads, which are disposed to surround the die pad and each of which has a convex portion on the bottom thereof. The frame rail and the internal inner leads are retained by a lead retaining member on their upper and/or lower surface(s).

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.

Abstract: A semiconductor package mainly comprises a substrate unit and a chip. The chip is electrically connected to the substrate unit. The substrate unit includes an upper surface, a lower surface and a side surface. A plurality of circuit traces are formed on the upper surface and a plurality of contacts are formed on the side surface, wherein the contacts are electrically connected to the circuit traces. Besides, a plurality of solder balls are formed on the contacts in order to transmit the signals from chip to outside through the substrate unit, the contacts and the solder balls. Furthermore, a semiconductor package module will be formed by electrically connecting the semiconductor packages with each other through solder balls and a module substrate, and mounting the semiconductor packages with each other through an adhesive layer. In addition, a method for manufacturing the semiconductor package is disclosed.

Abstract: A semiconductor package includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.

Abstract: Disclosed are a ceramic multilayer substrate formed by vertically stacking and firing a plurality of ceramic substrates, in which a connection bar is longitudinally formed on connection areas between internal patterns and an external terminal of each ceramic substrate, thereby preventing metallic conductive layers of the internal patterns from being deformed during processing the external terminal and stably connecting the internal patterns to the external terminal, and a method for manufacturing the substrate.

Abstract: A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Abstract: In one embodiment, the present invention includes an apparatus having a metal layer with a pad disposed above a substrate; and a cap disposed above the metal layer having a first portion to provide for contact with a probe and a second portion to provide a bonding surface, and the cap is electrically coupled to the pad.

Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: A method for forming a metal wiring layer of a semiconductor device, where a first layer having a recess region is formed on a semiconductor substrate. A second layer is formed on inner walls of the recess region and on an upper portion of the first layer. A third layer is formed on the second layer so as to have a smaller third layer thickness on the inner walls of the recess region than on the upper portion of the first layer. A fourth layer is then formed on the-third layer, providing a metal wiring layer with improved step coverage.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: An interlayer dielectric multilayer film is formed by providing a boron nitride film as a protective film 34 between interlayer dielectric films 33 with a low relative dielectric constant which comprise organic coated films or porous films. The interlayer dielectric films 34 having a low relative dielectric constant are combined with the boron nitride film excellent in mechanical and chemical resistance, high in thermal conductivity and having a low relative dielectric constant, thereby achieving a low relative dielectric constant, while maintaining adhesion and moisture absorption resistance.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of connecting pads on one surface, an insulating film formed on one surface of the semiconductor substrate. The insulating film has holes each corresponding to one of the connecting pads, and a recess having a bottom surface depressed from the upper surface in the direction of thickness. Interconnections are formed on an upper surface of the insulating film or on the bottom surface of the recess, and connected to the connecting pads through the holes in the insulating film.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: In the multichip module and shutdown method thereof, there are provided a semiconductor chip for voltage regulation which shuts itself down at a first setup temperature and a semiconductor chip for amplifier which is disposed in a common package together with the semiconductor chip for voltage regulation and shuts itself down at a second setup temperature. The semiconductor chip for voltage regulation is provided with means for outputting via a bus a signal for compulsorily shutting down the semiconductor chip for amplifier when the semiconductor chip for voltage regulation reaches a third setup temperature lower than the first setup temperature.

Abstract: An object of the present invention is to provide a semiconductor device capable of adapting to an increase in the external terminals which can be arranged on the mount surface (a greater number of pins). A mesa-type semiconductor chip is mounted on a mount surface of a substrate which is a semiconductor chip carrying portion such that the side wall surface of the four side walls of the first semiconductor chip intersects the mount surface at an acute angle &thgr; (0°<&thgr;<90°). Further, a first pad formed on a main surface of the first semiconductor chip is electrically connected to a solder ball provided on an unmounted surface, via a first wiring layer, one end of which is connected to the first pad, and which extends along the main surface, the side wall surface, and the unmounted surface of the semiconductor chip.

Abstract: A wiring terminal is formed on a wiring substrate, and an electrode is formed on a semiconductor device. The width of the wiring terminal is smaller than the width of the electrode. When the semiconductor device is mounted on the wiring substrate, the wiring terminal becomes embedded in the electrode due to applied pressure.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: Eductor apparatus is provided for introducing gas bubbles into a contaminated liquid in a gas flotation cell, the apparatus comprising a clean liquid inlet port, the inlet port having an outlet end (104) through which the clean liquid is ejected in a first direction, a gas inlet chamber adjacent to the outlet end of the inlet port for introducing gas to the liquid from a gas inlet port, the gas inlet chamber substantially surrounding the flow of liquid when the apparatus is in use, and a gas/liquid mixing and diffusing section wherein gas is entrained within the liquid prior to being ejected from the eductor apparatus into the contaminated liquid, the gas/liquid mixing and diffusing section having a direction of fluid flow substantially transverse to the first direction such that the fluid exits from the gas/liquid mixing and diffusing section substantially radially outwardly relative to the first direction.

Abstract: An apparatus is provided for the gasification or aeration of liquids. Elongated aeration elements are connected to a distribution conduit and have an essentially rigid support tube about which is disposed a membrane of elastomeric material. Compressed gas introduced between the support tube and membrane escapes via slits in the membrane. An elastically deformable fitting is disposed between the distribution conduit and one of the aeration elements, and is disposed in a bore in the conduit. The fitting has an essentially flat portion, one side of which rests against the outer surface of the conduit, and the other side of which rests against an end of the aeration element. A hollow bolt is securely connected to the aeration element and is guided through a bore in the fitting into the interior of the conduit, where it is provided with apertures.

Abstract: A security article includes a light transmissive substrate having a first surface and an opposing second surface, with the first surface having an embossed region with an optical diffraction pattern or a holographic image pattern. A color shifting optical coating is formed on the substrate such as on the opposing second surface, with the optical coating providing an observable color shift as the angle of incident light or viewing angle changes. The security article can be used in a variety of applications and products to provide for enhanced security measures such as anticounterfeiting.

Abstract: Calibrating near infra red (NIR) spectroscopic instrumentation for quantitative measurement of resin-loading of prepared wood materials, as moving in an assembly-forming line, for subsequent pressing under heat and pressure for manufacture of engineered-composite wood product. Feedback of measured data of resin-loading, during in-line assembly operations, enables maintaining consistent resin-loading and optimizes resin usage. Calibration of NIR spectroscopic instrumentation can be carried out on equipment simulating in-line movement of pre-established reference-source test-samples; or, can be carried out during on-line movement of wood-material test samples. The developed calibration method removes absorptive effects at wavelengths for constituents other than resin, such as the moisture content of the wood-materials and of the resin, while maintaining accurate and prompt NIR spectroscopic measurements of resin-loading in a continuous assembly line.

Abstract: A method is provided for producing dimensionally stable rotationally molded parts from semi-crystalline materials. A test mold is constructed having dimensions closely approximating the desired dimensions of the final part. A test part is then molded in the test mold using conventional rotational molding techniques. After the test part has partially cooled, it is removed from the mold, allowed to cool to ambient temperature, measured and annealed in an oven. During annealing, the part is heated to the crystallization temperature, midway between the glass transition temperature and the crystalline melting temperature. After annealing, the part is allowed to cool to ambient temperature and measured again. The post annealing dimensions are then compared with the dimensions determined before annealing to determine the amount of shrinkage. A production mold is then constructed to take into account the amount of shrinkage calculated.