Abstract: A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

Abstract: The intensity of the light emitted from the light-emitting diode on wafer is measured and then the potential difference between the terminals of the light-emitting element, and the plasma current flowing thereinto are derived from measured light intensity. Since the use of a camera enables non-contact measurement of emitted light intensity, the lead-in terminals for lead wires that are always required in conventional probing methods become unnecessary. In addition, since the target wafer does not require lead wire connection, wafers can be changed in the same way as performed for etching.

Abstract: A preferred embodiment includes a method for monitoring the performance of a filter positioned in an airstream in a semiconductor processing system. The method includes sampling the airstream at a location upstream of the filter to detect the molecular contaminants present in the airstream; identifying a target species of the contaminants upstream; selecting a non-polluting species of a contaminant having a concentration greater than a concentration of the target species; measuring the non-polluting species in the airstream at a plurality of locations; and determining the performance of the filter with respect to the target species from measurements of the non-polluting species. The plurality of locations includes a location downstream of the filter and at a location within the filter. Further, the method for monitoring includes generating a numerical representation of a chromatogram of the airstream sampled at a location upstream of the filter.

Abstract: A method to detect metal contamination on a semiconductor topography is provided. The semiconductor topography may include a semiconductor substrate or a dielectric material disposed upon a semiconductor substrate. The metal contamination may be driven into the semiconductor substrate by an annealing process. Alternatively, the annealing process may drive the metal contamination into the dielectric material. Subsequent to the annealing process, a charge may be deposited upon an upper surface of the semiconductor topography. An electrical property of the semiconductor topography may be measured. A characteristic of at least one type of metal contamination may be determined as a function of the electrical property of the semiconductor topography. The method may be used to determine a characteristic of one or more types of metal contamination on a portion of the semiconductor topography or the entire semiconductor topography.

Abstract: A semiconductor fabricating method is disclosed. A first container accommodating a predetermined number of semiconductor wafers and labeled with a first identifier and a second container labeled with a second identifier are mounted on a first processing apparatus, and the first and second identifiers are stored. While the first processing apparatus is submitting the semiconductor wafers to a first process, designated ones of the processed wafers are loaded into the second container as sample wafers. The second container is mounted on an inspection apparatus to inspect the sample wafers. Then, the first and second containers are mounted on a second processing apparatus and are identified by comparison of identifiers thereof with the stored first and second identifiers, respectively. The second processing apparatus submits the rest of the processed semiconductor wafers and the inspected sample wafers to a second process, and the processed sample wafers are returned to the first container.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.

Abstract: A nondestructive inspection device (or method) is basically configured such that a laser beam (1300 nm) is irradiated on a surface (or back) of a semiconductor device chip to scan. Due to irradiation of the laser beam, a defect position is heated to cause a thermoelectromotive current, which induces a magnetic field. A magnetic field detector such as SQUID detects a strength of the magnetic field, based on which a scan magnetic field image is produced. A display device superimposes the scan magnetic field image on a scan laser microphotograph on a screen, so it is possible to perform defect inspection on the semiconductor device chip. Incidentally, a semiconductor device wafer is constructed to include a thermoelectromotive force generator and its wires, which are electrically connected to first-layer wires. By irradiation of the laser beam on the thermoelectromotive force generator, it is possible to detect a short-circuit defect, which lies between the first-layer wires.

Abstract: A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer.

Abstract: A thin film made of an amorphous material having supercooled liquid phase region is formed on a substrate. Then, the thin film is heated to a temperature within the supercooled liquid phase region and is deformed by its weight, mechanical external force, electrostatic external force or the like, thereby to form a thin film-structure. Thereafter, the thin film-structure is cooled down to room temperature, which results in the prevention of the thin film's deformation.

Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.

Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such the protected and unprotected regions are defined. The unprotected regions are oxidized to form isolated magnetic regions.

Abstract: The present invention provides a fabrication method of a pressure type fingerprint sensor, which uses the commercial integrated circuit process to form the sensor and the processing circuit together on the same chip. The present invention comprises a plurality of capacitive pressure sensors arranged in a 2-D array and applies the charge sharing principle to each capacitive pressure sensor for signal reading. The main structure of each pressure sensor is a pair of plate electrodes with an air gap between them to form a plate sensor capacitor, wherein the plate electrodes comprise a floating electrode and a fixed electrode. When the finger ridge contacts the floating electrode, the pressure from the finger changes the spacing of the air gap so as to change the capacitance of the plate sensor capacitor. The 2-D sensor array can read the 2-D pressure distribution pressed by the finger ridge to construct the fingerprint pattern.

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract: A method of forming an image sensor package includes wire bonding bond pads of an image sensor to interior traces on a substrate with bond wires. A first optically curable material is applied to enclose the bond wires. A second optically curable material is applied between a lid and the substrate. The first and second optically curable materials are cured through the lid with ultraviolet radiation. The first and second optically curable materials are cured rapidly without heating thus minimizing the fabrication cost of the image sensor package.

Abstract: A method of programming a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, and a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region.

Abstract: An object of the present invention is to make it possible to effect a reliable and compact configuration for a semiconductor device when mounting a plurality of semiconductor elements in a single package, and achieve higher integration and higher functionality more effectively. In a multi-layer wiring board 20 in which wiring patterns (conductor layers) 22, 24, and 26, and insulating layers 23, 25, and 27, are formed alternately in multiple layers on a base substrate, and electrically connections are made between the wiring patterns through via holes VH1 and VH2, semiconductor elements 30 are imbedded and mounted inside the insulating layers 23, 25, and 27, and the semiconductor elements 30 are deployed so that they are electrically connected to wiring patterns that are covered by the insulating layers, and so that they are stacked up in a direction perpendicular to the planar dimension of the multi-layer wiring board 20.

Abstract: In a method for fabricating a Si—Al alloy packaging material, by adding Al—Si alloy powders to Si powders and pressurizing-forming it, or by pressurizing-filling Si powders or a preforming body of Si powders with Al—Si alloy melt, a Si—Al alloy packaging material having good characteristics can be obtained.

Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Abstract: A flip chip type semiconductor device is provided with a semiconductor chip with a plurality of pad electrodes on one surface. A solder electrode is connected to each pad electrode and a metallic post is connected to each solder electrode. The surface of the semiconductor chip on a side on which the pad electrodes are provided is coated with an insulating resin layer and whole the pad electrode and solder electrode and part of the metallic post are buried in the insulating resin layer. The remaining portion of the metallic post is projected from the insulating resin layer to form a protrusion. Then, an outer solder electrode is formed so as to cover this protrusion. The outer solder electrodes are arranged in a matrix on the insulating resin layer. The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode and the surface of the insulating resin layer.

Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is smaller in thickness than the tape base material 1a, and then sealing is performed by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a is set to correspond to a stress neutral plane of the TCP as a whole.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A method of picking up a plurality of semiconductor chips formed by dividing a semiconductor wafer comprises the step of adhesively holding the plurality of semiconductor chips on an elastic adhesive pad which has innumerable pores in the surface and generates adhesion force when negative pressure is produced by the pores crushed by restoration force generated by elasticity and adhesion, and the step of picking up the semiconductor chips in a state of air in the pores being expanded by heating the elastic adhesive pad which adhesively holds the plurality of semiconductor chips at a predetermined temperature.

Abstract: A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line.

Abstract: A new method is provided of treating the wafer prior to the process of singulating the wafer into individual die. A surface of the wafer over which CMOS image sensor devices have been created is coated with a layer of material that is non-soluble in water. The wafer is singulated by sawing through the layer of material that has been coated over the surface of the wafer and by then sawing through the wafer. The singulated die is then further processed by applying steps of die mount, wire bonding, surrounding the die in a mold compound and marking the package.

Abstract: An array of crystalline silicon dies on a substrate and a method for yielding the array are provided. The method comprises: delineating an array of die areas on a crystalline semiconductor wafer; implanting the die areas with hydrogen ions; overlying the die areas with a layer of polymer to form, for each die, an aggregate including a die area first wafer layer; polymerically bonding an optically clear carrier to the die areas; thermally annealing the wafer to induce breakage in the wafer; forming, for each die, an aggregate wafer second layer with a thickness less than the die thickness; and, for each die, conformably attaching the aggregate wafer second layer to a substrate. The substrate can have an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than and equal to approximately 20 nanometers.

Abstract: A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on the circuit board. The mounting plate of the heat sink is provided with a plurality of openings through which the solder of the solder pad flows during the solder reflow process so that the mounting plate is securely adhered between the power transistor and the circuit board. The mounting plate of the heat sink is connected thermally to an extension member which extends generally perpendicular to the mounting plate, the extension member in turn being connected to a heat dissipation surface which may be one or several fins.

Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.

Abstract: The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers.

Abstract: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method of fabricating a thin film transistor, includes the steps of (a) forming a gate electrode on an electrically insulating substrate, (b) forming a gate insulating film on the electrically insulating substrate, covering the gate electrode therewith, (c) forming a semiconductor layer on the gate insulating film above the gate electrode, (d) forming source and drain electrodes both making electrical contact with the semiconductor layer, (e) patterning the semiconductor layer into a channel, (f) applying first plasma to the semiconductor layer through the use of a first gas, and (g) applying second plasma to the semiconductor layer through the use of a second gas, and (h) forming an electrically insulating film covering the semiconductor layer therewith.

Abstract: A method for polysilicon crystallization by simultaneous laser and rapid thermal annealing is disclosed. In the method, a substrate that has an amorphous silicon layer on top is first provided and positioned on a conveyor situated inside a temperature-controlled chamber. The temperature-controlled chamber is equipped with a window in a top wall that is substantially transparent to thermal and laser energy. A beam of thermal energy and simultaneously a beam of laser energy merged with the thermal energy is then directed through the window onto a top surface of the substrate to convert an amorphous silicon film into a polysilicon film.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A method of fabricating a gate structure of a field effect transistor, comprising forming a hard mask, etching a gate electrode, and contemporaneously forming a gate dielectric and removing the hard mask.

Abstract: A semiconductor device is provided that comprises a gate oxide film, a gate electrode, a nitride film, a low concentration impurity area, and a high concentration impurity are. The gate oxide film is formed on a semiconductor substrate. The gate electrode is formed on a predetermined region of the gate oxide film, and an upper portion thereof is wider than a lower portion thereof by a predetermined width. The nitride film is formed at a side of the lower portion of the gate electrode, and a width of the nitride film is equal to the predetermined width. The low concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode. The high concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode.

Abstract: An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

Abstract: A method for forming a semiconductor device, which features omitting a separated procedure for forming a barrier layer by molding a bottom electrode of a capacitor with TiN compounds. The method for forming a bottom electrode of a capacitor with little roughness on the surface by skipping the etching step for patterning on a metallic layer includes: molding a storage node hole to expose the plug by forming a sacrificial layer on the semiconductor substrate where transistors and plugs are formed and etching the sacrificial layer optionally; and by embedding TiN in the storage node hole and separating the neighboring bottom electrodes in the chemical-mechanical polishing method or etch back.

Abstract: Disclosed is a method of forming a capacitor in a semiconductor device.

Abstract: A method of determining the active region width (10) of an active region (4) by measuring the respective gate currents (Ig,100, Ig,100′, Ig,100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element (16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective gate currents (Ig,100, Ig,100 ′, Ig,100″) as a quasi-linear function (IW) of the respective predetermined widths (Wi), extrapolating a calibration term (WI=0) from the quasi-linear function (IW), and subtracting the calibration term (WIg=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

Abstract: The present invention relates to a method of manufacturing a flash memory cell. The method includes forming a stack gate in which a floating gate and a control gate are stacked at a given region of a semiconductor substrate, and performing a rapid thermal nitrification process to form a nitride film at the side of the stack gate and over the semiconductor substrate. Therefore, the present invention can improve a retention characteristic and can prevent movement of threshold voltage control ions.

Abstract: The invention provides a low temperature process for depositing silicon nitride or silicon dioxide dielectric films over magnetically active materials in the manufacture of MRAM devices and MRAM devices produced by the method.

Abstract: A method of forming an array of FLASH field effect transistors and circuitry peripheral to such array includes forming a sacrificial oxide over an array area and a periphery area of a semiconductor substrate. After forming the sacrificial oxide, at least one conductivity modifying implant is conducted into semiconductive material of the substrate within the array without conducting the one conductivity modifying implant into semiconductive material of the substrate within the periphery. The sacrificial oxide is removed from the array while the sacrificial oxide is left over the periphery. After removing the sacrificial oxide from the array, at least some FLASH transistor gates are formed within the array and at least some non-FLASH transistor gates are formed within the periphery.

Abstract: The present invention relates to a method of manufacturing a flash memory device. In the method, a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device. As the process for forming the LDD structure for the low voltage is omitted, the cost is reduced in the entire process of manufacturing the flash memory device.

Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.

Abstract: A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.