Abstract: A system and method for enabling flash memory systems to support flash devices with pages that are larger than operating system data sector sizes, while not violating the device's specifications, and also optimizing performance. According to the present invention, the writing logic of a flash memory system must take into account the PPP limitations and page size of the device during sector write operations. The PPP influences the decision when to simply write the new data, and when to allocate a new page and copy previously existing data to the new page. According to the present invention, when a page contains more than one sector, the software makes the standard translation into physical address, but after finding the address, it examines the page containing that address, and counts the number of other sectors within the same page already containing data.

Abstract: A low power semiconductor memory device having a normal mode and a partial array self refresh mode. The device includes a plurality of banks including a memory cell array; a memory control unit for generating a pre-bank selection signal related to the bank selection; a bank selection signal generating unit for generating a bank selection signal practically selecting a bank by using the pre-bank selection signal in the normal mode and for generating a bank selection signal according to refresh properties of the bank without using the pre-bank selection signal in the partial array self refresh mode.

Abstract: Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy.

Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. This random distribution of multiple copies of segments of data improves both scalability and reliability. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all of the storage units.

Abstract: A non-uniform memory access (NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memory, and the home node contains at least a home system memory. To reduce access latency for data from other nodes, a portion of the remote system memory is allocated as a remote memory cache containing data corresponding to data resident in the home system memory. In one embodiment, access bandwidth to the remote memory cache is increased by distributing the remote memory cache across multiple system memories in the remote node.

Abstract: The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.

Abstract: In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a “set gate control flag” command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor.

Abstract: A system and method are provided for sharing and caching information in a data processing system and for efficiently managing a cacheable state shared among processes and clones. In one aspect, a method for managing a plurality of caches distributed in a network comprises maintaining, by each cache, a plurality of statistics associated with a cacheable object, wherein the statistics associated with the cacheable object comprise an access frequency (A(o)), an update frequency (U(o)); an update cost (C(o)), and a cost to fetch the cacheable object from remote source (F(o)); computing, by each cache, a metric using said statistics, wherein the metric quantitatively assesses the desirability of caching the cacheable object; and utilizing the metric, by each cache, to make caching decisions associated with the cacheable object.

Abstract: Devices, softwares and methods update preemptively entries in a cache memory that are expiring. Updating takes place at scheduled refresh times. Refresh times are computed from usage history data and change history data that is maintained and tracked for each entry. This way a frequently made inquiry will be fulfilled with an entry that has been refreshed preemptively in advance, even after its original expiration time.

Abstract: Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache memory. The invention provides for circuits and methods for monitoring normal system accesses to system memory to manipulate CRC values in system memory in conjunction with associated access to disk drive of a storage subsystem. When accesses are detected loading or retrieving CRC values from system memory, the CRC values are loaded substantially in parallel into the CRC value cache memory.

Abstract: A caching mechanism for a virtual persistent heap is described. A feature of a virtual persistent heap is the method used to cache portions of the virtual persistent heap into the physical heap. The caching mechanism may be effective with small consumer and appliance devices that typically have a small amount of memory and that may be using flash devices as persistent storage. In the caching mechanism, the virtual persistent heap may be divided into cache lines. A cache line is the smallest amount of virtual persistent heap space that can be loaded or flushed at one time. Caching in and caching out operations are used to load cache lines into the heap or to flush dirty cache lines into the store. Different cache line sizes may be used for different regions of the heap. Translation between a virtual persistent heap address and the heap may be simplified by the caching mechanism. All references may be kept in one address space, the virtual persistent heap address space.

Abstract: A prefetch engine is responsible for prefetching critical data. The prefetch engine operates when a cache miss occurs accessing critical data requested by a processor. The prefetch engine requests cache lines surrounding the cache line satisfying the data request be loaded into the cache.

Abstract: A computer system includes a processing unit, a system memory, and a memory controller coupled to the processing unit and the system memory. According to the present invention, the memory controller accesses the system memory to obtain prefetch data and transmits the prefetch data to the processing unit in a prefetch write operation specifying the processing unit in a destination field. In one embodiment, the memory controller transmits the prefetch write operation in response to receipt of a prefetch hint from the processing unit, which may accompany a read-type request by the processing unit. This prefetch methodology may advantageously be implemented imprecisely, with the memory controller responding to the prefetch hint only if a prefetch queue is available and ignoring the prefetch hint otherwise. The processing unit may similarly ignore the prefetch write operation if no snoop queue is available.

Abstract: As microprocessor speeds increase, performance is more affected by data access operations. A combined solution of hardware and software directed pre-fetching limits additional instructions in a program stream, and minimizes additional hardware resources. In the current invention, the hardware and software directed pre-fetching technique is performed without explicit pre-fetch instructions utilized within the program stream and occupies a minimal amount of additional chip area. To minimize instruction bandwidth of the processor, the software and hardware directed pre-fetching approach uses additional registers located at an architectural level of the processor to specify pre-fetch regions, and a respective stride used for each of the regions. The impact to the instruction bandwidth of processing of instructions by the processor is limited to those additional instructions contained within the application that are required to set these registers.

Abstract: A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.

Abstract: A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner.

Abstract: A memory engine combines associative memory and random-access memory for enabling fast string search, insertion, and deletion operations to be performed on data and includes a memory device for temporarily storing the data as a string of data characters. A controller is utilized for selectively outputting one of a plurality of commands to the memory device and receives data feedback therefrom, the memory device inspects data characters in the string in accordance with the commands outputted by the controller. A clock device is also utilized for outputting a clock signal comprised of a predetermined number of clock cycles per second to the memory device and the controller, the memory device inspecting and selectively manipulating one of the data characters within one of the clock cycles.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: A system for efficiently representing or “mapping” data so that it can be rapidly communicated to a back-up storage system from a primary processor or a shared storage device while at the same time allowing a backup system to backup files rather than devices is described.

Abstract: A synchronization confirmation method required for operation of a database is provided to a host device connected to a disk device which provides remote asynchronous data transfer. Immediately after commit of write data, an application of the host device issues a sync command which requires synchronization confirmation. A disk control device notifies the host device of a number concerning latest data received from the host device of a local side and a number concerning latest data received by a remote side. When the two numbers have coincided with each other, the host device judges the commit operation to have been completed.

Abstract: A method and software for managing memory are provided in which objects residing in session memory are formatted so the references contained in the objects are in a machine-independent format, namely, that the references are encoded numerically. An exit table is provided to handle references with session memory that refer to locations in call memory, in which each entry in the exit table is associated with a corresponding reference in session memory and contains a pointer to the location in call memory.

Abstract: A method for managing a memory of a computer system to store a data of a first size, comprising the steps of defining chunks of the memory, wherein each chunk is a continuous memory space of a predetermined size. Defining chunk pools for managing the chunks, wherein each chunk pool corresponds to chunks of a particular size and defining unit pools for managing units of the first size, wherein the chunk pool corresponding to the unit pool provides a chunk of the particular size to be separated into the units of the first size, and the data of the first size is stored in the units.

Abstract: A method for augmenting the memory capabilities of an option ROM in which PCI function calls are used to access a larger sized non-volatile memory. Thirty two bit addressing is used in the PCI function call routines to allow for 4 GB addressing. An option ROM and the separate larger sized non-volatile memory or a single non-volatile memory may be used for storing the overflow images.

Abstract: Method and apparatus are disclosed for identifying logical volumes stored among a plurality of storage elements in a computer storage system. A unique logical volume identifier may be assigned to the logical volumes and used to access identifying information about the logical volumes.

Abstract: A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region.

Abstract: In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+M<B, a second corrected target module address when I+M>=B+L and an uncorrected module address when B<=I+M<B+L.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract: A method and an architecture for recovery from a branch misprediction in a processor. The method may include the steps of (A) evaluating a branch prediction for a branch instruction, (B) pausing an instruction cache line fetch in response to the branch instruction, and (C) resuming the instruction cache line fetch from where paused in response to evaluating the branch prediction as incorrect to recover from the branch misprediction.

Abstract: An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.

Abstract: An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Abstract: A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters.

Abstract: A method and system for operating an input/output circuit for driving peripheral devices controlled by an embedded system. For increasing the overall system availability the invention proposes to add some limited, repeatedly-performed status storing functionality preferably into a register storage of the I/O devices. The stored information can be easily exploited (i.e., read out from external of the input/output devices) via the controller of the embedded system.

Abstract: A file editing system that provides a high file content secrecy, a file version management, and an asynchronous editing is disclosed. For a high file content secrecy, the block data of files managed by a file management server device are enciphered in units of blocks, and a client device obtains the block data of the desired file in enciphered state, deciphers the obtained block data in units of blocks, carries out an editing of the desired file to obtain editing data, enciphers the editing data in units of blocks, and transmits the enciphered editing data to the file management server device.

Abstract: A transaction processing system employs an authentication device which receives identifying and authentication information from a token such as a credit or debit card. The authentication device forms an information block comprising the identifying and authentication information and encrypts the information block using a preprogrammed key. The information block is transferred to a transaction terminal such as a merchant terminal or customer computer and subsequently transferred to an authorizing server. The authorizing server transfers the information block to an authenticating server, which decrypts the information block, extracts the identifying and authentication information and compares the identifying and authentication information against similar information accessible to the authenticating server. The authenticating server instructs the authorizing server to accept or reject the transaction based on the result of the comparison.

Abstract: Disclosed is an apparatus and method to build programs from activity function units (AFUs) within a graphical environment. Each AFU is made from graphical representations of functional units (FUs). The resulting AFUs can be locked so that users cannot view proprietary and trade secret information as to how they accomplish their tasks. AFUs can be combined with other FUs and previously-created code represented in FU form to build large complex programs which are modified and added to by the user by means of manipulation of graphical elements on the computer screen without disclosing underlying coding.

Abstract: Methods, systems, and devices are provided for securely updating private keys, key pairs, passwords, and other confidential information in a distributed environment. A transaction is created including appropriate encrypted soft-token content, and then transmitted to a new ocation. Comparisons are made to determine whether the new soft-token content should be recognized as authentic and entered at the new location. Updates are accomplished without ever sending the plain text form of a key or a password across the wire between the distributed locations.

Abstract: A system and method which allows the secure interchange of information a web browser based user system and an On-Line Transaction Processing (OLTP) enterprise server. In addition to the standards based security provided by the browser for individual data transfers, a facility enables a user to log-on to an entire transactional session. This facility provides for validation of user-id and user password.

Abstract: A system, method and computer program product are provided for analyzing a network. Initially, network traffic information relating to network traffic is collected. Next, the network traffic information is encrypted. In use, the network traffic information is capable of being analyzed by a network analyzer adapted for decrypting the network traffic information.

Abstract: A data processor, which is capable of preventing from causing a harmful influence due to an operation of the other loads, even when the data processor is powered by a battery, which is commonly used by the other loads. A vehicle-mounted personal computer as the data processor is powered by a vehicle-mounted battery via a main power supply circuit. When a key switch is turned on, a start-up circuit in the main power supply circuit outputs a start-up signal after a predetermined time has passed, so that output voltage from the vehicle-mounted battery is stable. After that, the main power supply circuit supplies power to the personal computer. As a result, the personal computer starts up by using a stable voltage. When the key switch is turned off, the personal computer moves to a sleep mode. When the key switch is turned on again, the personal computer returns to a previous condition by performing a resume process.

Abstract: To identify interference from other data carrying subscriber loops (i.e., from loop disturbers), a power spectral density sample may be obtained from the subscriber loop under consideration based on at least one measurement while the loop is not transmitting data. The sample power spectral density may then be correlated with each one of a set of known power spectral densities. Each known power spectral density represents a power spectral density in a loop which is not transmitting data in the presence of one of (i) no subscriber loop disturbers, (ii) a particular subscriber loop disturber, and (iii) particular subscriber loop disturbers. Based on the correlations, subscriber loop disturbers may be recognized.

Abstract: A coupling piece for carrying out digital transmissions between an electrical interface of a first device and an electrical interface of a second device. The devices each use different voltage levels for distinguishing between the two logical states “high” and “low”. An internal circuit is provided for converting the voltage levels of the first device to the voltage levels of the second device, which correspond to the state. The higher voltage level is conveyed to this internal circuit by one of the two devices so that the low level can be converted to the higher level. The internal circuit carries out the conversions using a switching process.

Abstract: A telecommunications device includes an event initiation bus, at least one card coupled to the bus that can execute an event, and at least one controller also coupled to the bus that can communicate an event code value to the card using the bus. The event code value indicates the event is to be executed. The controller determines an event code value from the bus, compares the communicated event code value with the determined event code value, and transmits an event strobe signal to the card using the bus if the communicated event code value matches the determined event code value. The event strobe signal enables execution of the event and the card executes the event in response to the event code value and the event strobe signal. In a particular embodiment, the device is a switching unit having a high availability backplane environment.

Abstract: A computer system that selectively disables power to wake on LAN (WOL) devices in the absence of AC power. In one embodiment, the computer system comprises a power supply and a power management controller. The power supply is configured to provide power to a wakeup device. The power management controller receives an AC voltage sense signal that indicates the presence or absence of an AC power source and enables the power supply to provide power to the wakeup device when the AC voltage sense signal is asserted. The power management controller preferably disables the power supply when the AC voltage sense signal is de-asserted. The computer system may operate in several states including an off state, a power on self test (POST) state, a working state, a trap state, and an armed state.

Abstract: A PC includes a main body housing and lid. The main body housing has an input unit on the upper surface, and the lid pivotally attached to the back portion via a hinge. The lid has a liquid crystal display on the inner surface, and an antenna disposed above the display to communicate with a peripheral device. The PC has a detector made up of a push type switch and projection for detecting the open/closed state of the lid. The CPU of the PC detects the open/closed state of the lid by a detection signal from the detector, and controls shift of the peripheral device between a normal mode and a power saving mode.

Abstract: A system and method for monitoring and controlling a power-manageable resource. In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number of power-manageable devices. A resource monitor may also be coupled to the power-manageable resource. The resource monitor may be configured to monitor the devices coupled to the power manageable resource. More specifically, the functions of the resource monitor may include monitoring the active/inactive state of each of the attached devices. The resource monitor may be configured to cause the sharable resource to be powered down if it is determined that all the attached devices are in an inactive state.

Abstract: According to the power shutoff method for the TCP/IP network device, the connection status of the terminal connected to the TCP/IP network is monitored, whether the power can be shut off or not is judged based on the result of the monitoring, and the power for the terminal is shut off when it is judged acceptable to shut off the power in the judgment step.

Abstract: Byte synchronization between a bus master and a serial interface or other bus slave is maintained and promptly corrected by using a unique signal, issued by the serial interface, to promptly and unambiguously notify the bus master of a loss of synchronization, followed by prompt resynchronization by the bus master. The serial interface sets a selected indicium in a status register equal to a selected value, when an invalid command is sensed at the interface. The bus master reads the status register and, when the selected indicium has the selected value, promptly resynchronizes the serial interface without further delay.