Abstract: The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.

Abstract: A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay.

Abstract: A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

Abstract: Disclosed is a method that enables a smart card to exchange data with an apparatus, which is intended to supply the smart card with a permanent clock signal in a permanent mode of operation. The method according to the invention includes the steps of detecting, in the course of the permanent mode of operation, of an impending disappearance of the permanent clock signal, wherein the detecting step includes a comparison of the value of the amplitude of the permanent clock signal with a predetermined value; and substituting an auxiliary clock signal for the permanent clock signal. The invention enables the smart card to receive, after the disappearance of the permanent clock signal, a number of clock pulses which suffices for completing pending read/write operations.

Abstract: Method, program product, and apparatus for providing a nondisruptive takeover by a backup adapter when an adapter from a group of adapters connecting a data processing system to a Local Area Network (LAN) fails. The adapters are arranged in one or more groups, with each group having at least two members, one member being a backup adapter in the idle state. Primitives, in accordance with the IEEE 802.2 standard, are monitored for each adapter, and when a failure is detected, the Medium Access Control (MAC) address for that adapter is loaded in the backup adapter, and the backup adapter is placed in the active state to nondisruptively takeover for the failed adapter.

Abstract: A base station, mobile station, and/or other terminal includes physical layer (layer 1) protocol and link layer (layer 2) protocol enhancements that interact with one another to cause the link layer protocol to inhibit is ARQ operations for data blocks having missing data packets that are still pending at the physical layer. A mobile station (or base station) receives a data packet from a base station across a wireless link. The physical layer then determines, a number, N, of data packets pending with its physical layer Automatic Retransmission reQuest (ARQ) operations. The physical layer then passes the data packet and the number, N, to a link layer operating on the mobile station. The link layer then modifies its ARQ operations based upon the number, N, of data packets pending with the physical layer ARQ operations. The link layer inhibits ARQ operations for data blocks missing data packets that are still pending with the physical layer.

Abstract: A system, method, and apparatus for providing continuous operations of a user application at a user computing device. At least two application servers are provided with each application server running the user application concurrently and independently. Each application server may have a persistent storage device associated with it for storing data. In response to a user request for data processing within the user application, the user request is transmitted to the at least two application servers for processing therein. A return result—responsive to the user request as processed by the one of the at least two application servers—is passed to the user computing device from one of the at least two application servers. In this manner, if one of the application servers fails or becomes unavailable due to a disaster or otherwise, the user requests can be continuously processed by at least the other application server without any delays.

Abstract: A service processor has a memory, and a controller coupled to the memory. The controller is configured to perform part of a maintenance procedure on a data storage system such that a state of the data storage system transitions from a first state to a second state, and store, in a memory, a data structure identifying the second state. The controller is further configured to, after the maintenance procedure is aborted prior to completion of the maintenance procedure and after a transition of the state of the data storage system from the second state to a third state, (i) restore the data storage system to the second state based on the data structure stored in the memory, and (ii) complete the maintenance procedure.

Abstract: A CPU unit comprising a microprocessor for controlling a controlled system according to a stored sequence program and predetermined data, and a memory area where the sequence program and predetermined data are stored and a second sequence predetermined data both used by a preset operation proxy controlled unit are stored, wherein when the microprocessor detects an abnormality of the operation proxy controlled unit, the microprocessor controls the operation proxy controlled unit according to the second sequence program and second predetermined data after the microprocessor ends the predetermined processings of the unit.

Abstract: A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Abstract: An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A writeable K by P trace array with parallel inputs and outputs is incorporated within a VLSI integrated circuit. The trace array is partitioned into N sub-arrays each sub-array having M=P/N entries for the K input signals. Logic circuitry couples selected K input signals to the trace array so that M states of the K input signals may be stored in each of the N sub-arrays. A start signal enables storing of states of the K input signals at time intervals determined by a clock. The clock is counted in a counter and when M is reached the counter is reset back to an initial state. New states of the K input signals written over old states until a pre-determined event signals occurs, at which time storing the sub-array is stopped saving the stored states of the logic inputs. Writing is simultaneously started in a succeeding sub-array in the same fashion until another event signal occurs.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A technique for reporting a hard disk drive failure in a computer system includes detecting a failure of one of a plurality of hard disk drives and reporting the failure to a CIMOM (Conceptual Information Model Object Manager) which in turn forwards a message by an LRA (Local Response Agent) to a PMP (Platform Management Provider which in turn forwards a command to an SMC (Server Management Controller), which forward the command to an HSC (Hot-Swap Controller) activate a display, the display reporting the failure or of a particular one of the hard disk drives to a user.

Abstract: A data switch is configured to communicate data messages in the form of multibit data unit segmented into a plurality of multibit data subunits. The data switch includes at least two separate, parallel switching units, each having a plurality of ports to communicate the multibit data subunits. Hardwired or software implemented prioritization logic provides for the initiations of transfer of data messages between the ports in response to a category of the data messages. A memory is used to store a history of prior data message transfers so that least recently transferred message types are serviced prior to those most recently switched. So as to reestablish synchronization between the parallel switching units, such as loss of a data subunit, a controller responds to a reset condition by temporarily suspending communications between affected ones of the ports and clearing the history so to recommence lock-step operations of the units.

Abstract: An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.

Abstract: A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.

Abstract: A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.

Abstract: A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for enabling or disabling access to the test resources, a test port associated with each test resource, each test port including a test port enable output for connection to an enable input of an associated test resource; and an input for receiving a serial output of the associated test resource; and a selector for selecting a test resource for communication therewith.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: The invention relates to a method in a wireless communication system (1) comprising wireless terminals (MT1-MT4), a communication channel (CH) and at, least one access point (AP1, AP2) and access point controller (AC1, AC2). The method comprises the steps of activating at least one data transmission connection between the wireless terminal (MT1-MT4) and the access point (AP1), in which information is transmitted in packets, forming data frames (FR) for the transmission of the packets, supplementing said data frame (FR) with at least one item of error checking data, in whose formation at least a part of the information contained in the data frame (FR) is used, converting said data frames (FR) into signals to be transmitted on the communication channel, receiving signals transmitted on the communication channel and converting them into data frames, forming reference.

Abstract: An information reproduction apparatus includes an error corrector which performs a first error correction for correcting errors in a horizontal direction within an input data block comprised of a product code and subsequently a second error correction for correcting errors in a vertical direction within the same block is disclosed. The error corrector produces a first signal each time an uncorrectable code word is detected while the first error correction is being performed. The apparatus further includes a first counter for counting the first signal, a comparator for comparing a count value of the first counter with a predetermined value and producing a second signal when the count value reaches the predetermined value, and a determination device determining that there is an error within the data block which the error corrector cannot correct, and delivering a third signal in response to the second signal to reread the data block.

Abstract: Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.

Abstract: An apparatus includes a plurality of AND gates each to receive as input a bit of a first binary vector and a corresponding bit of a second binary vector, where the length of the first binary vector is not greater than the length of the second binary vector. The apparatus also includes a multiple input XOR gate to calculate in a single cycle a scalar product of the first binary vector and the second binary vector by performing an exclusive OR operation on the output of each of the AND gates.

Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

Abstract: A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient.

Abstract: A maximum a posteriori (MAP) detector/decoder employs an algorithm that computes log-likelihood value with an a posteriori probability (APP) value employing a number N of previous state sequences greater than or equal to two (N≧2). By defining the APP with more previous state sequences, the set of &agr; values may be calculated for a current state and then reduced. After generating the reduced set of &agr; values, the full set of &bgr; values may be generated for calculation of log-likelihood values. By calculating a set of &agr; values that may be decimated by, for example, N, the amount of memory required to store the &agr; values used in subsequent computations is reduced.

Abstract: An authoring system and procedure for organizing photos (and other physical object types) are provided. Using the authoring system, an author organizes a set of physical objects into a particular story through an interface. Each physical object is associated with a specific identifier, such as a barcode, and the author uses an input device to scan identifiers of selected physical objects that are to be included within the particular story. The authoring process is performed off-line. Using the input device, the author adds her own commentary as part of building the story. For example, she can associate an audio clip with a particular physical object that makes up the story or with the entire story itself. In one embodiment, the input device includes a microphone for receiving voice input, as well as a barcode reader for scanning a particular barcode of a selected physical object. The author also selects one or more presentation styles that will be used to display the entire story.

Abstract: A method of generating an image or a video stream in which the composition space in a standard display tool is used as the composition space. One example of a standard display tool is an HTML-compliant browser. In one embodiment, an image or a video editor gains control of the timer and the frame grabber of the standard display tool, a document encoded in a standard display language is received by the standard display tool, the editor controls the timing according to quality requirements, the standard display tool composes an image from the document in the compositor space of the standard display tool, the frame grabber transmits the image to a destination. Where the invention supports video streaming, the destination is a video compressor that collects a series of images as frames, and generates a video stream from the images.

Abstract: A method of performing distributed development of a computer software application by using a WebDAV (Web Distributed Authoring and Versioning) client, to access a WebDAV server, ensures that referential integrity is maintained when checking in documents from the client top the server.

Abstract: A system and method of highlighting and manipulating text of different languages or fonts which are matched to a best-matching font are presented. Today's operating systems do not provide the native tools and functions to easily display text of unknown language or multiple languages. The complexity of any underlying code that handles a multilingual display is sharply increased due to the text being segmented into multiple text runs. The invention employs character set engine that provides necessary character set guessing functionality, as well as an enumerator module to build a linked list of suitable output fonts to display text from an arbitrary language, and multilingual text. Output can be granted by traversing that list. Different portions of the sequence of languages in the text may have minimum outline, start and end markers and other highlighting and other text manipulation features scaled or adjusted according to the differing fonts.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: The states of a logic circuit block are set as operation start states and operation end states. An instruction to be analyzed is selected from input/output instruction information. An input signal corresponding to the selected instruction is applied to an RT (Register Transfer)-level model that is in the operation start state. Then, the input signal value applied to the RT-level model is changed. In order to extract operation of the logic circuit block, the RT-level model is analyzed until it reaches the operation end state. An operation model of the logic circuit block is produced based on the extracted operations. In this way, the model of the logic circuit block specifically described at RT level can be converted into a high abstraction-level model including no concept of time.

Abstract: Systems and methods for linking a graphical display and an n-dimensional data structure in a graphical user interface are provided. One is a method for linking a graphical display and an n-dimensional data structure in a graphical user interface supported by a computer application. Briefly described, one such method comprises the steps of: providing a graphical user interface, the graphical user interface comprising a first portion for providing a graphical display comprising one or more image objects and a second portion for providing an n-dimensional data structure associated with the graphical display; receiving a user selection of one of the image objects in the first portion of the graphical user interface; and populating the n-dimensional data structure based on the selection of the image object.

Abstract: An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: For drivers of different sizes driving signal lines of different lengths, maximum transition time constraints are compared to signal transition times to determine whether a potential noise problem exists with respect to the signal lines. Each driver size has a maximum line length and a maximum transition time associated with it. These maximum transition time constraints are used to determine whether the signal lines connected to respective drivers in the IC will have potential noise problems associated with them. For each signal line in the IC design, the signal transition time is determined and compared to the maximum transition time constraint. If the signal transition time exceeds the maximum transition time constraint, a potential noise problem exists with respect to the signal line.

Abstract: A method and mechanism for performing a timing analysis on virtual component blocks, which is an abstraction of a circuit block is provided. A set of modes for a circuit block are identified, where a mode is a set of meaningful control input values. Each functionally meaningful or useful control input combination is applied to the circuit block. For each control input combination applied, a delay for each data input/output path and each control input/output path not passing through a blocked circuit node for the applied combination of control inputs is calculated. The delay information for the data paths and control paths is stored within a timing model. The delay information may include a maximum or minimum delay for the circuit block. The timing of sequential circuit blocks may also characterized using the methods and mechanisms herein.

Abstract: A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.

Abstract: A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

Abstract: Probe points can be inserted (430) into an FPGA-based embedded processor SoC (305a) while specifying hardware and software cores with a design automation tool. This tool then aids the user (via high level GUI) in imbedding logic analysis functions in the SoC and connecting selected monitor signals to the logic analyzer. The design automation tool provides the necessary support files for the logic analysis software suite for naming and formatting of monitor signals on the waveform display. Trigger and trace information can be captured for the probe points and waveforms representing the captured information can be displayed (450) for analysis. An integrated logic analyzer core can be downloaded (440) into the FPGA-based embedded processor SoC to facilitate insertion of the probe points and capture of information. A software application can receive the captured information and translate it into a format suitable for display.

Abstract: Method and code for dedicated resource placement enhancement is described. More particularly, a local area of a network is obtained for determining placement options of logic blocks to increase availability of dedicated resources within the local area. Each placement option is scored. This scoring may be based in part on whether a signal is to be propagated over a dedicated resource, and whether this signal is presently meeting a slack or target delay. Logic blocks, and therefore the dedicated resources, are placed after scoring.

Abstract: A method for designing at least one mask for manufacturing an integrated circuit is disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.

Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.

Abstract: A method and apparatus that automatically creates the user interface in an object-oriented software program, without the need for explicit user interface code, is disclosed. The present invention includes a visual object base class with functions that support the creation and management of views, one or more instrumented object classes that are subclasses of the visual object base class and from which instrumented objects are created, and a Visualization Engine. Each instrumented object class defines one or more of the class members to be visual elements that are capable of being represented in the user interface environment.

Abstract: Techniques for gathering execution information about an application, such as a distributed application, are described. Key communication points in cross execution context calls, such as remote procedure calls, are determined and control is transferred to interception routines to insert and extract execution information. Outgoing remote procedure calls are intercepted on a client that inserts call origin information into the request sent to a server system. The server system intercepts and extracts the call origin information and additionally inserts other information in a response sent to the client system upon completion of a remote procedure call. In turn, the client system intercepts the response and extracts other performance information. On each client and server system, information is gathered by a reader and forwarded to a local collector. Program execution data may be collected and correlated for coordinated application monitoring.

Abstract: Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.