Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: Nonvolatile memory cells are arranged at crossing points of bit-lines and word-lines. A mode signal indicates whether the nonvolatile memory cells are to be used as a RAM or as a ROM. When the nonvolatile memory cells are to be used as RAM, current is allowed to flow through the bit-lines in one specific direction, current is allowed to flow through the word-lines and the direction of the current flowing through the word-lines is adjusted to write data in the nonvolatile memory cells. When the nonvolatile memory cells are to be used as ROM, no current is allowed to flow through the bit-lines or the word-lines so that data can not be written in the nonvolatile memory cells.

Abstract: Magnetic memory elements and methods for forming the same, where a magnetic memory element includes an etch stop layer disposed between a lower electrode and a magnetoresistive cell body or stack. The etch stop layer advantageously protects the lower electrode during patterning of the magnetoresistive cell body. The etch stop layer can be patterned with patterning of the magnetoresistive cell body. The etch stop layer can be formed from conductive materials or from resistive materials. When the etch stop layer is formed from resistive materials, the etch stop layer forms an in situ resistor that can isolate a failed memory cell from other memory cells in a corresponding array of cells, such as in an MRAM. This permits the MRAM to continue to utilize other magnetoresistive cells that are coupled to the electrodes in the event of a failure of the magnetoresistive cell.

Abstract: The invention includes a method of providing magnetic stability of a memory cell. The memory cell is generally located proximate to a conductive line, and proximate to a write mechanism that can set a magnetic state of the memory cell. The method includes receiving a representation of a maximum magnetic field intensity available from the write mechanism. A desirable placement of the memory cell relative to the conductive line can be generated for providing stability of the memory cell, while still allowing the write mechanism to change the magnetic state of the memory cell.

Abstract: An improved voltage reduction circuit and method is described that incorporates an independently controllable back bias voltage for increased gate/bulk fields in isolation well voltage reduction transistors that couple to and reduce external voltages that are too high for the integrated circuit process technology limits. The improved voltage reduction circuit and method allows for a higher overall available voltage and current flow for regulation by the circuit. Additionally, the improved voltage reduction circuit and method reduces voltage reduction circuit size by allowing for efficient implementation in a single isolation well. Furthermore, the improved voltage reduction circuit and method includes a back bias voltage control circuit that turns on and regulates the back bias voltage and avoids the problem of reverse bias conditions.

Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

Abstract: A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks.

Abstract: Programming efficiency of a read only memory (ROM) embedded dynamic random access memory (DRAM) is improved by programming only one polarity of bits in non-volatile cells of the ROM embedded DRAM, and then blanket programming volatile cells in the ROM embedded DRAM to represent the remaining bits.

Abstract: A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Abstract: The soft error rate in a semiconductor memory is improved via the use of a circuit and arrangement adapted to use a mirror bit to recover from a soft error. According to an example embodiment of the present invention, a semiconductor device includes first and mirror memory cells configured and arranged to receive and store a same bit in response to a write operation, with the memory cells more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a change from the second state into the first state. The memory cells are separated by a distance that is sufficient to make the likelihood of both memory cells being upset by a same source very low. For a read operation, the bits stored at the fist and second memory cells are compared. If the bits are the same, the bit from the first and/or mirror bit is read out, and if the bits are different, a bit corresponding to the more susceptible state is read out. In this manner, soft errors can be overcome.

Abstract: A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory units for the replacement of defective data memory units of the main data memory, and a redundancy control logic for controlling the access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, and the main data memory and the redundancy control logic being connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.

Abstract: A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.

Abstract: In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

Abstract: A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.

Abstract: A method for repairing a memory cell having a plurality of bit lines. The memory cell is tested with a compression testing mode, and future testing is set to compression testing mode when an error is detected, or to normal testing mode when no error is detected. It is determined whether detected errors warrant repair, and all repairs deemed necessary are performed.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A memory device is disclosed having a column select transistor gate that is controlled by tri-statable control logic. The tri-statable control logic operates to allow the gate of the column select transistor to float during sensing of the bit cell. The column select transistor acts as a floating gate amplifier, i.e. a common gate amplifier having a gate that floats during the sensing period. In addition, the column select transistor can operate to facilitate decoding of the memory and to allow precharge of a bit line of a memory cell. Further, avoidance of a static power drain is made possible by the fact that the gate is floating during the sensing period.

Abstract: A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.

Abstract: A memory circuit 2 includes a plurality of memory cells 4, 6 which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit lines A, Abar, B, Bbar associated with the memory cells 4, 6. During a subsequent precharge operation serving to restore the precharged voltage levels of the bit lines A, Abar, B Bbar charge sharing is performed between non-accessed bit lines and those which have been accessed and accordingly at least partially discharged. Also the precharging circuits 12, 14, 16, 18 associated with the non-accessed bit lines contribute towards the precharging operation.

Abstract: A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on conditions, initial power-up and flash programming. Charge pump feedback logic is employed to detect the charge pump turn-on condition and activate the proper pre-programmed soft-start setting loaded in the memory registers.

Abstract: A semiconductor memory device has a plurality of sub power source lines for supplying a power source voltage to memory cells, a main power source line for supplying the power source voltage to the sub power source lines, and a plurality of fuse elements for connecting the main power source line to the sub power source lines. Predetermined number of the sub power source lines are commonly connected by one of plurality of common connecting sections. Each of the common connecting sections is disposed at one ends of the sub power source lines. Each of the common connecting sections is connected to the main power source line through each of the fuse elements. The number of the sub power source lines connected to the common connecting section is equal to the number of the sub word lines subordinate to one main word line, and also equal to the number of the redundant sub word lines subordinate to one redundant main word line.

Abstract: A voltage generation section, which generates voltages for driving the control gates in a plurality of nonvolatile memory cells, has a booster circuit and a voltage control circuit. The voltage control circuit has a plurality of voltage output terminals, and switches and outputs a plurality of voltages inputted from the booster circuit to a plurality of voltage output terminals in accordance with a selection state of the nonvolatile memory cell. The voltage control circuit pre-drives a control gate line by outputting a maximum voltage among the voltages to all of the voltage output terminals in a pre-drive period. A disconnection state, in which no voltage from the booster circuit is outputted, is set in a period prior to the pre-drive period, and a power supply voltage may be outputted instead of the voltage from the booster circuit.

Abstract: A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node is configured to receive a charge. A first transistor has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.

Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.

Abstract: A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

Abstract: A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additional, a voltage pump can supply operating voltage to the inverter to assist in overdriving the wordline. A voltage sink can also be coupled to the inverter which, in combination with the voltage pump, can be used to shift the output voltages used to turn the wordline on and off. A second inverter can also be added, and in such a case the transistors within the latch and the first inverter can be reduced in size, switching time, and power consumption.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: In a memory controller for use with a DDR SDRAM, an apparatus improves the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method adjusts the noise immunity provided by the apparatus. In particular DQS quality circuits frame the DQS signal for a predetermined portion of the READ operation.

Abstract: An efficient invention for opening two pages of memory for a DRAM are discussed.

Abstract: A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a partitioned memory configuration is implemented to backup the data word and its associated error correction code to the non-volatile memory. In this way the non-volatile memory is able to store a range of counts whose maximum number far exceeds the memory's endurance limit.

Abstract: A reproduction apparatus and a reproduction method by which an error of time information that arises from interruption of power supplied to a timer that manages the term of term-managed contents data is minimized to allow accurate term management of the contents data. The timer produces time information when power is supplied to the timer from a cell, but the timer stops operating when no power is supplied thereto. The time information produced by the timer is stored into a memory, and the memory holds the stored time information when no power is supplied to the timer. When power from the cell is restored to the timer, the timer is set accordingly to the time information stored in the memory, so that the timer may thereafter produce correct time information thereby allowing term management of the term-managed contents data to be performed accurately.

Abstract: A handheld childbirth labor timing apparatus includes a timing device with a visible display, a calculating device, a memory device and a selection device. In various embodiments the apparatus is programmed to execute methods for the simple timing of the durations of and intervals between actual childbirth contractions, for practicing selected sequences of such contractions in preparing for childbirth, and also for storing a set of expected sequences that, when matched, with an actual childbirth labor sequence will present an alerting signal to the user so as to timely summon medical help.

Abstract: A method and apparatus for precision time interval measurement in a time-of-flight mass spectrometer (TOF-MS). The method and apparatus produces an instrument capable of measuring bursts of data occurring at rates much higher than the average data rate. An asynchronous serial stream of data, consisting of a start pulse followed by an arbitrary number of stop pulses, repeated an arbitrary number of times, is converted into a digital stream of data synchronized to a precision master clock. Conversion of the asynchronous, analog data to synchronous digital data simplifies the measurement task by allowing the use of powerful, low-cost digital logic in the measurement.

Abstract: An automotive audio system includes a first unit for acquiring a sound signal to be reproduced, a second unit for controlling the first unit by means of a control signal and also reproducing the supplied sound signal, and a bus for establishing communication between the first unit and the second unit. The control signal and the sound signal are transferred in digital format between the first unit and the second unit via the bus.

Abstract: A method and device for recording information blocks on a record carrier is described. The device has control means 20 for recording and retrieving position data indicative of the position of the recorded information blocks. The control means include a mapping unit 31 for determining in which region the information block is recorded and a detection unit 32. The region is one of a number of consecutive regions constituting the recordable area. The mapping unit records a random signal unit in a unit location in a mapping area. The unit location indicates said region, and the unit length of the random signal unit is smaller then the length of said information block. The detection unit 32 detects the presence of the recorded random signal units in said mapping area and so determines if a region contains at least one information block. The highest written address is found by detecting the highest written unit location in the mapping area, and subsequently searching said region for the presence of recorded marks.

Abstract: A control system and method for controlling a sled of an optical storage device by using a stepping motor. The optical storage device includes a pick-up head having a lens and a sled. The control system includes a tracking actuator's controller used to receive a tracking signal TE for generating a tracking control signal TRO to control positions of the lens; a numerical controller connected with the tracking actuator's controller used to receive the tracking control signal TRO for generating a numerical control signal; a frequency converter connected with the numerical controller used to receive the numerical control signal for generating a pulse flag signal and a direction flag signal; and a ring generator connected with the frequency converter used to receive the pulse and direction flag signal for producing a sled control signal to drive the stepping motor for controlling the sled.

Abstract: An information processing apparatus is preferably made to contain hardware components of plural turntables, plural head units, plural decoding units, at least one encoding unit, and a system control unit. These components are adapted in such a manner as to afford (1) true multitasking in information reading and writing, (2) direct communication for information to be exchanged directly within the information processing apparatus, (3) disc removability for information to be stored as off-line archives and to become transportable between computer systems, (4) separation of user-created data from program files for eliminating time-consuming file-defragmentation processing and for conveniently safekeeping the user-created data, and (5) capability of launching favored software programs directly from original software discs.

Abstract: A drive device has a feed mechanism that causes a control object to move in order to control the positioning of the control object, a motor that serves as the drive source of said feed mechanism, and a control means that controls this motor. The control means has an operation history memory unit that stores the operation history of whether the motor is doing an initial start or a restart, and a command selection unit that selects control commands and outputs them to said motor based on information stored in said operation history memory unit. Because intermittent operation that repeatedly drives and stops the motor occurs when there is a restart, the thermal shutdown associated with overheating of the driver IC is avoided, and any difference between the feed amount due to the control means and the actual feed amount can be prevented.

Abstract: A grating mounting section 10 for mounting a laser diode 3 and a diffraction grating element 8 is formed in a frame body 2 of an optical pickup device. The diffraction grating element 8 includes a main body 83 provided with a grating face 82, a holder 84 being integral with the main body 83 while surrounding the same, and an arm portion 81 protruded outward from the outer circumferential face of the holder 84 as viewed in the radial direction. The arm portion 81 is protruded outward through a groove 22 formed in the grating mounting section 10 of the frame body side. An angular position adjustment of the diffraction grating element 8 can be carried out by turning the arm portion 81 about the optical axis.

Abstract: It is an optical information recording and reading apparatus for recording and/or reading information at a high density by using a near-field light-generating device as a near-field optical head. The end surface of the core of a flexible optical waveguide is formed in an intermediate position in the optical waveguide and in a portion fixed to the near-field optical head. Light for recording and reading information is spread within the clad. The spread light flux is reflected toward the near-field optical head by a reflective surface formed on the side of one end of the optical waveguide. The reflected light flux is collected by light-collecting structures and then is made to enter an optical minute aperture formed in the near-field optical head. Near-field light is created near the minute aperture. Light scattered by the surface of the recording medium is received. Thus, information on the recording medium can be recorded and read.

Abstract: A magnetic restoring device of actuator provides a sufficient magnetic restoring force for stably holding a movable part of actuator in a neutral position. The actuator acts as an objective lens driving device in an optical pickup. A non-contact magnetic restoring mechanism is provided for causing pickup to return to a neutral position after a focusing or tracking operation. The magnetic restoring device comprises magnets, two magnetic inductive members, and two yokes wherein magnets and yokes are opposite; one arc-shaped surface is formed on the magnet in the focusing direction; and the other one is formed on the magnet in the tracking direction. The magnetic inductive members are provided between the magnets and the yokes to form a magnetic circuit, thereby increasing a magnetic field intensity and sensitivity of actuator. The device increases a magnetic restoring force in the focusing and tracking directions respectively.

Abstract: An objective lens converges a shorter wavelength laser beam on a DVD having a protective layer, which is 0.6 mm thick, and a longer wavelength laser beam on a CD having a protective layer, which is 1.2 mm thick. A common region is defined on the objective lens. The common region provides a numerical aperture appropriate for converging the longer wavelength laser beam on the CD. Coma of the objective lens in the first region is compensated better in a case where the longer wavelength laser beam is converged on the CD than a case where the shorter wavelength laser beam is converged on the DVD.

Abstract: An actuator control device is provided for performing some modifications such as making the output of a disturbance observer zero for quickly restoring the proper tracking control if the out-of-track state takes place and if the outside force exceeding the maximum force generated by an actuator is applied to the device itself. In the actuator control device, a disturbance observer estimates disturbance added to the actuator. The second control signal corresponding to the estimated disturbance is added to the first control signal. The added signal is made to be a third control signal. Further, the second control signal is stored in a storage unit. The stored value is further added to the third control signal as the fifth control signal. By performing some modifications such as making the second control signal zero according to the abnormal state, this arrangement makes it possible to quickly restore the proper tracking control even if the out-of-track state takes place.

Abstract: Disclosed is an apparatus for controlling eccentricity in a photo-record player and a control method thereof. A relative eccentric quantity is found from a TE signal (or, tracking driving voltage) induced per one revolution of disc ‘on track’and an eccentricity phase to be controlled is found from a periodicity of TE (or, tracking driving voltage) per one revolution of disc. A suitable compensating value for the relation between the found eccentricity quantity and phase is generated by taking FG representing a period of revolution as a reference. Then, the compensating value is used for an eccentricity control ‘on track’, or driving the tracking actuator on ‘seek’. Therefore, the present invention reduces a seek location error due to the eccentricity on ‘seek’, thereby enabling to increase a seek performance.

Abstract: A recording medium storing linking type information and a method of processing a defective area in the medium. The recording medium stores information indicating that linking is applied immediately after the defective area, distinguishing a linking type which occurs in a general incremental recording mode from a linking type which occurs after the defective area. Defective areas are detected and registered in a predetermined area (recording management data (RMD) area) before user data is recorded or while user data is being recorded in the recording medium having a plurality of continuous basic recording units, such as a digital versatile disc-rewritable (DVD-RW) in which recording and reproducing can be done repeatedly. Linking is not only applied in an incremental recording mode or in a restricted overwrite recording mode, but linking is also applied to an area immediately after the defective area which is registered in the defect list, increasing reliability of the user data.