Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells,

Abstract: The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain.

Abstract: A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform include read out, initialization, and entanglement. The state of a qubit can be determined by grounding the qubit, applying a current across the qubit, measuring the resulting potential drop across the qubit, and interpreting the potential drop as a state of the qubit. A qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction for a time sufficient that the quantum state of the qubit can relax into the selected state. In some embodiments, the qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction and then ramping the current to zero in order that the state of the qubit relaxes into the selected state.

Abstract: A method of reading a selected resistive memory bit having its output connected to a bitline, which is connected to a plurality of unselected electrically parallel resistive memory bits, is provided. The method comprises selecting the resistive memory bit to be read by applying a read voltage to an input of the resistive memory bit, and unselecting the plurality of unselected resistive memory bits by applying a deselect voltage to all inputs of the unselected resistive memory bits. The current out of the bitline is then sensed by a current sensor. A memory device is also provided comprising a plurality of resistive memory bits connected to a shared bitline, a means for selecting a single bit from the plurality of resistive memory bits, a means for deselecting the remaining, unselected bits from the plurality of resistive memory bits and a means for sensing the output current from the bitline.

Abstract: An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.

Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

Abstract: An interfacing circuit for reducing current consumption includes a command decoder, an operation controller, and a transmission controller. The command decoder decodes input packet commands and generates corresponding commands. The operation controller generates first through N-th operation signals for performing operations corresponding to the commands in response to a clock signal. The transmission controller transmits the first through N-th operation signals as first through N-th control signals in response to the clock signal. The transmission controller comprises a reset signal generator which generates a reset signal for interrupting the transmission of the first control signal when multiple commands of the first through N-th commands are generated simultaneously, wherein the commands would otherwise incorrectly operate the circuit receiving the first through N-th control signals when the commands are generated simultaneously.

Abstract: A magnetic memory includes a plurality of variable resistors arrayed as memory elements in a matrix, a plurality of bit lines each of which is arranged on each row of the matrix and connected to one terminal of each of variable resistors belonging to the same row, a read circuit which detects the resistance values of the variable resistors based on currents flowing through the bit lines, and load elements arranged on the bit lines independently of the memory elements.

Abstract: A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.

Abstract: A digital magnetic memory cell device for read and/or write operations, having a soft-magnetic read and/or write layer system and at least one hard-magnetic reference layer system, which is designed as an AAF system and includes at least one reference layer, wherein the reference layer system has a layer section comprising at least one bias layer system with at least one ferrimagnetic layer, the magnetic moments of the bias layer system and of the reference layer being coupled in opposite directions via a coupling layer.

Abstract: A method and system for providing a magnetic element and a corresponding memory are disclosed. In one aspect, the method and system include providing a dual spin tunnel/valve structure and at least one spin valve. The dual spin tunnel/valve structure includes a nonmagnetic spacer layer between a pinned layer and a free layer, another pinned layer and a barrier layer between the free layer and the other pinned layer. The free layers of the dual spin tunnel/valve structure and the spin valve are magnetostatically coupled. In one embodiment a separation layer resides between the dual spin tunnel/valve structure and the spin valve. In another aspect, the method and system include providing two dual spin valves, a spin tunneling junction there between and, in one embodiment, the separation layer. In both aspects, the magnetic element is configured to write to the free layers using spin transfer when a write current is passed through the magnetic element.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a fill read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.

Abstract: A method of programming a memory includes the steps of attempting to program a bit at a designated address for a predetermined time; testing the bit to see if it has been programmed; increasing the predetermined time by approximately an order of magnitude; repeating the previous steps (until the bit at the designated address is programmed; and repeating all the previous steps by advancing the designated address until all bits in the memory are programmed.

Abstract: A refresh zone detection part divides a block of a semiconductor memory into refresh zone units for executing refresh, and detects the refresh zone including the sector of the writing target. A refresh execution part sequentially refreshes the sectors included in the refresh zone detected by refresh zone detection part, every time data is written to a sector. Thus, it is possible to prevent the number of rewritings to a specific sector from increasing, and the refresh can prevent data change due to accumulative disturbance.

Abstract: A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1-MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1-MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).

Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: A selector selects one standard voltage from among divided voltages from a voltage dividing circuit and a reference voltage from a reference voltage generating circuit, in accordance with a test mode enable signal and a reference voltage select signal. An internal voltage generating circuit receives the standard voltage from the selector and generates an internal power supply voltage.

Abstract: A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorisation key. An authorisation unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorisation key. The authorisation key is typically supplied by a support centre in response to being notified of the device identifier. In one embodiment, the authorisation unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorisation key.

Abstract: A semiconductor device includes a primary memory array, primary addressing circuitry, a redundant memory array, redundant addressing circuitry, and a first signal pad. The primary memory array includes primary memory elements operable to store data, and the primary addressing circuit is operable to select the primary memory elements. The redundant memory array includes redundant memory elements operable to store data and is also operable to be programmed from a programmable state to provide redundant memory elements for defective primary memory elements. The first signal pad is operable to receive serial selection data, and the redundant addressing circuit is connected to the first signal pad and is operable to receive the serial selection data from the first signal pad and select the redundant memory elements in response.

Abstract: A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

Abstract: An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.

Abstract: A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

Abstract: Provided is a semiconductor storage unit in which semiconductor storage unit manufacturers can protect data in their products after the products are put on the market. The semiconductor storage unit includes: a user memory that serves to one of reading and writing of data and is accessible upon a first instruction; a redundant memory that serves to one of reading and writing of data and is accessible upon a second instruction; an input control circuit for outputting a signal after analyzing the instructions that are inputted to the input interface; an access control circuit for allowing access to the user memory or the redundant memory; an address decoder that outputs, a signal for choosing a memory cell of the user memory or of the redundant memory to the user memory or to the redundant memory; and an output control circuit for reading data of the user memory or the redundant memory.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: The present invention relates to a memory cell having a quasi-folded bit line sensing arrangement with an open bit line cell array. The memory cell array noise is negligible compared to the conventional open bit line. Also, the twisted bit line structure can be applied for the invention to reduce the inter-bit line coupling noise. The embodiments of the present invention reduce the size of the edge array, reduce the sensing power requirements, and provide a simple bit line layout. According to one embodiment of the present invention, a memory device comprises a plurality of sense amplifiers, each sense amplifier enabling access to data associated with arrays of cells; a bit line pair being coupled to each sense amplifier and comprising a bit line and a complementary bit line; a plurality of word lines associated with an array of cells; and a plurality of switches is employed to enable access to memory cells of the memory device.

Abstract: A main power supply line and a main ground wiring provided to supply power from one side (a first direction) of a memory region, a main power supply line and a main ground wiring provided to supply the power from the other side (a second direction opposite to the first direction) of the memory region are provided in a column direction. A bit line driver arranged on one side is supplied with power from one side, and a bit line driver arranged on the other side is supplied with the power from the other side. As a result, no current path is formed in a region of the power supply lines on the selected memory region.

Abstract: The present disclosure relates to a semiconductor memory device. A charge recycling circuit is driven to raise a potential of a restore node and a sensing bar node to a given potential before a sensing operation is performed. After the sensing operation is performed, electric charges discharged from the restore node and from the sensing bar node are stored using the charge recycling circuit and can then be used when a next sensing operation is performed. Therefore, current consumed when the sensing operation is performed can be reduced and the power consumption can be thus reduced.

Abstract: A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.

Abstract: An array of memory cells that require periodic refresh is operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the differential-cell standby mode, as a local clock signal is provided to implement the refresh operations during standby mode.

Abstract: The present invention is directed to a method and apparatus for providing variable output drive capability to an output driver. One aspect of the present invention is related to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is used to enable certain of the pre-driver output stages in each output path. Another aspect of the present invention is related to a method of correcting output skews in a subsequent amplification stage. Other aspects of the present invention relate to a portion of a data path, a memory device, and a computer system all having a pre-driver with pre-driver output transistors responsive to signals indicative of the strength of output drive transistors.

Abstract: The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

Abstract: The invention relates to a shaking incubator with at least one specimen storage device comprising several superposed specimen storage spaces. A shaking unit comprising a specimen storage position, a shaking platform and a base unit is arranged in at least one specimen storage space. The invention makes it possible to shake different specimens, located in the same specimen storage device, individually and independently of each other under incubator conditions.

Abstract: A machine for combining powder material with cohesive site-won spoil has an input hopper (4) which provides a preliminary breaking up step. Some lime is added from a lime feeder (6) as the material is transported to a pan mixer (8). During transport a rotavator (30) acts on the cohesive material so that finely divided material enters the mixing means (8). Further powder ingredients can be added to the components in the pan mixer (8) by means of a powder ingredient supply system (10).

Abstract: The invention relates to a mixing apparatus wherein raw material may be crushed to fine particles of desirous size to be mixed uniformally by multi-layed mixing blocks.

Abstract: An arithmetic unit detects difference &agr; (=X−Y) between a sound source arrival azimuth X° of a sound wave, which is transmitted from a sound source buoy and is directly received in a wave receiving buoy, to a reference axis of the wave receiving buoy, and a target arrival azimuth Y° of a reflective sound, which is reflected by a target, to the reference axis of the wave receiving buoy. The arithmetic unit detects an azimuth angle &bgr; of the sound source buoy on the basis of position information (latitude and longitude) of the sound source buoy and wave receiving buoy that is obtained by using GPS. Then, the arithmetic unit detects the azimuth (target azimuth) of the target to a magnetic north azimuth by the operation of (&bgr;−&agr;).

Abstract: Although normal microphones are very cheap, their range is usually limited up to around 10 KHz and is typically not free from various distortions. Other microphones that can reach 20 KHz or close to it typically cost tens or hundreds of dollars and still have various limitations, and higher-end microphones, for example of the types needed for Live Music performance or for the Mass media broadcasting, such as for example Radio or TV, are typically much more expensive and can cost even thousands of dollars. The main reason for these limitations is the fact that normal Microphones use a membrane, which is a mechanical element, and therefore they are limited by the mechanical qualities of the membrane. The present invention solves this problem by using a high quality Membrane-less Microphone capable of functioning in a very wide range of frequencies without distortions, which can be at the same time very compact and much cheaper than the state-of-the-art high-end microphones.

Abstract: An object is to provide an electronic device and a method of assembling electronic devices, in which a wiring member can be prevented from twisting and the reliability and efficiency of work can be improved. A twist protection function is provided to a wiring member, which is connected to a curved liquid crystal display panel at one end, and folded to be received in a casing. Such a twist protection function can be fulfilled by forming a connector portion of a circuit block into a roughly V-like shape, to which the wiring member is connected with bending in roughly V-like shape, or by thermally deforming the wiring member on the side of the curved liquid crystal display panel.

Abstract: Disclosed is an analogue chronograph comprising a digital display. The digital display contains an hour and/or minute indicator using numbers. The latter are arranged on individual circular tracks and under a viewing window, form the hour and/or minute indicator in a digital manner. The minute indicator, in particular, can be sub-divided into decimal and unit positions. The chronograph enables the elapsed time to be easily read, even when subjected to strong vibrations, or when the wearer of the chronograph can only glance at the face. The hour indicator has, in addition to numbers 0 to e.g. 9, a symbol similar to a flag, in order to indicate that the limit of the validity range of the time measurement has been reached.

Abstract: A multi mode alert timer having a timer display, switches for start stop and reset functions and audible, visible, and tactile alert signal selection and a housing where a user may select a timer alert signal including the individual alert signals or any combination thereof.

Abstract: An information storage device having a uniaxial tracking mechanism as a pickup which can perform a stable track pull-in operation is provided. A deceleration pulse amplitude a supplied to a tracking actuator is determined from a linear function á=K(V−V0) of a detected movement velocity of a beam in the vicinity of a target track. The deceleration pulse amplitude is divided into two, and is supplied to the tracking actuator on two different occasions.

Abstract: A record carrier (1) is described which has a servo track (4) indicating an information track (9) intended for recording information blocks, which servo track (4) has a variation of a physical parameter, a so called wobble. The wobble is modulated for encoding record carrier information, such as addresses. The servo track is subdivided in modulated parts in which the frequency and/or phase of the variation deviates from the wobble frequency, and non-modulated parts. The slope of the wobble is substantially continuous at transitions between the modulated and non-modulated parts by using wobbles (25,26,27,28) starting at the maxima or minima of the wobble in the first part of the modulated parts.

Abstract: An information recording medium wherein an optically detectable information recording medium is comprised of at least a substrate, a recording layer, and a resin layer. The information recording medium has surface roughness R &sgr; on the surface of the recording layer, which is in contact with the resin layer, under 5 nm. The information recording medium controls the reproduction signal noise, enables highly densified recording.

Abstract: A tracking servo apparatus is provided which is capable of performing correct operations even when imbalance occurs in outputs from a multi-output photodetector while an optical disk is in an unrecorded state.

Abstract: A disk apparatus according to one aspect of this invention comprises a photodetection unit configured to divisionally detect light reflected by the disk as a plurality of photodetection signals, and a tracking error signal generation unit configured to generate a tracking error signal on the basis of a phase difference between the plurality of photodetection signals detected by the photodetection unit, wherein the tracking error signal generation unit includes an equalization unit configured to equalize waveforms of the plurality of photodetection signals detected by the photodetection unit, and the equalization unit has frequency-gain characteristics that obtain a gain of not less than 15 dB at a frequency corresponding to a shortest pit or mark.