Abstract: A computer system incorporating capabilities for displaying the audio disk track number when the computer system is playing an audio disk. The computer system determines if a disk is present in the disk drive. If a disk is present, the computer system determines if an audio disk is present in the disk drive. If so, the computer system then monitors the disk drive. When the audio disk is played by the disk drive, the computer system displays the audio disk track number. The computer system then periodically polls the disk drive to update the audio disk track number. The computer system displays a battery gauge status when the audio disk track number is not being displayed. The status display is visible when the portable computer is in either an open or closed state.

Abstract: A DMA controller has both a receiving portion and a sending portion and may be used in a modem or other data transmission context. The DMA controller is intended to provide to or receive from data samples on a bus that may or may not be available. For the case when the bus is available, samples of data are either sent to or received from proper memory locations. When the bus is not available, the number of the samples that are missed due to the bus not being available is stored. This count is then used to ensure that the samples that are provided or received when the bus becomes available are stored in or read from the proper location to provide the samples at the proper time. The locations in which the samples were lost are provided with predetermined values.

Abstract: An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential input/output requests of the host are separated through a distribution processing to a plurality of paths, they are recognized on the device controller side and a countermeasure is taken. In the case in which a path from the host to the device controller is caused to be redundant into an operation system and a standby system, a path confirmation command is issued to the device drivers of a standby system path in order to confirm that the standby system path is normally operated or not.

Abstract: An apparatus, method and program product for use with a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by said processor for storing data, one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation, and a summary register for registering I/O requests by any one or more of said devices. The apparatus includes a dispatcher for polling said summary register to determine if an I/O request is outstanding. A program in the dispatcher calculates a delay value responsive to the workload of the processor in handling I/O requests. An adapter between the device and the processor drives an interrupt of the processor if the calculated time delay is exceeded between completing I/O requests.

Abstract: An apparatus for storing data of transactions includes a memory having a plurality of queues having locations where the data is stored, and shared memory. Each queue of the plurality of queues has a minimum threshold of the memory which the queue is guaranteed to have for use which no other queue of the plurality of queues can use, and a maximum threshold of the memory which the queue can use, when the maximum threshold is greater than the minimum threshold. The apparatus includes an admitting mechanism for admitting the data to the locations in the memory. The admitting mechanism having a first block of logic which is used to calculate the minimum threshold and the maximum threshold for each queue, and a single centralized block of logic to contain calculations for determining whether or not the shared memory can support a transaction. The first block of logic and the centralized block of logic independent of each other.

Abstract: The invention provides a data output control apparatus which is suitable for allowing detailed information on a network to be readily obtained. A data output control terminal selects one of printing apparatuses corresponding to a data-format-conversion terminal which allows conversion of data associated with a data print request; outputs the data associated with the data print request to the data-format-conversion terminal allowing conversion of the data and corresponding to the printing apparatus; by the data-format-conversion terminal, converts the data associated with the data print request into data which can be printed by the printing apparatus; and outputs the converted data to the printing apparatus. One or more of data-format-conversion terminals is selected in accordance with the transmission load of the Internet, and data-format-conversion processes are executed by the data-format-conversion terminal.

Abstract: A system and method are disclosed for managing information storage among plural disk drives. In accordance with exemplary embodiments of the present invention, the system includes plural host interfaces and first and second elements. The first and second elements each comprise a set of disk drives for storing information. Each of the first and second elements is associated with an element frame. Each disk drive included in the first element is connected to a different one of the plural host interfaces during the element frame of the first element. The system includes a switch controller, configurable by at least one of the plural host interfaces, for selecting among the first and second elements, and for directing information from a first one of the plural host interfaces to a selected disk drive within the first element. The system also includes a frame controller for controlling a duration of each element frame.

Abstract: A universal serial bus (USB) connector connecting structure for a multi-function device comprises a shell, a memory unit installed in said shell, and a universal serial bus, installed at one side of said shell, electrically contacted to said memory unit. Said universal serial bus (USB) is electrically contacted to and embedded on a sliding mechanism which is settled on a built-in fixed bed at one inner side of said shell, whereby said universal serial bus (USB) can be slide out from and stored in said shell by the means of said sliding mechanism.

Abstract: A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.

Abstract: Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.

Abstract: A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed.

Abstract: In one embodiment of the invention, an embedded controller receives an interrupt command and a query number from a system management interrupt (SMI) handler. The embedded controller generates a system control interrupt (SCI) in response to the interrupt command. A driver that receives the SCI issues a query command to the embedded controller. A routine associated with the query number is invoked in response to the query command.

Abstract: A method for achieving low overhead for operating system (“OS”) interrupts is described. In a preferred embodiment, when an interrupt occurs, a lightweight interrupt handler is used to acknowledge that the interrupt occurred, prevent the CPU and the OS from fully servicing the interrupt until a designated future time, set a CPU flag indicating that the interrupt has been received, and return from the lightweight interrupt handler. In this manner, the interrupt is partially acknowledged by the CPU and the OS, but the driver that caused the interrupt is still awaiting service. To achieve low latency, a heavyweight (“non-deferrable”) time-based interrupt that flushes all deferred interrupts is scheduled to occur within a specified time. At a later time, when drivers would normally be polled for work, the CPU flag is checked to see if there is interrupt work.

Abstract: A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.

Abstract: Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.

Abstract: A crossbar structure for use in a multi-processor computer system to connect a plurality of processors to at least one shared resource. The crossbar structure comprises for each processor, a storage location for receiving from a respective processor a memory address of a lock control structure associated with the shared resource. When the processor needs to acquire a lock thereto, the crossbar structure, on behalf of the processor, performs memory operations on the lock control structure at the address specified in the storage location in order to acquire the lock on behalf of the processor.

Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.

Abstract: A microprocessor system is provided that includes a first memory bank having a first base address and a second memory bank having a second base address. A memory controller is adapted to register the first and second base addresses. A swap command is adapted to instruct the memory controller to swap the first and second base addresses. A microprocessor issues the swap command. The memory controller includes a first base address register adapted to register the first base address and a second base address register adapted to register the second base address. A command register is adapted to register the swap command. In one embodiment, the first memory bank is a DRAM bank and the second memory bank is a ROM bank. The swap command instructs the memory controller to swap the first and second base addresses before temporary storage is established in the DRAM bank.

Abstract: A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an inoperable memory location and moving a memory address corresponding to the inoperable memory location to a first position in a list of available memory addresses. The method further includes the steps of incrementing an address pointer to a second position in the list of available addresses indicating a next available memory address in the list of available addresses, wherein said step of incrementing an address pointer to a second position operates to remove the memory address stored in the first position from the list of available memory addresses.

Abstract: The invention provides a flash memory integrated circuit device that is connectable to a computer via a universal serial bus. The universal serial bus (USB) has become a standard serial interface, which allows data to be stored in and read from an external memory device at high speed. Therefore, it is advantageous to combine the benefits of a flash memory device with the speed of the universal serial bus. In addition, by designing the flash memory device with a USB interface, the flash memory device appears as a standard USB storage device, which permits the host and flash memory device to connect and interact with ease.

Abstract: A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.

Abstract: In one embodiment of the invention, a disk storage accessing system for enabling a plurality of computers to share and access a plurality of disk storage comprises a plurality of computers that refer to the disk storage. Each of the computers includes a counting module for counting a frequency of access to each of the disk storage, and a module for receiving an access path change command to change access paths for the computer to access a different disk storage according to the command.

Abstract: A read-on-arrival scheme for reading data stored on a track of a data storage disc is disclosed. The track is divided into a plurality of sequentially arranged data sectors. Each data sector stores a block of data. A host computer issues a read command requesting retrieval of a segment of data blocks stored on a plurality of the data sectors. The segment may include a target data segment as well as a pre-fetch and post-fetch data segment. The read command specifies a target sector that a transducer is to initially access on the track. Upon receipt of the read command, components of a disc drive move the transducer to the track for access of the segment requested in the command. The disc drive components enable the transfer of data regardless of whether the transducer first accesses a sector located in sequential order prior to or following the target sector.

Abstract: Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first memory controller and a first cache coupled to the first memory controller, the first memory controller including first interface for coupling with second auxiliary processor including second memory controller and associated second cache and second interface for coupling with first auxiliary processor, first memory controller including logic for treating the caches as single memory; a bus coupling first primary processor and first auxiliary processor; and interconnection channel separate from the bus coupling first interface of first memory controlled and second interface of second memory controller. Interconnection may be an out-of-band channel permitting device-to-device sharing of associated cache memories without requiring data transfer over the bus. Method and computer program product are also provided.

Abstract: A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. User memory may pass through memory in a single hop by combining parity generation with FIFO buffering in the read and write user data paths. Independent memory channels may be controlled to level the load providing high memory bandwidth.

Abstract: A cache system and method in accordance with the invention includes a cache near the target devices and another cache at the requesting host side so that the data traffic across the computer network is reduced. A cache updating and invalidation method are described.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A system, computer program product and method for reallocating memory space for storing a partitioned cache. A server may be configured to receive requests to access a particular logical drive. One or more logical drives may be coupled to an adapter. A plurality of adapters may be coupled to the server. Each logical drive may be associated with one or more stacks where each stack may comprise one or more cache entries for storing information. The one or more stacks associated with a logical drive may be logically grouped into a logically grouped stack associated with that logical drive. Each of the logically grouped stacks of the one or more logical drives coupled to an adapter may be logically grouped into a logically grouped stack associated with that adapter. By logically grouping stacks, memory supporting a partitioned cache may adaptively be reallocated in response to multiple criteria thereby improving the performance of the cache.

Abstract: A system and method designed to reduce network congestion. In one aspect, a system according to the invention includes a server and two or more clients. Each client has software that runs on the client. The software requires data that is stored at the server. Advantageously, the software maintains a cache for storing the required data after the data is retrieved by the software from the server. Once the required data is in a cache, the software need not retrieve the required data from the server; the software can retrieve the required data from the software's cache. To ensure that the data that is stored in the cache does not become stale and to avoid network overload, the software updates its cache at a random point in time.

Abstract: A dual-cache array controller for a hard-drive based storage system includes software for identifying and addressing errors made in user handling of the cache boards. Controller firmware is programmed to determine whether or not there is any unflushed data in a cache board, to identify a used cache board, and to detect whether or not the cache board belongs to the controller in use or to another controller. Once a problem is identified, the controller is further programmed to issue an appropriate error message and to take corrective action, such as locking up the system until the correct cache board changes are made.

Abstract: A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.

Abstract: A system/method of enhanced backplane messaging among a plurality of computer boards communicating over a common bus uses a set of pre-allocated buffers on each computer board to receive messages from other computer boards. Each sending computer board is represented on each remote computer board by a descriptor ring with pointers to pre-allocated buffers on that remote computer board. When a sending computer board has a message to deliver to a remote computer board, the sending computer board uses its DMA controller to transfer the message into the pre-allocated buffers on the remote computer board. The sending computer board also sends a mailbox interrupt to the remote computer board. The remote computer board interrupt handler searches its descriptor rings and manipulates a series of pointers to move messages from the descriptor rings to the intended receiving application(s). Pointer manipulation is also used to replenish the descriptor ring(s) with empty buffer(s).

Abstract: A method, system, and computer program product for testing enforcement of logical partitioning in a data processing system are provided. In one embodiment, a call to an interface routine of a logical partitioning enforcement software unit is generated and sent to the logical partitioning enforcement software unit. Generating a call to an interface routine may include, for example, pseudo-randomly selecting one of a valid interface routine and an invalid interface routine and generating a call to the selected interface routine. A reply is received from the logical partitioning enforcement software unit and compared with an anticipated reply. Responsive to a discrepancy between the reply and the anticipated reply, a user is notified of a problem, thus allowing the user to take appropriate actions to correct the problem.

Abstract: A combination of data processing systems that are connected to a common peripheral bus, such as a PCI bus. The processor(s) of each system or blade may communicate with the peripheral bus through an intermediate bus controller. The bus controller may include facilities, such as registers that define a starting address, suitable for defining a window in the blade's system memory that is available or visible to other processors (or masters) on the bus. One or more of the bus controllers may be configured to read information that uniquely identifies each system or blade. The bus controller may use this identification information to define the window in the blade's system memory that is visible to other processors. In an embodiment where each blade is connected to a PCI bus through a CompactPCI® connector, the identification information may be read from the geographic address (GA) pins on the system's J2 connector.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: A personal computer hard disk has disk media that comprises a primary portion and a backup portion; both portions are in the same hard disk housing. The backup portion is logically separate from the primary portion, and access to the logically separate backup portion is controlled by a backup access control mechanism. The backup access control mechanism may comprise a manually-actuable mechanism, such as a switch or a jumper, or it may comprise software provided in an ROM forming part of the internal memory of the hard disk.

Abstract: In a data storage system providing access to a production dataset and snapshot copies of the production dataset, a production meta bit map identifies blocks of storage that are invalid in the production dataset. If a block in the production dataset is invalid when a snapshot copy is being made, then there is no need to copy the block to storage for the snapshot before writing to the block. Moreover, if a block in the production dataset supporting a snapshot copy is dynamically invalidated, it may be kept in the production dataset until it is written to. For this purpose, a respective snapshot copy of the meta bit map is made and kept with each of the snapshot datasets, and the snapshot copies of the meta bit map are merged in order to indicate the blocks that are invalid for all of the snapshots.

Abstract: A Virtual Disk Storage (VDS) System for providing multiple virtual data storage devices for use in a computer system which contains a central processing unit (CPU). The VDS System includes a memory system for storing information and a VDS Controller which is in communication with the memory system and the CPU. The VDS Controller partitions the memory system into multiple virtual data storage devices, and then restricts the computer system from communicating with certain of these virtual data storage devices. The VDS Controller thus selectively isolates at least one of the virtual data storage devices from communicating with the computer system, in order to prevent corruption of information stored in at least one virtual data storage device.

Abstract: A system and method for using memory mapped I/O (MMIO) to manage system devices is provided. A parent device in the ACPI namespace uses (MMIO) to identify the memory addresses of its children devices. An existing, but unused, construct of ACPI is used to pass the MMIO information through the operating system (OS) to the device drivers, enabling memory to be reserved by a device, and also remain hidden to the OS. The vendor defined resource data type for long information, also known as the “vendor-long” descriptor, is used to pass the appropriate information through the OS.

Abstract: A behavioral memory mechanism for a data processing system is disclosed. The data processing system includes a processor, a real memory, a behavioral address generator, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The behavioral address generator generates a behavioral virtual memory address associated with the behavioral virtual memory region. The address translator translates the behavioral virtual memory address to a real address associated with the real memory.

Abstract: In a data driven information processor, an operation apparatus includes a data select unit and a flag select unit selecting information according to the value of flag data in an input data packet. The data select unit selects the processed result for each data in the input data packet or the data itself. The flag select unit selects the flag data set with a value according to the processed result or the flag data of the input data packet. The selected information is stored in the input data packet, which is output to a program storage unit. Accordingly, the processed result can be obtained for certain data selected out of a plurality of data in the data packet to be reflected in the subsequent operation process without dividing the data packets.

Abstract: A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.

Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.

Abstract: A processor is disclosed having a fetch unit that initiating interrupt service routines in redundant, unsynchronized threads. A counter is provided to track the difference between leading and trailing threads in terms of the number of instructions committed by the instruction execution circuitry. When the processor receives an external interrupt signal, the instruction fetch unit stalls the leading thread until the counter indicates that the threads are synchronized, and then simultaneously initiates an interrupt service routine in each of the threads. In a second embodiment similar to the first, the instruction fetch unit does not stall the leading thread, but rather, immediately initiates the interrupt service routine in the leading thread, and copies the difference to an interrupt counter. When the counter reaches zero, the fetch unit initiates the interrupt service routine in the trailing thread.

Abstract: A control component for controlling the booting up of a complex computer system is described. The control component is configured such that it carries out its task irrespective of changes to the architecture/topology of the computer system. This task is carried out in that the control component controls the booting up of the system on the basis of data that are taken exclusively from a system database.

Abstract: A method to provide hierarchical reset capabilities for a configurable system on a chip is disclosed. The method includes determining a plurality of reset functions, and establishing a reset hierarchy among the plurality of reset functions.

Abstract: This invention generally relates to a method and apparatus for securing data contents stored in a non-volatile memory. More specifically, data contents to be stored a flash memory are first partitioned into block based data and rotated such that the addresses are scrambled. During a read operation, a random sequence generated through a random number generator causes contents of the retrieved data to also include original and extra (dummy) data. Through filtering and reverse rotation, original data contents are recovered. Accordingly, data contents in the flash memory are protected against unauthorized access, revision, or modification.

Abstract: A set of microprocessors may be set to a common mode in which the microprocessors utilize features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix to be applied to each of the microprocessors based on this common mode. Firmware or software can detect whether microprocessors are set to run in different modes in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a value to a configuration register associated with each microprocessor. If features are mixed, a different value can be written which tells each microprocessor to revert to a common mode of operation for that family of microprocessors. A common set of microcode patches may be downloaded to the microprocessors. Alternatively, the various microprocessors may also be instructed to run in a particular mode that emulates a particular stepping.