Abstract: A system and method for attaching multiple electrical components to a heat sink is disclosed. The apparatus includes a pair of spacers for each component. The spacers define a uniform distance between a circuit board and a base of a heat sink. Each spacer is secured to the circuit board and determines a distance from a base of the component to the circuit board. The heat sink is attached to the assembly by a plurality of threaded fasteners that extend through the circuit board, through a center space of the spacers and into threaded recesses of the heat sink.

Abstract: An adjustable circuit sled module for a mass storage device has a housing, a mass storage device, a circuit board, a cover and spacers. The spacers position the mass storage device to align the power and data interface ports of the mass storage device with corresponding power and data interface connectors of the circuit board. The resulting sled module can be adjusted to accommodate a variety of brands and sizes of mass storage devices.

Abstract: A bracket assembly includes a bracket which readily and easily couples with a printed circuit board. The bracket includes at least one tab assembly foldably attached with a support flange for supporting the printed circuit board. The bracket also includes an outer flange which is coupled with the computer chassis. Alignment apertures on the support flange and the printed circuit board facilitate the alignment of the printed circuit board, and allow for rework of the printed circuit board. Each tab assembly is adapted to frictionally engage with corresponding features on the printed circuit board.

Abstract: A first driver IC is mounted in the area which includes one side of the panel substrate on an electro-optical panel, and the edge portion of the film base material on which a second driver IC is mounted is bonded to the vicinity of the one side of the above-mentioned panel substrate. Also, driver-controlling electronic components which each provides control signals to the first and second driver ICs are mounted on the same surface as the second driver IC in the film base material.

Abstract: An electronic system fire containment and suppression apparatus that can include but is not limited to at least one PCB-localized fire containment and suppression structure which can include at least one printed circuit board (PCB) guide rail having at least one intumescent-paint-coated aperture. A communication device, such as a network router or switch, wherein the electronic system fire containment and suppression apparatus is deployed. A method of deploying the electronic system fire containment and suppression apparatus in a communication device. A method of manufacturing the electronic system fire containment and suppression apparatus.

Abstract: An earphone jack is fixed on a printed circuit board by soldering as well as a first holding rib and a second holding rib for holding in the horizontal direction and a third holding rib for holding in the perpendicular direction with respect to the printed circuit board are provided on a shield case. The shield case is held in the perpendicular direction with respect to the printed circuit board by a fourth holding rib provided on the case.

Abstract: An electronic circuit unit for use in an electronic equipment cabinet. The electronic circuit unit has first and second opposite main walls including EMI absorbing material and a motherboard frame between the main walls, the motherboard frame including a plurality of wall segments also including EMI absorbing material. A motherboard is mounted in the motherboard frame by a first locating retainer. The first locating retainer positions the motherboard such that it resides between the main walls of the electronic circuit unit. A signal-processing module forming at least a portion of the first main wall is removably mounted to the motherboard frame by a second locating retainer. The signal-processing module connects with the motherboard through an electrical connector having mating parts. The first and the second locating retainers are positioned relative to one another to allow the mating parts to align and mate when the signal processing module is fastened to said motherboard frame.

Abstract: The invention relates to a high-voltage transformer arrangement which converts to the direct current voltage from a direct current voltage source (2) into a direct current voltage output signal (Vout), using a current inverter (4) and a transformer (8) to an output rectifier (12), which is connected downstream, and a filter (14). The transformer (8) has a transformer core comprising several interruption points in the magnetic path, at which insulator sections are located. The individual core sections are controlled by potential. The separate transformer core sections together with their corresponding windings form a primary system and a secondary system, which is separated from said primary system both spatially and in terms of potential, having a relatively high stray inductance.

Abstract: A complex resonance type switching converter provided with a self-excited voltage resonance type converter has a conduction controlling device Q2 connected in series with a control winding Nc of a drive transformer CDT in which a detecting winding NA, a driving winding NB of a self-oscillation driving circuit, and the control winding Nc are wound on an identical core. An amount of current conducted in the conduction controlling device Q2 is varied, whereby a level of a base current flowing from the self-oscillation driving circuit to a base of a switching device Q1 is changed and switching frequency of the switching device Q1 is variably controlled. Thereby a conduction angle and the switching frequency of the switching device are changed simultaneously, and consequently constant-voltage control is effected on a direct-current output on the secondary side of the converter. Use of such a drive transformer CDT makes it possible to prevent variations of the self-oscillation driving circuit and reduce size.

Abstract: A drive circuit for a synchronous rectifier of a switch mode power converter is disclosed. The switch mode power converter may include a main power transformer and a primary switch for cyclically coupling the main power transformer to an input source. The drive circuit may comprise a turn-on switch, a turn-off switch, a charge pump and a pulse transformer. The charge pump may be coupled to a secondary winding of the main power transformer. The turn-on switch is for turning on the synchronous rectifier and may be coupled to the charge pump. The pulse transformer may include primary and secondary windings, wherein the primary winding is responsive to a control signal supplied to the primary switch. The turn-off switch is for turning off the synchronous rectifier and may include a control terminal coupled to the secondary winding of the pulse transformer.

Abstract: A progammable power supply for providing a regulated DC output power is disclosed. The power supply provides the output power to any one of a plurality of electronic devices adapted for receiving the output power at an operational voltage or an operational current. The power supply receives a programming signal to maintain the output power at the operational voltage or operational current associated with a particular selected electronic device. Accordingly, by varying the programming signal, the power supply can be programmed to provide output power to any one of several electronic devices having differing input power requirements.

Abstract: A system for controlling multiple vehicle includes a twelve volt (12V)/forty-two volt (42V) battery power distribution system that provides direct current. The system converts single phase alternating current to multiple phase alternating current to simultaneously power multiple vehicle systems. A single pulse width modulation generator converts the direct current from the 12V/42V battery power distribution system to alternating current. This provides one power supply path of alternating current, which has a first phase. A splitter device splits the one power supply path of alternating current into three power paths. A lead/lag circuit is used to shift the alternating current of the second path to a second phase different than the first phase of the first power supply path. A second lead/lag circuit for shifts the alternating current of the third path to a third phase different than the first phase or the second phase. This creates a three-phase alternating current power from a single direct current source.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.

Abstract: A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.

Abstract: A memory device includes a number of memory cells 112 arranged in rows and columns. Each memory cell 112 is coupled to a wordline 120 and at least one bitline 126 and/or 128. Each bitline 126 (128) is coupled to a sense amplifier 130, which is enabled by a sense amplifier enable circuit 134. The sense amplifier enable circuit 134 is coupled to the dummy bitline. This circuit provides the enable signal at a time based on an amount of leakage voltage determined from the dummy bitline.

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.

Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

Abstract: The present invention is a method of data storage using a phase-change memory clement operating within its amorphous phase. The element stores at least one bit of data upon the application of a pulse that resets the element to one of at least a first resistance state and a second resistance state. Since the threshold voltage of a memory element varies linearly with its programmed resistance, the stored data can be read by the application of one or more discriminating voltages to the element. The current flowing through the element is limited to prevent a phase change when an applied discriminating voltage is greater than the threshold voltage. When the applied discriminating voltage is less than the threshold voltage, current flowing through the memory element is not limited. Based upon these current outputs, the resistance state of the element is determined.

Abstract: A highly reliable magnetic memory exhibits enhanced data-holding stability at high storage density in a storage layer of a magnetoresistive effect element used for memory cells. A magnetic memory includes a memory cell array having first wirings, second wirings intersecting the first wirings and memory cells each provided at an intersection area of the corresponding first and second wirings. Each memory cell is selected when the corresponding first and second wirings are selected.

Abstract: A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

Abstract: A sector structure of a flash memory device minimizes a layout area in a chip without deteriorating a high-speed operation. The sector structure of the flash memory device includes a plurality of sectors, each sector including memory cell transistors in a cell array block sharing a common bulk region with transistors in a column decoder block.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: Methods and apparatus for storing erase counts in a non-volatile memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a data structure in a non-volatile memory includes a first indicator that provides an indication of a number of times a first block of a plurality of blocks in a non-volatile memory has been erased. The data structure also includes a header that is arranged to contain information relating to the blocks in the non-volatile memory.

Abstract: A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

Abstract: A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.

Abstract: A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

Abstract: In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.

Abstract: Main memory units are each composed of an even number of sub memory units having different addresses. The sub memory units have memory cells, bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas of the main memory units are formed in mirror symmetry. Consequently, the sequence of the data terminal numbers of the bit lines in the case of relief where a redundancy memory unit is used can be easily made the same as in the case of non-relief where the redundancy memory unit is not used. As a result, at the time of defect analysis, the sequence of the bit lines need not be taken into account regardless of whether the product is a relief product or non-relief product. This allows a reduction in the time necessary for defect analysis.

Abstract: According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

Abstract: A semiconductor memory device includes a plurality of memory cells each capable of storing and programming N-level data; a reference cell storing a reference level used when reading a data level stored in the memory cells; a counter circuit counting number of times of reading of the reference cell; a check means for determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted reaches a specified value; and a correction means for, if the check means determines that the reference level is out of the range, correcting the reference level to fall within the range in accordance with a master reference cell. With this constitution, it is possible to provide the semiconductor memory device capable of efficiently correcting the state of the reference cell, preventing the deterioration of the reference cell due to disturbance or the like, and highly accurately maintaining the level of the reference cell.

Abstract: A device and method for independent control of SDRAM memory in an SDRAM memory module. The device includes an in-line controller (ILC) coupled to receive indications of memory controller interrupt events. The ILC is coupled with the SDRAM memory, possibly through a registered buffer, in such a way that when an indication of a memory controller interrupt event is received, the ILC issues appropriate instructions to the SDRAM memory and prevents any spurious memory controller signals from being transmitted along the control bus. A memory module incorporating an ILC in communication with a memory controller and an SDRAM memory device or bank of such devices. Ultimately, a number of ILCs may be used, each controlling an individual SDRAM bank or discreet memory device.

Abstract: There is disclosed an improved ultrasonic hologram or other ultrasonic imaging process that accurately forms phase and amplitude information of the hologram in a manner that renders the unit relatively insensitive to environment vibrations, and provides long maintenance free functioning lifetime. Specifically, there is disclosed an improved ultrasonic hologram detector component that forms an ultrasonic hologram on the surface of a detection deformable detector material, resulting from the deformation of the surface. The surface deformation is due to the reflection of an ultrasound (ultrasonic) energy profile of the combination of an “object wave” that passes through an object and that of a “reference wave” that is directed to the surface at an off axis angle from the “object wave”.

Abstract: An apparatus for ultrasonically detecting an edge of a web, includes a ultrasonic-wave transmitter transmitting ultrasonic-wave pulse train, a ultrasonic-wave receiver receiving the ultrasonic-wave pulse train and converting the received ultrasonic-wave pulse train into electric signals, the web being fed between the ultrasonic-wave transmitter and receiver, a rectifying circuit for rectifying the electric signals, a low-pass filter circuit for smoothing output signals transmitted from the rectifying circuit, a first sample-holding circuit for sampling an output signal transmitted from the low-pass filter circuit, at first timing, a second sample-holding circuit for sampling an output signal transmitted from the low-pass filter circuit, at second timing later than the first timing, a third sample-holding circuit for sampling an output signal transmitted from the first sample-holding circuit, at the second timing, and a differentially amplifying circuit for calculating a difference between output signals trans

Abstract: An improved acoustic window for an acoustic waveform passage having a generally uniform transmission loss at an angle of incidence of between −40° and +40°. The composition is formed from at least one core layer and at least two septa, with the core layer being a material having a generally low-acoustic-impedance, a static shear modulus between about 1.0 psi (0.007 MPa) and about 15,000 psi (103 MPa), a transverse (or through-thickness) sound velocity for the acoustic waveform of between about 700 and about 2200 meters per second, a transverse acoustic impedance of less than or equal to 4×106 kilograms per square meter-second, and a shear loss factor of greater than 0.02, the septa being composed of at least one ply of a material, preferably a graphite fiber reinforced epoxy composition, having a transverse acoustic impedance of less than 60×106 kg/m2-sec, a tensile modulus of more than 0.5×106 psi, a thickness of less than 0.

Abstract: The present invention provides a system for, and method of determining an azimuth of a seismic energy source. In one embodiment, the system includes a directional assembly having a mount configured to be coupled to a seismic energy source, a rotatable mass assembly coupled to the mount, a compass rose coupled to one of the mount or the rotatable mass assembly and a direction reference coupled to the other of the mount or the rotatable mass assembly. The compass rose is registered with the direction reference to provide a direction orientation of the rotatable mass assembly with respect to the mount.

Abstract: An electronic device capable of counting down to an integral time point has an integral time point selector for setting an integral time point. A timer serves for recording the current time. A synchronous calculating unit serves for reading the integral time point from the integral time point selector and reading the current time from the timer. The time interval from the current time to the integral time point is calculated as a counting down time period. A counter serves for reading the counting down time interval from the synchronous calculating unit and starting to count down.

Abstract: A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i.e. it is programmed. Over time, the charge storage element then loses the charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell measures an elapsed time period without a continuous power source. One type of time cell is an analog time cell that may have a form similar to a non-volatile memory cell, particularly a floating gate field effect transistor (FGFET). The time cell may have an expanded floating gate for storing an electrostatic charge.

Abstract: A display face is created by cutting or slicing a bowling ball wherein a portion of a weight block or core center of the bowling ball is displayed. The weight block or core is different in different balls. Accordingly, a slice of the bowling ball with the weight block therein creates a novel or unique appearance on the display face. The unique display face may be provided with clock hands and indicia representing clock numerals mounted in front of the bowling ball slice. Alternatively, the bowling ball slice may be utilized as a plaque on which an award plate is mounted or on which indicia are engraved. The display face may not contain a portion of the weight block or center core where slices taken from the periphery of the bowling ball or taken from a bowling ball without a weight block or center core. Additionally, the bowling ball may be provided with a fragrance to create a scent, and this fragrance a scent may also be associated with the display face.

Abstract: A piece of media, apparatus and method are provided wherein the piece of media may store the audio data as well as equalizer settings that permit the audio data to be equalized. In one embodiment, the piece of media stores equalized audio data and the equalizer settings. In accordance with the invention, in one embodiment, the equalizer-effect piece of media permits the audio data on the piece of media to be equalized even when the audio data player does not include an equalizer. In another embodiment, the equalizer-effect piece of media includes raw audio data and equalizer settings and permits an external equalizer to play equalized audio data without needing to set the equalizer. In a preferred embodiment, the piece of media may be compact disk.

Abstract: An optical head including a light source for emitting luminous energy recordable on a recording medium, a heat radiating section, in contact with the light source, for radiating heat which accompanies the light emission thereof, and a resin-made bench for mounting and fixing the aforementioned elements, or an optical head having a light source for generating luminous energy required for recording on a disk-shaped information recording medium or reproducing information recorded on the disk-shaped information recording medium; a radiator plate, in contact with the light source either directly or indirectly, for guiding heat which accompanies the emission of light by the light source; an objective lens for focusing light on the disk-shaped information recording medium; an objective lens drive unit for driving the objective lens in the focal and radial direction of the medium; a light receiving element for receiving light reflected from the medium; a sheet-shaped flexible circuit for feeding power to the light so

Abstract: Both of one audio information and another audio information are recorded on a same information record medium. An audio information reproducing apparatus is provided with: a detecting device for detecting said one audio information and said another audio information from the information record medium and also detecting a time period required for one beat of the detected another audio information; and an accumulating device for accumulating said one audio information detected from the information record medium to thereby continue reproducing and outputting said one audio information through the accumulating device. The audio information reproducing apparatus is also provided with a controlling device for controlling the detecting device to detect said another audio information and the time period required for one beat, within a time duration that the accumulated one audio information is being reproduced and outputted through the accumulating device.

Abstract: In a data reproducing apparatus, a monitor edge sample value is generated based on a second sample value at a trailing edge of the reproduction signal and a change amount of the monitor edge sample value is generated as an offset amount in a first processing part. Then, the offset amount is supplied to a second processing part where the second sample value is obtained by sampling the reproduction signal at the trailing edge. Then, the second processing part restores data based on the reproduction signal and the offset amount.

Abstract: According to the present invention, in an optical disk apparatus constructed to supply signals for controlling a semiconductor laser drive circuit provided to an optical pickup from a signal processing circuit through a flexible cable, the semiconductor laser drive circuit is so constructed as to generate a drive current signal for the semiconductor laser on the basis of a binary signal and a clock signal which are supplied from the signal processing circuit through the flexible cable and the signal processing circuit is so constructed as to stop supplying the block signal to the semiconductor laser drive circuit through the flexible cable during reproduction of data, and to start supplying the clock signal to the semiconductor laser drive circuit before recording of data.

Abstract: An optical head which has a prism with an incident section, an internal reflective surface and an emergent surface, and an optical head device which employs the optical head. Light emitted from a light source is incident to the prism through the incident section, reflects at least once on the internal reflective surface and is converged in the vicinity of the emergent surface. Then, the light effuses through the emergent surface as near field light.

Abstract: A recording medium stores information that is reproducible utilizing near-field light. A phase shift arrangement layer is formed with alternately arranged phase shifter regions for shifting incident light by 180 degrees and transmission regions that are transparent to the incident light. A row of data marks is arranged above the phase shifter regions and transmission regions. As a result, the spread of near-field light due to incident light transmitted through the phase shifter regions and transmission regions is canceled, to provide a sharp distribution of near-field light over the data marks. light.