Abstract: A liquid crystal display panel including a thin film transistor array substrate structure including, a substrate, a gate line and a data line disposed on the substrate and insulated from each other by a gate insulating pattern, a thin film transistor provided at intersection of the gate and data lines, a protective film disposed to protect the thin film transistor, and a pad structure connected to a respective one of the gate line and data line, the pad structure including a transparent conductive film and a data metal layer; and a color filter array substrate structure joined with the thin film transistor array substrate structure, wherein the protective film is disposed within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure, and exposing either the data metal layer or the transparent conductive film along a side portion of the substrate.

Abstract: A method of manufacturing a semiconductor characterized in that, in polycrystallizing an amorphous silicon thin film formed on a substrate through an annealing process, the amorphous silicon thin film has a plane area of 1000 ?m2 or less. A thin-film transistor characterized by comprising an active silicon film which is formed, of a plurality of island-like regions arranged in parallel to each other, the island-like regions being formed of a polycrystal silicon thin film having a plane area of 1000 ?m2 or less. A method of manufacturing a thin-film transistor comprising the steps of: forming an amorphous silicon thin film on a substrate; processing the amorphous silicon thin film into a plurality of island-like regions having a plane area of 1000 ?m2 or less; polycrystallizing an amorphous silicon thin film that forms the island-like regions through an annealing process; and forming a thin-film transistor having at least one of the plurality of island-like regions as an active silicon layer.

Abstract: The invention provides a laminated dielectric layer for semiconductor devices formed by a combination of ZrO2 and a lanthanide oxide on a semiconductor substrate and methods of making the same. In certain methods, the ZrO2 is deposited by multiple cycles of reaction sequence atomic layer deposition (RS-ALD) that includes depositing a ZrI4 precursor onto the surface of the substrate in a first pulse followed by exposure to H2O/H2O2 in a second pulse, thereby forming a thin ZrO2 layer on the surface. After depositing the ZrO2 layer, the lanthanide oxide layer is deposited by electron beam evaporation. The composite laminate zirconium oxide/lanthanide oxide dielectric layer has a relatively high dielectric constant and can be formed in layers of nanometer dimensions. It is useful for a variety of semiconductor applications, particularly for DRAM gate dielectric layers and DRAM capacitors.

Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.

Abstract: A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode, a data line connected to the source electrode, and a lower data pad electrode connected to the data line. A semiconductor pattern is formed beneath the source/drain pattern. A transparent electrode pattern includes a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode. The thin film array substrate further includes a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed.

Abstract: A thin film transistor substrate for a display device includes a gate line; a gate insulating film disposed over the gate line; a data line disposed on the gate insulating film intersecting with the gate line to define a pixel area; a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a channel between the source electrode and the drain electrode; a protective film disposed covering the gate line, the data line, and the thin film transistor; a pixel electrode connected to the drain electrode of the thin film transistor; and a storage capacitor having a first upper storage electrode connected to the pixel electrode, and a second upper storage electrode connected to the first upper storage electrode on a side surface basis via a first contact hole passing through the protective film and the first upper storage electrode at an overlapping portion of the gate line and the first upper storage electrode.

Abstract: A thin film transistor (TFT) substrate is fabricated in three mask processes. In a first mask process, a gate line and a gate electrode are formed. In a second mask process, a data line, a source electrode, a drain electrode, a semiconductor layer, and a first upper storage electrode overlapping the gate line are formed from a gate insulating film, undoped and doped amorphous silicon layers, and a data metal layer. In a third mask process, a pixel hole is formed through protective and gate insulating films within and outside a pixel area, the first upper storage electrode is partially removed, a pixel electrode contacts a side of the drain electrode within the pixel hole at the pixel area, and a second upper storage electrode contacts a side of the first upper storage electrode in the pixel hole outside the pixel area.

Abstract: A liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate and a color filter array substrate. The TFT array substrate includes gate and data lines insulatively crossing each other to define a pixel area, a TFT provided at the crossing of the gate and data lines, a passivation film protecting the TFT, a pixel electrode partially overlapped by the TFT, a gate pad connected to the gate line, and a data pad connected to the data line. The gate line, the gate and data pads, and the pixel electrode include a transparent conductive material. A gate metal material is on the transparent conductive material where the TFT partially overlaps the pixel electrode. The passivation film over the gate and data pads is removed to expose the transparent conductive material included within the gate and data pads.

Abstract: A modular light emitting diode (LED) mounting configuration is provided including a light source module having a plurality of pre-packaged LEDs arranged in a serial array. The module is connected to a heat dissipating plate configured to mount to an electrical junction box. Thus, heat from the LEDs is conducted to the heat dissipating plate and to the junction box. A sensor is configured to detect environmental parameters and a driver is configured to illuminate the LEDs in response to the environmental parameters, thereby selectively configuring the LEDs to function in a wide variety of useful applications.

Abstract: Thin film for optical applications, light-emitting structure using the same and the fabrication method thereof are disclosed. The present invention provides a silica or silica-related thin film for optical applications in which silicon nanoclusters and rare earth elements are co-doped. The average size of the silicon nanoclusters is less than 3 nm and the concentration of the rare earth elements is less than 0.1 atomic %. The ratio of the rare earth element concentration to that of silicon nanoclusters is controlled to range from 1 to 10 in the thin film. The thin film emits light by exciting the rare earth elements through electron-hole recombinations in the silicon nanoclusters. According to the present invention, the conditions such as the size and concentration of the silicon nanoclusters, the concentration of the rare earth element, and their concentration ratio are specifically optimized to fabricate optical devices with better performance.

Abstract: The present invention provides a method and associated structure for forming an electrostatically-doped carbon nanotube device. The method includes providing a carbon nanotube having a first end and a second end. The method also includes disposing a first metal contact directly adjacent to the first end of the carbon nanotube, wherein the first metal contact is electrically coupled to the first end of the carbon nanotube, and disposing a second metal contact directly adjacent to the second end of the carbon nanotube, wherein the second metal contact is electrically coupled to the second end of the carbon nanotube.

Abstract: A light emitting diode having an adhesive layer and a reflective layer and a manufacturing method thereof featured by adhering together a light emitting diode stack and a substrate having a reflective metal layer by use of a transparent adhesive layer so that the light rays directed to the reflective metal layer can be reflected therefrom to improve the brightness of the light emitting diode.

Abstract: An LED chip package body includes an LED chip having a pad-installed surface, a plurality of pads installed on the pad-installed surface and a rear surface formed on an opposite side of the pad-installed surface. A light-reflecting coating is disposed on the pad-installed surface and has a plurality of exposed holes for exposure of the corresponding pads. A first insulative layer is formed on the light-reflecting coating and has a plurality of through holes communicating with the corresponding exposed holes. A second insulative layer is disposed on the rear surface and has a central through hole for exposure of a central portion of the rear surface. A lens is received in the central through hole. Each of a plurality of external connected conductive bodies is electrically connected to the corresponding pad and projects out of the corresponding through hole in the first insulative layer.

Abstract: Disclosed are a GaN-based semiconductor light emitting diode, in which transmittance of electrodes is improved and high-quality Ohmic contact is formed, and a method for manufacturing the same, thus improving luminance and driving voltage properties. The GaN-based semiconductor light emitting diode includes: a substrate on which a GaN-based semiconductor material is grown; a lower clad layer formed on the substrate, and made of a first conductive GaN semiconductor material; an active layer formed on a designated portion of the lower clad layer, and made of an undoped GaN semiconductor material; an upper clad layer formed on the active layer, and made of a second conductive GaN semiconductor material; and an alloy layer formed on the upper clad layer, and made of a hydrogen-storing alloy. The GaN-based semiconductor light emitting diode improves a luminance property and reduces Ohmic resistance, thus obtaining high-quality Ohmic contact.

Abstract: Disclosed herein is a wavelength converted light emitting apparatus comprising a substrate, a light emitting diode, and a phosphor layer. The substrate is formed at its upper surface with first and second conductive patterns. At a partial region of the first conductive pattern and at the second conductive pattern are formed first and second connection bumps, respectively. The light emitting diode has first and second surfaces opposite to each other, and a side surface. The first surface of the light emitting diode is formed with first and second electrodes. The light emitting diode is disposed at the upper surface of the substrate so that the first and second electrodes are connected to the first and second connection bumps, respectively. The phosphor layer is formed along the second surface and side surface of the light emitting diode by a certain thickness, thereby serving to convert a wavelength of light emitted from the light emitting diode.

Abstract: The light emitting device has a light emitting diode which is made of a nitride semiconductor and a phosphor which absorbs a part of lights emitted from the light emitting diode and emits different lights with wavelengths other than those of the absorbed lights. The phosphor is made of alkaline earth metal silicate fluorescent material activated with europium.

Abstract: A semiconductor package comprises a semiconductor chip, leads, and bonding wires wherein at least portions of the chip, bonding wires and leads are covered and protected with an electrically insulating fluorochemical material which is a cured product of a curable composition comprising (A) a polyfluorodialkenyl compound comprising —(CF(CF3)—CF2—O)— units and having alkenyl groups at both ends of its molecular chain, (B) an organohydrogenpolysiloxane having at least two Si—H groups, and (C) a platinum group metal catalyst.

Abstract: A light-emitting diode has a case having a concave portion, a reflection mirror obtained by forming metal on the concave portion, and a lead to one end of which a light-emitting element is attached. A cavity including the concave portion of the case is filled with an accelerated curing epoxy resin. The epoxy resin is cured so that the epoxy resin, the reflection mirror and the case are formed into a sandwich structure. With such a structure, a light-emitting diode free of wrinkles and cracks on the reflection mirror is provided. Further, at the time of handling or transportation, the reflection mirror is not damaged. Moreover, during reflow soldering, at the time of solder-mounting the light-emitting diode to a printed circuit board, thermal deformation, such as wrinkling and cracking of the reflection mirror is completely prevented.

Abstract: A LED manufacturing process includes multiple compounding potting procedures to form a fluorescent layer between a first resin layer and a second resin layer, keeping the chip and the electrode wire embedded with a part of the frame in the second resin layer and spaced from the fluorescent layer at a distance.

Abstract: Disclosed herein is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer on a substrate, an active layer formed on the n-type nitride semiconductor layer so that a portion of the n-type nitride semiconductor layer is exposed, a p-type nitride semiconductor layer formed on the active layer, a high-concentration dopant area on the p-type nitride semiconductor layer, a counter doping area on the high-concentration dopant areas, an n-side electrode formed on an exposed portion of the n-type nitride semiconductor layer, and a p-side electrode formed on the counter doping area. A satisfactory ohmic contact for the p-side electrode is provided by an ion implantation process and heat treatment.

Abstract: Provided are a nitride-based light emitting device and a method of manufacturing the same. The nitride-based light emitting device has a structure in which at least an n-cladding layer, an active layer, and a p-cladding layer are sequentially formed on a substrate. The light emitting device further includes an ohmic contact layer composed of a zinc (Zn)-containing oxide containing a p-type dopant formed on the p-cladding layer. The method of manufacturing the nitride-based light emitting device includes forming an ohmic contact layer composed of Zn-containing oxide containing a p-type dopant on the p-cladding layer, the ohmic contact layer being made and annealing the resultant structure. The nitride-based light emitting device and manufacturing method provide excellent I-V characteristics by improving ohmic contact with a p-cladding layer while significantly enhancing light emission efficiency of the device due to high light transmittance of a transparent electrode.

Abstract: A method for fabricating multiple channel heterostructures with high sheet carrier densities in each channel, while maintaining a low energy barrier for transfer of majority carriers between the channels. For a heterostructure where n-type conductivity is desired, n-type dopant impurities are placed at each heterointerface with negative polarization charge, equal in magnitude to the negative polarization charge. For a heterostructure where p-type conductivity is desired, p-type dopant impurities are placed at each heterointerface with positive polarization charge, equal in magnitude to the positive polarization charge. The heterointerfaces with dopant impurities can be graded in chemical composition, over a certain distance, while the dopant impurities are distributed along the graded distance. The heterointerfaces with dopant impurities can also be abrupt, in which case the dopant impurity is located in a sheet or thin layer at or near the heterointerface.

Abstract: A semiconductor avalanche photodiode (APD) with very high current gain utilizes a small vacuum or gas filled gap which is used as a region to accelerate electrons to high energies. The APD has an absorption layer, a gap, and a multiplication layer. The absorption layer is adapted to generate electron-hole pairs upon absorbing light. The APD is adapted to generate an electric field in the gap and at an interface between the absorption layer and the gap. The electric field extracts electrons from the absorption layer into the gap and accelerates the extracted electrons while in the gap. The multiplication layer is adapted so that said accelerated electrons impinge on and cause a flow of secondary electrons within the multiplication layer.

Abstract: The invention relates to an integrated circuit arrangement on the basis of III/V semiconductors, which comprises at least one active component (2) and a multilayer arrangement of wiring planes. A metallized layer comprising a metal contact (4) of the at least one active component (2) is configured as one of the lower wiring planes. In this manner, metallized layers that are conventionally only used for providing the metal contacts of the components, can be integrated into the wiring of the integrated circuit arrangement.

Abstract: A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), deposited on the substrate, an AlGaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded AlGaN layer deposited on the AlGaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded AlGaN layer to a top of the n-type doped graded AlGaN layer, and a cap layer, comprised of GaN or AlGaN with an Al mole fraction smaller than that of the AlGaN barrier layer, deposited on the n-type doped graded AlGaN layer.

Abstract: The present invention provides an anisotropic conductive film for testing an electronic component, which comprises a film substrate comprising an insulating resin and plural conductive paths insulated from each other and penetrating the film substrate in the thickness direction, preferably, an anisotropic conductive film wherein the plural conductive paths are disposed in a houndstooth check pattern and the distance between conductive paths between adjacent rows of conductive paths is smaller than the distance between conductive paths within a row of conductive paths. In another preferable embodiment, the insulating resin comprises a naphthalene skeleton epoxy resin crosslinked with a phenol resin and an acrylic rubber, and both ends of the plural conductive paths are exposed on both the front and the back surfaces of the film substrate.

Abstract: The object of the present invention is to provide a composite storage circuit capable of executing a writing operation and reading operation at high speed, and as the result of that, a semiconductor apparatus capable of realizing an instant-on function and an instant-off function is provided. The composite storage circuit is constituted of a volatile storage circuit and a non-volatile storage circuit connected in parallel, and the same information as storage information in the volatile storage circuit is stored in the non-volatile storage circuit. Moreover, as a power supply to the volatile storage circuit decreases, storage information in the volatile storage circuit is written in the non-volatile storage circuit. Further, after a power failure or a decreased power supply, storage information from the non-volatile storage circuit is returned to the volatile storage circuit upon restarting power feeding. Further, a semiconductor apparatus is constituted by having the composite storage circuit described above.

Abstract: A light emitting diode having an adhesive layer and a reflective layer and a manufacturing method thereof featured by adhering together a light emitting diode stack and a substrate having a reflective metal layer by use of a transparent adhesive layer so that the light rays directed to the reflective metal layer can be reflected therefrom to improve the brightness of the light emitting diode.

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.

Abstract: A method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is provided which comprises the steps of forming upon a semiconductor substrate (10) a field effect transistor structure comprising a gate oxide (12), a gate electrode (14) formed upon said gate oxide (12), a drain region (16) and a source region (18) which are formed within the semiconductor substrate (10) adjacent to the gate electrode (14), and depositing a fluorine in-situ doped insulating layer (28) covering the field effect transistor structure. The fluorine in-situ doped insulating layer (28) is provided for improving the transistor reliability.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.

Abstract: An aspect of the present invention provides a semiconductor device that includes a first transistor including a source region, a drain region provided in the same device region as the source region, and a loop-shaped gate electrode region, and a second transistor sharing, with the first transistor, the loop-shaped gate electrode region and the source region or the drain region.

Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23, 24).

Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

Abstract: Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the opposing sidewalls, where the second fins have respective exposed sidewalls protruding from the substrate. The second fins or the first fin can be removed to provide at least one fin for a multi fin FET.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: A memory includes an array of magnetic memory cells, each magnetic memory cell being adapted to store a bit of information, interconnects in communication with the magnetic memory cells, and conductors in communication with the magnetic memory cells and the interconnects, the conductors filling spaces between adjacent magnetic memory cells of the array.

Abstract: An exemplary thermally-assisted magnetic memory structure comprises a first conductor substantially surrounded by a cladding, a memory cell being thermally isolated from the first conductor by a thermally resistive region, and a second conductor electrically contacting the memory cell.

Abstract: A method of forming a one-transistor memory cell includes the steps of: forming a dielectric layer over a substrate having a pass-gate formed thereon; forming an opening in the dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate; forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and forming an electrode layer over the capacitor dielectric layer. A one-transistor memory cell is also disclosed. The one-transistor memory cell has a substrate having a pass-gate formed thereover. A dielectric layer is formed over the pass-gate and the substrate and has an opening exposing a portion of the substrate adjacent to the pass-gate. A capacitor dielectric layer is formed on sidewalls of the opening and on the exposed portion of the substrate. An electrode layer is formed on the capacitor dielectric layer.

Abstract: A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.

Abstract: A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity having a first conductivity type, at least a second doped polysilicon layer filled in the upper portion through a second dielectric film and doped with a second impurity different from the first impurity, the second impurity having the first conductivity type, and a buried strap layer provided on the second doped polysilicon layer and composed of the first doped polysilicon layer.

Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

Abstract: Integrated circuit ferroelectric memory devices are provided that include an integrated circuit transistor. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device further includes a plate line directly on the ferroelectric capacitor. Methods are also provided that include forming a ferroelectric capacitor on the integrated circuit transistor and forming a plate line directly on the ferroelectric capacitor.

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: A trench (12) of a semiconductor memory cell (1) has an insulation collar (44), which is open toward the substrate (42) on just one side (50). On the other side (52), the insulation collar (44, 47, 55) rises all the way up to the insulation cover (62). There is therefore no need for a shallow trench isolation. The contact (70) which is buried on one side is formed by oblique implantation, for example with N2 or argon, the implantation taking place from a fixedly predetermined direction with an angle of inclination of between 15 and 40°. The implantation substances effect different etching or oxidation properties, etc., of the implanted materials. In combination with this method, it becomes possible to realize a new layout for the semiconductor memory cell (1), in which the structures for forming the active areas form long lines (31) extending over a plurality of adjacent semiconductor memory cells.

Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

Abstract: A semiconductor memory device comprises a silicon substrate having a main surface, a trench formed on the silicon substrate to open in the main surface and a memory cell formed on the trench. The memory cell includes a first storage holding part formed on a first side wall of the trench, a second storage holding part formed on a second side wall of the trench, impurity diffusion layers formed on both sides of the trench and a gate electrode formed to extend from the trench onto the impurity diffusion layers for covering the first and second storage holding parts.

Abstract: A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.