Abstract: A device comprising a number of different wavelength-selective active-layers arranged in a vertical stack, having band-alignment and work-function engineered lateral contacts to said active-layers, consisting of a contact-insulator and a conductor-insulator. Photons of different energies are selectively absorbed in or emitted by the active-layers. Contact means are arranged separately on the lateral sides of the vertical stack for injecting charge carriers into the photon-emitting layers and extracting charge carriers generated in the photon-absorbing layers. The device can be used for various applications for light emission or light absorption. The stack of active layers may also include top and bottom electrodes whereby the device can also be operated as a FET device.

Abstract: A precipitation agent is deposited on a lower electrode layer of an organic electronic device prior to fabrication of organic layers. After the precipitation agent is deposited, organic material is deposited over the precipitation agent. The precipitation agent induces a more uniform and flatter profile when the organic material is allowed to dry into a film on the treated surface.

Abstract: An electronic device includes first and second electrical contacts electrically coupled to a semiconductor polymer film, which includes mono-substituted diphenylhydrazone.

Abstract: Double heterojunction polycrystalline thin-film solar cell devices that include a polycrystalline p-layer, a polycrystalline i-layer, and a polycrystalline n-layer. In one variant, at least two of the p-layer, i-layer, and n-layer comprise a polycrystalline Cu material. In another variant, each of the p-layer, i-layer, and n-layer comprise a common cation or a common anion.

Abstract: A barrier layer that meets three requirements, “withstand well against etching and protect a semiconductor film from an etchant as an etching stopper”, “allow impurities to move in itself during heat treatment for gettering”, and “have excellent reproducibility”, is formed and used to getter impurities contained in a semiconductor film. The barrier layer is a silicon oxide film and the ratio of a sub-oxide contained in the barrier layer is 18% or higher.

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate.

Abstract: A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 ?; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 ?; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

Abstract: In order to obtain a light-emitting device having a higher aperture ratio in pixels than that of the prior art, a source signal line and a current supply line to be connected with a pixel unit are switched by a switching circuit to use a common wiring lines so that the number of wiring lines in the pixel unit is reduced to realize the high aperture ratio.

Abstract: A method for forming an LED includes bonding a heat generating region of a light emitting device to a heat conductive substrate, so as to define a composite structure and so as to substantially enhance the heat dissipation. Enhancing heat dissipation from the device facilitates operation at higher currents, so as to provide greater light output therefrom.

Abstract: A method for producing an emission module having at least two vertically emitting lasers in which an optically active laser layer is arranged on a substrate and at least one upper covering layer is arranged on said laser layer. In a first etching step, upper mesa regions are formed by etching the upper covering layer, wherein the etching depth of the first etching step is chosen such that the first etching step is ended above the optically active laser layer, and the first etching step is carried out such that the resulting distance between adjacent upper mesa regions is so small that the radiation generated by the finished lasers can be coupled directly into a single optical waveguide. In a second etching step, the optically active layer is severed to form lower mesa regions, the second etching step being a wet-chemical or dry-chemical etching step with a predominantly chemical etching component.

Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.

Abstract: A light emitting device includes: a plurality of luminescent cells each having substantially same thickness and including a first and a second conductive layers having conductive characteristic and a light emitting layer being sandwiched by the first and the second conductive layers and including a luminescent material that emits light when a voltage is applied; a first electrode substrate being contacted with the first conductive layer of each of the luminescent cells to be electrically connected there with; a second electrode substrate being contacted with the second conductive layer of each of the luminescent cells to be electrically connected therewith; and a sealing member that seals the luminescent cells within a space formed between the first and the second electrode substrates. The first electrode substrate and the first conductive layer are transparent with respect to the light emitted from the light emitting layer.

Abstract: Guard electrodes 2 which are electrically connected with a conductive portion of a cooling water passage 23 through connection lines 3 are respectively provided in the middle of a water inlet pipe 1 connected with a water inlet master pipe 10 and a water outlet pipe 6 connected with a water outlet master pipe 13 in M pieces of semiconductor laser units 4. At this time, since the guard electrode 2 has a potential equal to the conductive portion of the cooling water passage 23, the electric current hardly flows between the guard electrode 2 and the conductive portion of the cooling water passage 23. As a result, rusting is inhibited in the M pieces of semiconductor laser units 4, and a clogged piping is prevented in the cooling water passage 23.

Abstract: A luminescence diode chip with a semiconductor body having an epitaxially grown semiconductor layer sequence with an active zone and a radiation coupling-out area, the active zone emitting an electromagnetic radiation during operation of the luminescence diode chip, which electromagnetic radiation, at least in part, is coupled out via the radiation coupling-out area. The luminescence diode chip has a radiation-transmissive covering body that is arranged downstream of the radiation coupling-out area in an emission direction of the luminescence diode chip and has a first main surface facing the radiation coupling-out area, a second main surface remote from the radiation coupling-out area, and also side faces connecting the first and second main areas.

Abstract: An insulating substrate made of insulating material is used. A pair of electrode patterns are formed on the surface of the insulating substrate, and a pair of through-holes are formed in the insulating substrate. A resin is mounted on the insulating substrate to close an opening of each of the through-holes. Two portions of the resin are removed to form a pair of electric conduction parts necessary for mounting an LED element.

Abstract: A light emitting element array is made with large light emitting elements and small light emitting elements are arranged on a substrate in a matrix-like form. The large light emitting element has the luminescent area of about 1 mm square. There is a clearance N1 of about 0.5 mm between the large light emitting elements. The small light emitting element has the luminescent area of about 0.5 mm square, and each small light emitting element is disposed at a position corresponding to each clearance N1 in the scanning direction. Because the large light emitting elements and the small light emitting elements do not overlap each other in the scanning direction, even if the light emitting element array comes close to a thermosensitive recording paper, there becomes no uneven distribution of light quantity of the light emitting element array in the scanning direction.

Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group Ill-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.

Abstract: A light emitting device includes a photonic crystal having a periodic pattern of elements exhibiting a spectrum of electromagnetic modes that includes guided modes of frequencies below a predetermined cutoff frequency, and radiation modes of frequencies below and above the cutoff frequency. A radiation source is associated with the photonic crystal. Each of the elements is covered by a reflective layer so as to introduce at least an omnidirectional photonic band gap between the guided modes and so as to permit coupling of the radiation to the radiation modes rather than to the guided modes.

Abstract: A crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area.

Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.

Abstract: A method for forming a sensor is provided, together with a sensor formed according to the method. Photoresist material is deposited on a surface of the sensor, and is then patterned and etched to form an array of microlens structures. The structures are spaced close together in a predetermined pattern so that when a reflow process is performed, the structures melt and coalesce to form a barrier. The barrier defines a region for constraining or channeling the flow of reagent and analyte samples used in bio-optical sensors.

Abstract: A light emission device. A lead frame comprises a first lead frame segment and a second lead frame segment. A light source is coupled to the first lead frame segment. A wire bond is coupled to the light source and coupled to the second lead frame segment. A translucent epoxy cast encases the light source, the wire bond and a portion of the lead frame.

Abstract: Provided are a semiconductor laser diode and a method of manufacturing the same. The semiconductor laser diode includes an n-type compound semiconductor layer; a resonant layer stacked on a predetermined region of the n-type compound semiconductor layer; a p-type compound semiconductor layer formed on the resonant layer; electrodes respectively formed on each of the p-type and n-type compound semiconductor layers; a bonding metal film stacked on the electrodes; and a high reflection film stacked on the other surface of the resonant layer facing a surface through which a laser generated from the resonant layer is emitted, wherein the thickness of the bonding metal film is greater than that of the high reflection film.

Abstract: A method and apparatus for forming a hermetic seal between two substrates includes providing an electromagnetic absorbent sealing material perimetrically about a surface of one of the substrates. Furthermore, the illustrative method includes heating the sealing material. In addition, a package having a hermetic seal and apparati for disposing a sealing material are described.

Abstract: A switchable stereoscopic display system, wherein the switchable stereoscopic display system can display two-dimensional and three-dimensional images, includes: an organic light emitting diode (OLED) display device; Electronics that rapidly updates individual OLEDs; and a linearly polarizer for the OLED display device. Additionally, a circular polarizing layer changes light from linearly polarized light to circular polarized light. A polarization layer, on top of the circular polarization layer, switches a polarization direction of emitted light within the OLED display device. Other electronics switches the polarization direction within independent segments of the polarization layer. Refreshed OLEDs are synched with the independent segments of the polarization layer.

Abstract: In a nitride semiconductor light-emitting device, and according to a method for fabricating it, a low-defect region having a defect density of 106 cm?2 or less and a carved region in the shape of a depressed portion are formed on the surface of a nitride semiconductor substrate, and the etching angle ?, which is the angle between the side surface portion of the depressed portion and an extension line of the bottom surface portion thereof as measured with the depressed portion seen in a sectional view, is in a range of 75°???140°. This prevents the development of cracks, and reduces the creep-up growth from the bottom growth portion of the carved region, thereby reducing the film thickness of the side growth portion. This makes it possible to produce, with a high yield, a nitride semiconductor laser device having a nitride semiconductor growth layer with good surface flatness.

Abstract: The semiconductor light generating device comprises a light generating region 3, a first AlX1Ga1-X1N semiconductor (0?X1?1) layer 5 and a second AlX2Ga1-X2N semiconductor (0?X2?1) layer 7. In this semiconductor light generating device, the light generating region 3 is made of III-nitride semiconductor, and includes a InAlGaN semiconductor layer. The first AlX1Ga1-X1N semiconductor (0?X1?1) layer 5 is doped with a p-type dopant, such as magnesium, and is provided on the light generating region 3. The second AlX2Ga1-X2N semiconductor layer 7 has a p-type concentration smaller than the first AlX1Ga1-X1N semiconductor layer 5. The second AlX2Ga1-X2N semiconductor (0?X2?1) layer 7 is provided between the light generating region 3 and the first AlX1Ga1-X1N semiconductor layer 5.

Abstract: Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous layer interposed there between. The amorphous material may be deposited on a bonding face of the first layer, second layer, or both, before the operation of bonding the first and second layers. The layer with less noble material may be a supporting layer and the other layer may be an active layer for forming components in optics, electronics, or opto-electronics. The amorphous layer may be polished before the bonding operation.

Abstract: A switchable resistive device has a multi-layer thin film structure interposed between an upper conductive electrode and a lower conductive electrode. The multi-layer thin film structure comprises a perovskite layer with one buffer layer on one side of the perovskite layer, or a perovskite layer with buffer layers on both sides of the perovskite layer. Reversible resistance changes are induced in the device under applied electrical pulses. The resistance changes of the device are retained after applied electric pulses. The functions of the buffer layer(s) added to the device include magnification of the resistance switching region, reduction of the pulse voltage needed to switch the device, protection of the device from being damaged by a large pulse shock, improvement of the temperature and radiation properties, and increased stability of the device allowing for multivalued memory applications.

Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) includes a light-receiving sensor section disposed on the surface layer portion of a substrate (21) that performs a photoelectric conversion, a charge transfer section that transfers a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semiconductor substrate and providing an electric part forming portion; and a periphery portion surrounding the cell portion. The periphery portion includes a trench, which penetrates the second and the third semiconductor layers, reaches the first semiconductor layer, and surrounds the cell portion so that the second and the third semiconductor layers are divided by the trench substantially. The periphery portion further includes a fourth semiconductor layer disposed on an inner wall of the trench.

Abstract: A high-power solid-state transistor structure comprised of a plurality of emitter or gate fingers in a uniform or non-uniform manner to provide improved high power performance is disclosed. Preferably, each of the fingers is associated with a corresponding one of a plurality of sub-cells, the sub-cells being arranged in at least one row. The advantage of the invention is that the structure can be practically implemented and the absolute thermal stability can be maintained for very high power transistors with reduced adverse effects resulting from random variation in the manufacturing and design process.

Abstract: A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

Abstract: An electronic system having a sandwich design and including two carriers, each carrier having a printed circuit layer, the upper printed circuit layer being positioned on different planes.

Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) includes a light-receiving sensor section disposed on the surface layer portion of a substrate (21) that performs a photoelectric conversion, a charge transfer section that transfers a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.

Abstract: A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

Abstract: A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.

Abstract: A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semi-conductive layers, such that the raised extrinsic base is self-aligned to the emitter.

Abstract: A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

Abstract: A semiconductor apparatus is characterized in that it comprises a semiconductor module having a plurality of semiconductor elements and an external connection terminal for externally connecting electrodes of the semiconductor elements in the semiconductor module, wherein the semiconductor elements in each semiconductor module are connected in parallel and/or in series via the external connection terminal.

Abstract: Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.

Abstract: In a photosensitive part 10, arranged from pixels A aligned in n rows and m columns, supply wiring lines 13a and 13b, which are electrically connected and apply transfer voltages to transfer electrodes 12a to 12d, formed of polycrystalline silicon, are installed so as to cover parts of the top surfaces of light-shielded pixels D. Dead zones for installing supply wiring lines, which existed priorly at the respective end parts in a horizontal direction of a photosensitive part, can thereby be eliminated and the photosensitive part can be made wide. Also, in the case where a plurality of the solid-state image pickup devices are used upon being made adjacent each other in the horizontal direction, parts at which image pickup is not carried out can be lessened. Also, the amount of lowering of the amounts of incident light on light-shielded pixels D can be corrected based on the output signals from light-shielded pixels D or other pixels A.

Abstract: Briefly, micromechanical system (MEMS) switches that utilize protective layers to protect electrical contact points.

Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

Abstract: A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Abstract: A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on the gate oxide layer; a spacer provided to a sidewall of the gate; and a well region provided within the active area. The well region includes a threshold voltage adjustment doped region, a halo region, a source region, a drain region, an additional doped region, and a channel stop region, the additional doped region provided between the well region and each of the source and drain regions.

Abstract: An image sensor is provided that can be made compact, low power consuming, and operative at high speed without degrading image quality and read-out speed. The image sensor includes a pixel cell having a photo diode 31 and a reset transistor 32 connected to a power supply, a detection transistor 33 for detecting the signal voltage of the photo diode 31, a selection transistor 34 for selecting the detection transistor 33 and reading the signal voltage therefrom; a peripheral circuit 12 having MOS transistors; and an input/output circuit 13 having MOS transistors. The gate dielectric films 60A of the reset transistor 32 and the detection transistor 33 are formed thicker than the gate dielectric film of the selection transistor 34.

Abstract: In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more ploymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer comprising a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.

Abstract: A ferroelectric film is provided that is expressed by a general formula of A1-bB1-aXaO3, wherein: A includes Pb; B is composed of at least one of Zr and Ti; X is composed of at least one of V, Nb, Ta, Cr, Mo and W; a is in a range of 0.05?a?0.3; and b is in a range of 0.025?b?0.15.