Abstract: The invention provides a semiconductor chip manufacturing method including the steps of: forming a concave portion extended in the thickness direction of a semiconductor substrate which has a front surface and a rear surface and has a function device formed on the front surface, from the front surface; forming an oxidation preventive film made of an inert first metal material by supplying the first metal material onto the inner wall surface of the concave portion; supplying a second metal material containing a metal which is oxidized more easily than the first metal material to the inside of the concave portion after the step of forming the oxidation preventive film; electrically connecting the second metal material supplied to the inside of the concave portion and the function device; and thinning the semiconductor substrate so that the thickness thereof becomes thinner than the depth of the concave portion by removing the semiconductor substrate from the rear surface while leaving the oxidation preventive f

Abstract: An electronic device includes: a first substrate and a second substrate; a lead frame disposed between the first and the second substrates for electrically connecting therebetween; and a first groove and a second groove disposed on the first and the second substrates, respectively. The first and the second grooves correspond to a connection portion between the first and the second substrates and the lead frame. The lead frame is connected to the first and the second substrates in such a manner that one end of the lead frame is engaged in both of the first and the second grooves through a conductive bonding material.

Abstract: A preventive film for a polarizer which comprises a non-oriented three-layer film comprising a polycarbonate film having a glass transition temperature or 100° C. or higher and, laminated on both surfaces thereof, a polybutylene terephthalate film: a releasable preventive film for a polarizing film which comprises the three-layer film and, applied on the surface of the polybutylene terephthalate film side, a silicon based releasing agent; and a polarizing plate preventive film for a polarizing film and the releasable preventive film for a polarizing film as uppermost surface layers of a polarizing film containing a polarizer. The preventive film for a polarizing film and the releasable preventive film for a polarizing film exhibit an extremely small double refraction and can be produced at a low cost, and the polarizing plate using these films allows the detection of optical defects with ease.

Abstract: A surface mount type semiconductor device can be configured to include a pair of lead frames that are butted to each other with a spacing such that ends of the lead frames are opposite to each other. A bare chip can be mounted on a chip mount portion on one end side of one of the lead frames, and wire-bonded to a connection portion on an end side of the other lead frame. A housing can be insert-molded to an end side of both of the lead frames, and the lead frames can be shaped such that they extend along the side and bottom surfaces of the housing and form surface mounting terminal portions. The lead frames are preferably formed to be thin at least at the regions that are to be bent, and other regions thereof are preferably formed to be thick to improve heat radiating effect.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: Various apparatus and systems, as well as methods and articles, may include the use of several compositions, such as solder formulations, including about 78%-83% by weight of lead, about 9%-11% by weight of antimony, about 1%-3% by weight of silver, and a balance of tin. Some embodiments include a process of removing a previously-existing lead finish, and applying a new finish to the lead to improve solder operation compatibility, as well as solder joint reliability in high temperature environments.

Abstract: A semiconductor device includes a semiconductor element, a resin substrate where the semiconductor element is mounted, and a supporting plate configured to support the resin substrate. A first gas discharging hole is made through the supporting plate. Gas generated from the resin substrate is discharged through the first gas discharging hole.

Abstract: There is here disclosed a semiconductor device comprising a semiconductor element, a first substrate disposed to face one side of the element, being provided first internal wirings on a main surface, and being provided first external wirings connected to the respective first internal wirings on another main surface, and a second substrate formed to be larger than the element by a material having flexibility, being disposed to face another side of the element, being provided second internal wirings having one-end portions extended to edges of a main surface, and the one-end portions connected to the first internal wirings with being bent toward the first substrate together with the edges, being mounted the element having an electrode connected to some of the second internal wirings on the main surface, and being provided external terminals connected to some of the second internal wirings on a middle of another main surface.

Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.

Abstract: Disclosed are a multi-chip assembly and a method for driving the same. The multi-chip assembly includes a first chip designed with a first device driven by a first power source and a second chip designed with a second device driven by a second power source. A power applying section applies first power to the first device of the first chip and a power converting section converts the first power to second power upon receiving the first power from the power applying section and applies the second power to the second device of the second chip. It is possible to provide the multi-chip assembly in the form of a package fabricated by stacking chips designed with mutually different devices driven through a single power source.

Abstract: A semiconductor device (700) having a leadframe with a first plurality of segments (110) having a narrow end portion (111) in a first horizontal plane (211) and a wide end portion (112) in a second horizontal plane (212). The leadframe further includes a second plurality of segments (120) having a narrow center portion (121) in the first horizontal plane, at least one wide center portion (122) in the second horizontal plane, and narrow end portions (123) in a third horizontal plane (213), which is located between the first and second planes.

Abstract: An edge seal for a chip with integrated circuits. A first metal line extends along a periphery of the chip, with a first inter-metal dielectric layer on the first metal line. A second metal line overlies the first inter-metal dielectric layer and extends along the periphery of the chip. A plurality of first metal plugs in the first inter-metal dielectric layer connects the first metal line and the second metal line and at least one first metal wall in the first inter-metal dielectric layer is laterally adjacent to a periphery of the first metal line.

Abstract: In a compact radio frequency module, a first chip forms a heater element and a second chip forms a device whose operating characteristics vary with temperature change or whose maximum operating temperature is lower than the maximum operating temperature of the first chip. A multilayer substrate has a plurality of dielectric layers and a plurality of conductor layers and mechanically supports the first chip and the second chip with some of the conductor layers electrically connected with these chips. The module can conduct the heat generated by the first chip throughout the module; guide the heat generated by the first chip from the module's top face side to its bottom face side; and interrupt the heat conduction from the first conductor pattern on which the first chip is placed to the second conductor pattern on which the second chip is placed.

Abstract: A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

Abstract: A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate. Lower end surfaces of the electric signal terminals and the heat releasing terminals are exposed from and sealed with a sealing resin. The heat sink plate is formed as an integrated body including a protruding portion that protrudes from a central portion of an upper surface and supports the semiconductor chip, a plurality of supporting portions that are positioned around a rear surface of the protruding portion so as to support the protruding portion and that are exposed at a rear surface of the sealing resin, the plurality of heat releasing terminals, and a thin-walled portion that is recessed from lower end surfaces of the supporting portions and the heat releasing terminals.

Abstract: In accordance with the invention a chip packaging structure and technique is arranged in which multiple surfaces of the semiconductor chip are surrounded in a pocket in a module with direct transfer thermally conductive materials. The chip packaging module consists of a thermally conductive plate and cover which together form a thermally conductive pocket or shell around the chip. The pocket inside the shell is filled with thermally conductive paste-like materials which are compressed under spring forces. The direct thermal transfer is achieved using thermal transfer plates of such materials such as silicon, diamond-like, or copper-invar-copper plates on all six sides.

Abstract: A method and apparatus for cooling an electronics chip with a cooling plate having integrated micro channels and manifold/plenum made in separate single-crystal silicon or low-cost polycrystalline silicon. Forming the microchannels in the cooling plate is more economical than forming the microchannels directly into the back of the chip being cooled. In some embodiments, the microchannels are high-aspect-ratio grooves formed (e.g., by etching) into a polycrystalline silicon cooling base, which is then attached to a cover (to contain the cooling fluid in the grooves) and to the back of the chip.

Abstract: The invention concerns an assembly of at least one electrical or electronic power supply component on a printed circuit board (10) characterized in that said or at least one electrical or electronic power supply component (30) is directly mounted in close thermal contact on a thermally conductive conduction board (20) itself mounted in an opening (13) comprised in said printed circuit board (10), the lugs (32) of said or at least one electrical or electronic power supply component (30) being connected directly on the printed circuit (10).

Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.

Abstract: The present invention provides an electronic device comprising a base substrate to be surface-mounted on a circuit board, one or more electronic component elements mounted on a surface of the base substrate and/or therein, an external electrode provided on an end portion of the base substrate and in the form of a post perpendicular to a rear surface of the base substrate for connecting the one or more electronic component elements to the circuit board. Furthermore, the base substrate is provided on its end portion with a slope crossing a side surface and a rear surface of the base substrate. A surface of the external electrode is exposed on the slope.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically.

Abstract: A passive component is integrated into a product having a rewiring location.

Abstract: A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.

Abstract: A mounting substrate of an embodiment of the present invention comprises a first main surface constituting a mounting surface on which an electric device is mounted, and having formed thereon an electrode pattern comprising a plurality of electrode pads that are electrically connected to the electronic device via a bump, and a second main surface which is positioned on the opposite side of the first main surface, and which has formed thereon a plurality of input/output terminals that are electrically connected to the electrode pads. All of the input/output terminals are formed in positions apart from the periphery of the mounting substrate.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: A bonding wire comprising a core mainly consisting of copper, a different metal layer formed of a metal other than copper and formed on the core, and a coating layer formed of an oxidation-resistant metal having a melting point higher than that of copper and formed on the different metal layer, from which balls having the shape of a true sphere in a wide ball diameter range can be formed stably, which can be produced without causing the deterioration of a plating solution at the time of plating, and in which the adhesiveness between the coating layer and the core thereof is excellent; and an integrated circuit device using the bonding wire are provided.

Abstract: A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film.

Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.

Abstract: A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes freestanding electrodes which are not fixed to the substrate.

Abstract: A semiconductor device includes a substrate having a first area on which a semiconductor element is mounted, a second area which surrounds the first area, and a third area located in a central portion of the first area; wirings extending from the second area to the third area and formed over the substrate; and an insulting film which is formed in the first and second areas so as to expose the third area and to cover portions of the substrate and the wirings. The semiconductor element which is electrically connected to the wirings within the third area. The semiconductor element has a size equal to the first area and is mounted on the first area so as to be spaced a predetermined interval from the insulating film.

Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

Abstract: A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.

Abstract: An interconnection structure for a semiconductor device, and a method of forming the same, having a tolerance to high temperature and high speed while not suffering from a problem of a drawing out of a first lower metal pattern. In addition, a second lower metal pattern may be formed, not using a patterning process including a photolithography process, but using a selection etching characteristic instead. Therefore, the second lower metal pattern is self-aligned to the first lower metal pattern, thereby making up for a decrease of a margin in the photolithography process with increasing high integration. As a result, the present invention may be employed to fabricate a semiconductor device to be more highly integrated.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

Abstract: After a via hole to connect a lower wiring and an upper wiring not shown is formed in an insulating film using an etching stopper film and a hard mask, a base film made from tantalum is formed on the insulating film so as to cover an inner wall of the via hole by a one-step low-power bias sputtering method of the present invention. Thus, the base film with a thin and uniform film thickness covering a region from an inner wall surface of the via hole to the insulating film is obtained.

Abstract: In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers formed, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

Abstract: More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.

Abstract: An insulating film having dielectric constant not greater than 2.7 is provided above a semiconductor substrate. A via comprises a conductive material, which is provided in a via hole formed in the insulating film. A first interconnection comprises a conductive material, which is provided in an interconnection trench formed on the via in the insulating film. A first high-density region is formed in the insulating film, and has a cylindrical shape surrounding the via, an inner surface common to the boundary of the via hole, and a film density higher than the insulating film.

Abstract: There is here disclosed a semiconductor device comprising a first base material which is provided at least one semiconductor device mounted on one main surface, a plurality of first connection portions provided on the main surface and being electrically connected to the semiconductor device, and a plurality of second connection portions provided outside a region on which the semiconductor device is mounted on the main surface, and a second base material which is disposed facing other main surface of the first base material on a side opposite to the side on which the semiconductor device is mounted, bonded to an edge of the first base material, and provided a plurality of third connection portions provided outside a region on which the first base material is mounted on and being electrically connected to at least one of the second connection portions.

Abstract: A method for assembling a whole semiconductor wafer (101) with a plurality of device units (120) having metal contact pads. Each contact pad has a patterned barrier metal layer and a metal stud (103, preferably copper or nickel) with an outer surface suitable to form metallurgical bonds without melting. A leadframe suitable for the whole wafer is provided, which has a plurality of segments groups (102), each group suitable for one device unit; each segment has first (102a) and second ends (102b) covered by solderable metal. A predetermined amount of solder paste (104) is placed on each of the first segment ends. The leadframe is then aligned with the wafer so that each of the paste-covered segment ends is aligned with the corresponding metal stud of the respective device unit. The leadframe is connected to the wafer and the whole wafer is encapsulated (105) so that the device units and the first segment ends are covered, while the second segment ends remain exposed.

Abstract: A flip-chip package for implementing a fine solder ball, and a flip-chip packaging method using the same. The flip-chip package includes a first wafer having a first electrode and a first under bump metal (UBM) formed on the first electrode and electrically connected to the first electrode; and second wafer opposing the first wafer and having a second electrode located in a position corresponding to the first electrode, and a second UBM formed on the second electrode and electrically connected to the second electrode. The first wafer has a depression formed on one or more areas adjacent to the first UBM, which depression partly receives a solder ball that connects the first and the second UBMs upon flip-chip bonding of the first and second wafers. Since the UBM is formed as an embossing pattern, a fine solder ball can be implemented. Additionally, the reliability of the package can be improved.

Abstract: Improved materials for use in the fabrication of electronic devices and devices made therewith are described. The materials comprise fillers having a negative coefficient of thermal expansion.

Abstract: The present invention provides an adhesive film for circuit connection which is to be interposed between circuit electrodes facing each other and used for electrically connecting the circuit electrodes to each other, which comprises a curing agent to generate free radicals with heating, a radically polymerizable substance, and a film-forming polymer, and in which a temporary fixing power to a flexible substrate having the circuit electrode is 40-180 N/m.

Abstract: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Abstract: A semiconductor chip package includes an integrated circuit chip and a substrate. A chip contact pad is formed on a first side of the chip. A stud is formed on the chip contact pad from wire using a wire bonding machine. The stud has a partially squashed ball portion bonded to the chip contact pad. The stud also has an elongated portion extending from the partially squashed ball portion. A first layer of insulating material is on a first side of the substrate. A bottomed well is formed in the first layer and opens to the first side of the substrate. A first conductive material at least partially fills the well. The first conductive material is electrically connected to at least one trace line in the substrate. The stud is partially embedded in the first conductive material to form an electrical connection between the chip and the substrate.

Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area of the semiconductor substrate, stacking first to third insulating layers over the substrate, forming a spacer on a sidewall of the third conductor pattern in the exposed periphery area, removing the third insulating layer, and forming first and second spacers on sidewalls of the first and second conductor patterns.

Abstract: A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

Abstract: A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.