Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi

Abstract: A display panel and a method for manufacturing the display device having the display pixel, includes forming a first substrate with pixel areas and a second substrate facing the first substrate. The second substrate includes a color filter layer having a first region and a second region that is arranged lower than the first region. A first member is arranged in the first region between the first substrate and the second substrate to maintain a cell gap between the first substrate and the second substrate. The second cell gap-maintaining member is arranged in the second region between the first substrate and the second substrate to absorb an external force being applied to the first substrate and the second substrate.

Abstract: An organic electro luminescence device and a fabrication method thereof are provided. An array element is formed on a first substrate and an electro luminescent diode is formed on a second substrate. The array element and the electro luminescent diode are electrically connected together by a spacer. A separator divides a sub pixel into a first region and a second region. In the electro luminescent diode, an anode electrode is formed over the first and second regions. An organic electro luminescent layer and a cathode electrode are formed on the anode electrode of one of the first and second regions.

Abstract: The thin film transistor has a non-transparent structure besides and insulated with the gate. Hence, the light transmitted from the substrate is blocked and the light current induced in the thin film transistor is negligible. The method uses a mask with a slit pattern to form a non-uniform photoresist. Hence, the mask could be used to pattern two conductor layers for forming source/drain/channel.

Abstract: A wide bandgap semiconductor material comprised of Silicon carbide containing a predetermined portion of germanium.

Abstract: A light emitting device having a circuit protection unit is provided. The circuit protection unit has a low-resistance layer and a potential barrier layer, wherein a barrier potential exists at the interface between the low-resistance layer and the potential barrier layer. The circuit protection unit is electrically connected with the light emitting device. When an electrostatic discharge or excessive forward current is occurred in the light emitting device, the circuit protection unit provides a rectifying function for preventing damages caused by static electricity or excessive forward current to the light emitting device.

Abstract: A light emitting device includes a semiconductor structure having lateral side faces, and including a light-generating layer, and two omnidirectional reflectors disposed respectively at two sides of the light-generating layer. Each of the omnidirectional reflectors exhibits a periodic variation indielectric constant in such a manner so as to introduce an omnidirectional photonic band gap in a given frequency range such that the radiation generated by the light-generating layer in the frequency range for all incident angles and polarizations can be totally reflected by the omnidirectional reflectors and can be extracted substantially only from the lateral side faces of the semiconductor structure.

Abstract: Disclosed is a light emitting semiconductor bonding structure and its manufacturing method. The light emitting semiconductor bonding structure includes a structure formed by bonding a substrate onto a light emitting semiconductor. The substrate is a structure containing electric circuits. The ohmic contact N electrode layer and P electrode layer are formed on the N-type contact layer and the P-type contact layer of the light emitting semiconductor respectively. The first metallic layer and the second metallic layer are formed on the surface of the substrate by means of immersion plating or deposition. The metallic layers are connected electrically to the corresponding electric signal input/output nodes of the electric circuit of the substrate.

Abstract: A Group III nitride semiconductor light-emitting element includes a crack-preventing layer 15 of n-type GaN provided between a n-type contact layer 4A and a n-type clad layer 5A, wherein the crack-preventing layer 15 has a dopant concentration lower than that of the n-type contact layer 4A.

Abstract: A structure for the n-type contact layer in the GaN-based MQW LEDs is provided. Instead of using Si-doped GaN as commonly found in conventional GaN-based MQW LEDs, the n-type contact layer provided by the present invention achieves high doping density (>1×1019 cm?3) and low resistivity through a superlattice structure combining two types of materials, AlmInnGa1-m-nN and AlpInqGa1-p-qN (0?m, n<1, 0<p, q<1, p+q?1, m<p), each having its specific composition and doping density. In addition, by controlling the composition of Al, In, and Ga in the two materials, the n-type contact layer would have a compatible lattice constant with the substrate and the epitaxial structure of the GaN-based MQW LEDs. This n-type contact layer, therefore, would not chap from the heavy Si doping, have a superior quality, and reduce the difficulties of forming n-type ohmic contact electrode. In turn, the GaN-based MQW LEDs would require a lower operation voltage.

Abstract: A device and method for emitting output light utilizes both quantum dots and non-quantum fluorescent material to convert at least some of the original light emitted from a light source of the device to longer wavelength light to change the color characteristics of the output light. The device can be used to produce broad-spectrum color light, such as white light.

Abstract: The present invention relates to a dipolar LED and a dipolar LED module incorporating the same, in which an upper hemisphere-shaped base houses an LED chip therein and adapted to radiate light from the LED chip to the outside, and a pair of reflecting surfaces placed at opposed top portions of the base in a configuration symmetric about an imaginary vertical plane. The vertical plane passes through the center of the LED chip perpendicularly to a light-emitting surface of the LED chip. The reflecting surfaces are extended upward away from the top portions of the base to reflect light from the LED chip away from the imaginary vertical plane. A pair of radiating surfaces are placed outside the reflecting surfaces, respectively, to radiate light from the reflecting surfaces to the outside. In this way, light emission from the LED chip can be concentrated in both lateral directions.

Abstract: An organopolysiloxane composition which cures to a resinous solid has high strength, transparency, and resistance to thermal- and photo-degradation, and is especially suited for encapsulating LEDs. The composition contains specific addition curable organopolysiloxanes having D, T, and Q units, and a proportion of silicon-bonded aromatic groups.

Abstract: A light-emitting diode capable of making its light emission more uniform without too high a concentration current and of improving the efficiency of outgoing light and its life. In the light-emitting diode, the n-side electrode has an n-side connecting portion and an n-side extending portion, which extends in the longitudinal direction from a predetermined part of the n-side connecting portion, and the p-side pad member has at least a p-side connecting portion to be connected to a conductive member. The light-emitting diode further includes an n-side connecting area, in which the n-side connecting portion is provided, provided in proximity to one end in the longitudinal direction, a p-side connecting area, in which the p-side connecting portion is provided, provided in proximity to another end in the longitudinal direction, and a middle area provided between them, and the n-side extending portion is positioned in the middle area, and extends so as to be opposed to the p-side current diffusing member.

Abstract: An optical semiconductor apparatus has an eyelet having a through hole, an insulating member provided in the through hole, a semiconductor optical element, and a submount on which the semiconductor optical element is mounted. The insulating member supports a plurality of lead terminals. The submount has a first portion supported by the eyelet, a second portion supported by the eyelet, and a third portion disposed between the first portion and the second portion and located above the insulating member. The semiconductor optical element is provided on the third portion of the submount.

Abstract: Provided are a reflective electrode and a compound semiconductor light emitting device having the reflective electrode, such as LED or LD is provided. The reflective electrode formed on a p-type compound semiconductor layer of a compound semiconductor light emitting device, comprising a first electrode layer formed one of a Ag and Ag-alloy and forms an ohmic contact with the p-type compound semiconductor layer, a third electrode layer formed of a material selected from the group consisting of Ni, Ni-alloy, Zn, Zn-alloy, Cu, Cu-alloy, Ru, Ir, and Rh on the first electrode layer, and a fourth electrode layer formed of a light reflective material on the third electrode layer.

Abstract: A semiconductor device with high reliability, low voltage, and high luminance is provided by preventing detachment of an electrode by way of obtaining good adhesion of the electrode, even in cases where a face-down mounting of a semiconductor laser is performed, and further, an insulating film and a protective film etc. are disposed in the area other than the area where the electrode is ohmically connected to the semiconductor layer. In a semiconductor device having an electrode electrically connected to the semiconductor layer, a dielectric film and an adhesion film comprising a degenerate semiconductor are stacked in sequence on a portion of a region between the semiconductor layer and the electrode, and the adhesion film is in contact with the electrode.

Abstract: A flip-chip electrode light-emitting element formed by multilayer coatings where a translucent conducting layer and a highly reflective metal layer acts as flip-chip electrode for enhancing the LED luminous efficiency. The flip-chip electrode light-emitting element includes a translucent substrate, a semiconductor die structure attached on the translucent substrate and made of group III nitride compounds, and an intermediate layer adapted to support the inverted semiconductor die structure on a submount. The flip-chip electrode formed by multiplayer coatings includes a current-spreading transparent conducting layer formed on a top side of the second type semiconductor layer, a highly reflective metal layer formed on a top side of the transparent conducting layer, a metallic diffusion barrier layer formed on a top side of the highly reflective metal layer, and a bonding layer electrically coupled to the intermediate layer and formed on a top side of the barrier layer.

Abstract: In a method of forming an electrically conductive lamination pattern, an insulating film is formed on a surface of a chromium-containing bottom layer, before an aluminum-containing top layer is formed over the insulating film, so that the insulating film separates the aluminum-containing top layer from the chromium-containing bottom layer. A first selective wet etching process is carried out for selectively etching the aluminum-containing top layer with a first etchant. A second selective wet etching process is carried out for selectively etching the chromium-containing bottom layer with a second etchant in the presence the insulating film which suppresses a hetero-metal-contact-potential-difference between the chromium-containing bottom layer and the aluminum-containing top layer during the second selective wet etching process.

Abstract: A radiation-emitting semiconductor component comprising a plurality of semiconductor bodies (10, 20, 30) which each have an active zone (11, 21, 31) and during operation emit light having in each case a different central wavelength (?10, ?20, ?30) and an assigned spectral bandwidth (??10, ??20, ??30), so that the mixing of this light gives rise to the impression of white light. In the case of at least one of the semiconductor bodies (10), the emission wavelength varies in the active zone (11) in a predetermined manner, so that the spectral bandwidth (??10) of the emitting light is increased as a result.

Abstract: An inventive method includes the steps of: growing a first p-type semiconductor layer of a compound semiconductor containing phosphorus on a substrate; and growing a second p-type semiconductor layer of a compound semiconductor containing arsenic on the first p-type semiconductor layer. While the first p-type semiconductor layer is grown, magnesium is added to the first semiconductor layer. While the second p-type semiconductor layer is grown, a p-type impurity other than magnesium is added to the second semiconductor layer.

Abstract: A heterostructure semiconductor device capable of emitting electromagnetic radiation and having a junction with opposite conductivity type materials on either side thereof supported on a substrate with an active layer therebetween comprising zinc oxide and having a band gap energy that is less than that of either of the opposite conductivity type materials.

Abstract: Starved source diffusion methods for forming avalanche photodiodes (APDs) are provided for controlling the edge effect. The edge effect is controlled by reducing edge gain near the edges of an APD active region. This is accomplished by creating a sloped diffusion front near the edges of the active region. The sloped diffusion front is advantageously formed in a single doping step by using a patterned mask during doping. The patterned mask reduces the depth to which dopants diffuse in areas where it only partly covers the underlying layer. By covering more of the underlying layer nearer the edge and progressively less towards the center, the sloped diffusion front is formed. The shallower diffusion depth near the edge reduces the edge gain, and therefore the edge effect. As a result, an APD to fiber misalignment is less likely, and possibility of edge breakdown is greatly reduced.

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract: The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.

Abstract: A semiconductor epitaxial wafer has, on a sapphire substrate, an AlN buffer layer formed of undoped AlN, a GaN buffer layer formed of 2 ?m-thick undoped GaN, and measurement electrodes formed thereon.

Abstract: The transistor circuit 1 includes a plurality of transistor cells 10 each having a transistor 11, a base ballast resistor 12, a capacitor 13, and an inductor 14. The transistors 11 have the respective collectors commonly connected to a collector terminal 1c of the transistor circuit 1 and the respective emitters commonly connected to an emitter terminal 1e thereof. Each base ballast resistor 12 is connected to bases of the transistor 11 at one end and to a base terminal 1b of the transistor circuit 1 at the other end. The capacitor 13 is serially connected to the inductor 14, thus to form a serial resonant circuit 15, which is connected in parallel with the base ballast resistor 12 and provided between the bases of the transistor 11 and the base terminal 1b of the transistor circuit 1 and connected thereto.

Abstract: The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.

Abstract: There is provided a method for producing a field effect transistor with a high field-effect mobility using a simple method for forming an organic semiconductor layer. A method for producing an organic field effect transistor comprising an organic semiconductor layer, comprising a step of forming the organic semiconductor layer by the photodecomposition of a bicyclic compound containing in a molecule thereof at least one bicyclic ring represented by formula (1): wherein R1 and R3 each denotes a group for forming an aromatic ring or a heteroaromatic ring which may have a substituent, together with a group to be bonded to R1 or R3; R2 and R4 each denotes a hydrogen atom, an alkyl group, an alkoxy group, an ester group or a phenyl group; and X is a leaving group which denotes carbonyl group or —N?.

Abstract: A circuit wiring laying-out apparatus includes a wiring device that moves automatically a wiring in a first region to a second region, to make uniform a number of wirings in the circuit.

Abstract: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively low-temperature solution-based processing achievable with the methods of the present invention permit the use of plastics in the fabricated devices.

Abstract: The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconnect space on top of the eM block is converted into 3D-M. This conversion incurs minimum additional cost, but with significant benefits: 3D-M can add a large storage capacity to the SoC chip and therefore the chip becomes more powerful.

Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.

Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.

Abstract: CMOS image sensor devices are provided, wherein active pixel sensors are designed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.

Abstract: A solid-state image sensor capable of suppressing mixture of charge between adjacent charge transfer paths (charge transfer regions), and suppressing reduction of a transfer efficiency of charge is provided. In the solid-state image sensor, the charge transfer region includes a first region with a first channel width, and a second region with a second channel width smaller than the first channel width. A boundary part of the charge transfer region between the first region with the first channel width and the second region with the second channel width is located in a region between two transfer electrodes adjacent to each other.

Abstract: A device and method for managing terahertz and/or microwave radiation are provided. The device can comprise one or more field effect transistors (FETs) that each include at least one channel contact to a central region of the device channel of the FET. The frequency of the radiation managed by the device can be tuned/adjusted by applying a bias voltage to the FET. The radiation can be impinged on the device, and can be detected by measuring a voltage that is induced by the radiation. Further, the device can generate terahertz and/or microwave radiation by, for example, inducing a voltage between two edge contacts on either side of the device channel and applying the voltage to the channel contact.

Abstract: An image sensor includes a substrate with an epitaxial layer deposited thereon, a plurality of photodiodes buried in the epitaxial layer, and a plurality of field oxide films interposed between the photodiodes for insulating the photodiodes. Each of the field oxide films includes a trench formed on the epitaxial layer, a first oxide layer deposited on an inside of the trench, a reflective layer deposited on the first oxide film for reflecting incident light to a side of the photodiode, and a second oxide layer formed on the reflective layer.

Abstract: A nonvolatile semiconductor memory includes a gate insulating layer, a control gate layer, a first silicide layer, charge accumulating layers, memory gate layers and second silicide layers. The gate insulating layer is formed on a first region of a semiconductor substrate. The control gate layer is formed on the gate insulating layer. The first silicide layer is formed on the control gate layer. The charge accumulating layer is formed on one side of the first region of the semiconductor substrate, and capable to accumulate charges. The memory gate layers is formed on the charge accumulating layer, away from the control gate layer. The second silicide layer is formed on the memory gate layer. The memory gate layer includes a thick gate layer and a thin gate layer. The thick gate layer is formed far side from the control gate layer, and bonded to the second silicide layer.

Abstract: A compact semiconductor device forming a capacitive element for high frequencies that allows good capacitance change to be achieved is provided. AMOS capacitor type semiconductor device includes a gate electrode formed on a surface of a substrate through a gate insulating film, source/drain regions provided to have the gate electrode therebetween, and aback gate including a contact diffusion region for contacting the substrate. Voltage applied across the regions between the source or drain region and the gate electrode and between the gate electrode and the back gate is adjusted, so that charge accumulated at the gate insulating film can be adjusted. In the device, the distance between the source and drain regions or the distance between the back gate and the gate electrode is determined so that electrons or holes can be accumulated at the interface between the gate insulating film and the substrate within a cycle of the applied voltage.

Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0?y<1.

Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

Abstract: Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.

Abstract: The present invention disclosed herein is a semiconductor device and a method for forming the same. The semiconductor device includes a first semiconductor pattern defining an active region, second semiconductor patterns placed on the first semiconductor pattern apart from each other, an insulated gate electrode spaced apart from the second semiconductor patterns to be placed therebetween, and stress generating patterns filling intervals between the insulated gate electrode and the second semiconductor patterns. The stress generating patterns apply a stress to a channel region defined by the first semiconductor pattern under the gate electrode, thereby increasing carrier mobility.

Abstract: A GaN-based semiconductor integrated circuit comprising a plurality of types of GaN-based semiconductor devices integrated on a single substrate, and one of the plurality of types of GaN-based semiconductor devices includes a Schottky diode. The Schottky diode includes a GaN-based semiconductor layer, a first anode and a second anode, wherein the first anode is joined to the GaN-based semiconductor layer to form a Schottky junction with a width smaller than the width of the GaN-based semiconductor layer, the second anode is joined to the GaN-based semiconductor layer to form a Schottky junction in a region other than the region in which the first anode is in contact with the GaN-based semiconductor layer, and electrically connected with the first anode, and the Schottky barrier formed between the second anode and the GaN-based semiconductor layer is higher than the Schottky barrier formed between the second anode and the GaN-based semiconductor layer.

Abstract: A semiconductor device including a substrate having a plurality of image sensing elements formed therein, a plurality of spaced apart color filters overlying the substrate and a light blocking material interposed between adjacent spaced apart color filters.

Abstract: A detection arrangement is for modular use for a combined transmission/emission tomography unit, for measuring transmission x-radiation and emission ?-radiation inside a detector. The detection arrangement includes at least three absorption layers of different thickness, arranged one above another in the radiation direction, for detecting absorption events in which case all of the at least three absorption layers consist of a single material. Each absorption layer is connected to a measuring chip which can transmit the measured values of location x, time t and energy E of detected absorption events to a common evaluation unit. The evaluation unit can undertake the breakdown into CT, SPECT and PET signals from the transmitted measured values of the absorption event, and the absorption layers are subdivided into a multiplicity of detection elements.

Abstract: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface.

Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.