Abstract: A system, method and article of manufacture are provided for affording a cryptographic service utilizing a server on a network. Initially, a client is identified utilizing the network. A first key is established, and a tunnel is generated on the network. Thereafter, information is received at the server from the client utilizing the tunnel. Such information is encrypted by the client using the first key. At the server, cryptographic work is performed using the first key.

Abstract: A secure repository individualized for a hardware environment and a method and system for providing the same. The secure repository includes a hidden cryptographic key and code that applies the key without requiring access to a copy of the key. The code that implements the secure repository is generated in a manner that is at least partly based on a hardware ID associated with the hardware environment in which the secure repository is to be installed, and may also be based on a random number. Cryptographic functions implemented by the secure repository include decryption of encrypted information and validation of cryptographically signed information. The secure repository may be coupled to an application program, which uses cryptographic services provided by the secure repository, by way of a decoupling interface that provides a common communication and authentication interface for diverse types of secure repositories.

Abstract: A method for securing cached data in an enterprise environment. The method can include processing a request to locate data in a query cache. If the data can be located in the query cache, the data can be retrieved from the query cache. Additionally, at least one encrypted portion of the retrieved data can be decrypted. Finally, the decrypted portion and any remaining unencrypted portion of the retrieved data can be forwarded to a requesting client. By comparison, if the data cannot be located in the query cache, the data can be retrieved from a back-end data source over a computer communications network, and forwarded to the requesting client. Additionally, at least a portion of the retrieved data can be encrypted and both the encrypted portion and any remaining unencrypted portion can be stored in the query cache.

Abstract: An encryption evaluation support system, includes an evaluation executing unit, and a point storing unit. The evaluation executing unit receives a figure representation of an encryption algorithm. The figure representation includes a plurality of unit figures. The point storing unit stores points allocated to the plurality of unit figures respectively. The evaluation executing unit gives the points to the plurality of unit figures of the figure representation, respectively, to output the points given to the plurality of unit figures of the figure representation.

Abstract: Input signals are electronically watermarked using an uneven or non-uniform sampling rate. The uneven or non-uniform sampling may be pseudo-random. The uneven or non-uniform sampling meets the Nyquist criterion so that aliasing and loss of content are avoided. The resulting sampling pattern in the sampled data is detectable by a comparison with the original source data.

Abstract: In a server of a public key system a list of fingerprints of public keys is stored and provided. Furthermore, a fingerprint of the fingerprint list is calculated for providing the calculated fingerprint of the list of fingerprints. A client terminal of the public key system receives a list of fingerprints of public keys and a first fingerprint thereof from a first source. The client terminal further receives a second fingerprint of the list of fingerprints from a second source and compares the first and the second received fingerprint.

Abstract: The present invention provides a service system using a certificate which is easily portable and difficult to counterfeit. The feature of the invention is to use a contactless IC chip as a portable certificate. An IC chip-attached seal is thin and small, and therefore is easily portable and distributable to a user. By integrating or attaching (or sticking) the IC chip into or on a certificate 3910, the counterfeiting of certificate 3910 becomes difficult.

Abstract: An encryption-free technique for enabling the self-authentication of value documents (including personal and commercial checks) presented at a point of purchase or financial institution. Certain data contained on the value document may be signed with a first digital signature and authenticated with a public key certificate issued from a trusted certificate authority. The signed data and public key certificate are stored on the value document, preferably in a two-dimensional bar code data format. In the case of certain personal value documents (such as checks, credit cards, passports, birth certificates, Social Security cards, etc.), a unique personal identification number (PIN) also may be included in the document data that is signed by a second digital signature.

Abstract: A secure electronic watermark inserter. A picture analyzer 3 analyzes an input picture 101, and decides the insertion strength of the electronic water marking to be inserted, from one pixel of the input picture 101 to another, to output the insertion strength information 104 to an electronic watermark pattern inserter 1 and to a shifting information pattern inserter 2. The electronic watermark pattern inserter 1 inserts an electronic watermark pattern 105, stored in an electronic watermark pattern storage unit 4, into the input picture 101. The key information pattern inserter 2 inserts the key information pattern 106, stored in the key information pattern storage unit 5, into a picture to be processed 102, having the inserted electronic watermark pattern, in accordance with the insertion strength information 104, to output the resulting picture.

Abstract: Apparatus and an accompanying method, for forming and embedding a highly tamper-resistant cryptographic identifier, i.e., a watermark, within non-marked executable code, e.g., an application program, to generate a “watermarked” version of that code. Specifically, the watermark, containing, e.g., a relatively large number of separate executable routines, is tightly integrated into a flow pattern of non-marked executable code, e.g., an application program, through randomly establishing additional control flows in the executable code and inserting a selected one of the routines along each such flow. Since the flow pattern of the watermark is highly intertwined with the flow pattern of the non-marked code, the watermark is effectively impossible to either remove from the code and/or circumvent. The routines are added in such a manner that the flow pattern of resulting watermarked code is not substantially different from that of the non-marked code, thus frustrating third party detection of the watermark using, e.

Abstract: A system and method is provided for creating and using strong passwords with high entropy. The system and method uses user generated questions and answers. To protect against an adversary from obtaining the questions and researching the answers, multiple levels of questions and answers are used. There are a first set of question(s) and a first set of answer(s) corresponding to the first set of questions as well as a second set of plurality of questions and a second set of plurality of answers corresponding to the second set of plurality of questions. The second set of plurality of answers is concatenated to form a single pass phrase. To enter the pass phrase at a client workstation, a user is presented with a plurality of entries for entering the second set of plurality of answers and an option to request a second set of plurality of questions.

Abstract: A method and system for persisting and recovering security keys in order to authorize access to a network system is disclosed. Certain security keys are read from a file with root as the effictive user id in order to enable the reading of the keys. The certain security keys are placed into a local cache by the read process. If there are no errors in the read process, the certain security keys will preferably include a private key. If the private key is not in the cache (e.g., because there was an error in the read process) the authorization fails.

Abstract: Methods, systems and computer program products are provide for controlling access to software is provided by the software to be controlled being divided into a first encrypted portion and a second unencrypted portion. The second unencrypted portion has access to, and may even incorporate, a first secret value and a software identification associated with a copy of the software. The first encrypted portion is encrypted with a first key value which is based on the first secret value and a second secret value. The second secret value is obtained and the first key value generated from the obtained second secret value and the first secret value. The first encrypted portion of the software may then be decrypted with the first key value. The software may be installed on a data processing system utilizing the decrypted first encrypted portion of the software.

Abstract: The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node.

Abstract: Disclosed are a method and an apparatus for protecting data on a storage medium by encrypting the data to be recorded on the storage medium with a password. This method comprises a step of, generating, for changing key data on each memory unit by one password, the key data, thereafter encrypting the key data with the password and writing the encrypted data to the storage medium, and a step of encrypting the data with the key data and encrypted data to the storage medium. The method further comprises a step of reading the encrypted key data from the storage medium, a step of decoding the encrypted key data with the password, and a step of decoding the data on the storage medium with the decoded key data. The encryption is done by using the key data generated separately from the password, and it is therefore feasible to prevent the password from being analyzed by decoding a cipher text.

Abstract: An information processing system has a main unit, an input device detachable from the main unit, a storage device for storing a startup password set by the input device, a startup password presence checking portion for determining whether or not the startup password is stored, and a startup password request portion for requesting an operator to set a startup password. The startup password request means: (i) requests the setting of the startup password with input unit for starting the main unit, if the input unit is connected to the main unit, and when the startup password is absent, (ii) makes the main unit start, if the input unit is connected to the main unit, and when the startup password is found present, and (iii) makes the main unit start regardless of the presence or absence of the startup password, if the input unit is not connected to the main unit.

Abstract: Methods, apparatus, and systems for power management of clustered computing platforms. Firmware provided on each platform is loaded for operating system runtime availability. The firmware traps power change events corresponding to a change in a power state of a component or device associated with a platform, such as a processor or a peripheral device. In response to the power change event, the firmware sends corresponding data to a power arbiter using an out-of-band (OOB) communication network/channel. The power arbiter determines an appropriate reallocation of power consumption allotments for the various platforms under its control based on a power management policy. Updated power consumption allocation information is then sent to selected platforms via the OOB network/channel. Upon receipt of the updated allotments, corresponding registers and/or tables are updated on the platforms to effectuate a change in power consumption of one or more components/devices associated with the platform.

Abstract: A disk array device and a method of supplying power to a disk array device to which power is supplied by at least two AC inputs are provided. Where at least two AC/DC power-supply groups are provided in correspondence with each of the AC inputs and each AC/DC power-supply group includes at least two AC/DC power supplies that are connected to the AC input corresponding to that group, outputs from the AC/DC power supplies are summed separately for each group to obtain group total outputs for each group, and the group total outputs are input to each of a plurality of loads in the disk array device to provide power to each of the loads.

Abstract: A method of state maintenance for a MMC system. The method includes using a plurality of signals, including a working voltage signal, a low voltage detection (LVD) signal, an LVD interrupt signal, a firmware polling signal, an LVD interrupt reset signal. The LVD signal responds to a voltage level of the working voltage at a preset voltage level. The LVD interrupt signal responds to the level of the LVD signal. After the LVD signal returns to the high level state and the firmware polling signal does the polling action to the LVD interrupt signal, then the LVD interrupt reset signal is issued to reset the LVD interrupt signal.

Abstract: A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

Abstract: A method of scheduling a CPU in which a clock of the CPU is controlled depending upon the states of processes to reduce power consumption. The clock is controlled by substituting clock functions of an embedded system into a scheduler function, comparting a wait time until a scheduling is completed with the sum of an execution time given for satisfying a real-time condition and an error range of a permissible error of a scheduling, changing a clock state of a process depending on the compared result, calculating an elapsed time with respect to a difference between the changed scheduling clock and a scheduling clock before the change of clock to control the wait time Wk and setting the clock of the CPU using the value of a newly determined clock.

Abstract: A mechanism that reduces power consumption of a transmitter/receiver circuit in a wireless device. The transmitter/receiver circuit is powered down to a reduced-power state after transmitting a message. The reduced-power state is too low to be able to transmit or receive information. Round trip statistics regarding how low it typically takes to receive a response to the message are then used to determine when to power up the transmitter/receiver circuit to the extent that it could receive the response. Accordingly, by being powered up for only a window of time in which the receipt of the response would likely occur, the transmitter/receiver circuit consumes less power while still likely receiving the response. The window of time may be adjusted as appropriate for the importance of the information, the performance of the specific wireless network, and the sensitivity of the wireless network to not receiving the response.

Abstract: A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

Abstract: Methods and devices for power management of graphics or other computer subsystems are disclosed. In one embodiment, graphics software components are configurable in a manner that allows them to place the graphics subsystem is a “safe” state prior to a suspend event, and back into a “working” state after a resume event, without explicit support from an operating system (OS) power management driver. When operating in the absence of an OS-supplied driver, the graphics driver receives notification of power management events, and sends a message to a support application, which then causes the graphics to enter a quiescent state by taking exclusive ownership of the display and issuing standard device-independent OS graphics calls (for a power-down event) or to relinquish display ownership (for a power-up event). From within this quiescent state the graphics may be safely power managed without adverse effects to the graphics chips and without creating any instabilities in other graphics applications.

Abstract: An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source.

Abstract: The present invention provides a method and apparatus for configuring a timing feedback path in a semiconductor device. The apparatus includes an oscillator adapted to provide a reference clock signal. The apparatus further includes at least one buffer layer adapted to receive the reference clock signal and provide a delayed clock signal, a selector adapted to select one of the delayed clock signal and the reference clock signal, and a device adapted to provide an output clock signal such that the selected one of the delayed clock signal and the reference clock signal is substantially in phase with the reference clock signal.

Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.

Abstract: A method and system for providing priority to a station in a congested half duplex Ethernet network. Specifically, one embodiment of the present invention includes a method for providing priority to a peripheral component (e.g., half duplex Network Interface Card) in a congested network. The method includes the step of detecting a collision of a data packet during transmission of the data packet by a peripheral component coupled to a network. Furthermore, the method includes the step of determining a restricted back off time. It should be appreciated that the restricted back off time is substantially equal to or less than a restricted time value. Additionally, the method includes the step of causing the peripheral component to wait the restricted back off time before trying to retransmit the data packet over the network.

Abstract: A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.

Abstract: In the data transmission system 1 for transmitting drive pulse data from a personal computer to an ink jet printer in 8-bit units, the drive pulse data includes 7 bits of pulse width data Hx and 9 bits of pulse interval data Lx. The personal computer reduces pulse interval data, which has an amount of data exceeding 8 bits, in half by shifting the bits one place to the right before transmitting the data to the inkjet printer. The basic time period used for decoding the pulse interval data is set to twice the basic time period used for decoding the pulse width data. The pulse interval data is decoded based on this larger basic time period.

Abstract: A system and method for increasing the data rate of a system bus without making modifications to existing (legacy) devices connected to the bus. A logical bus is overlaid onto one or more physical buses in a TDM manner. The overlaying is done by transmitting data into the one or more existing buses during a previously unused phase of the bus clock having no effect on existing devices connected to the buses. The additional devices are capable of latching data on either phase bus clock.

Abstract: In a computer system, a method and system for allowing customization of data collection in the event of a system error is described. In one embodiment, a Program Registration Table (PRT) contains entries associating a program name with an executable file and associated parameters. Additionally, an Error Matrix (EM) includes entries specifying which program(s) in the PRT to execute in response to a particular system error. In the event of a system error, the program(s) to execute is determined by examining the entries in the EM. The program(s) is then executed. The output from the program(s) executed may then be sent offsite for analysis. Changing the behavior of the machine in the event of a system error may be accomplished by updating entries in the PRT and EM, without the need to change any code on the system.

Abstract: A microprocessor system to correct built-in ROM code includes a program counter and an address space divided into a program ROM (read only memory) space, a small address RAM that is a subset of the program ROM, a working RAM (random access memory), and a small program RAM. When the program counter accesses instructions in the program ROM, the lower bits of the program counter are simultaneously accessing an entry in the address RAM. When a valid bit of the accessed entry indicates and the page number of the accessed entry is the same as the page number in the program counter, the jump address in the accessed entry is placed into the program counter so that corrected code in the program RAM will be executed instead of the indicated faulty code in the program ROM.

Abstract: A method for accessing data on an optical disk by a drive. The optical disk includes spare packets and data blocks. Each data block is for recording data written to the optical disk, and each spare packet has spare blocks for replacing defect blocks to record data. The drive has a memory allocated with buffers, and each buffer is for recording data of a spare packet. When writing data of a first buffer to a packet of the optical disk, if a plurality of first spare blocks are found defective, then searching a second spare packet which has spare blocks for replacing the first blocks. If the second spare packet is not read in a buffer, reading the second spare packet into a releasable buffer. After copying data written to the first spare blocks from the first buffer to the second buffer, making the first buffer releasable.

Abstract: A disk array device having two or more disk units, each disk unit including at least one disk drive, at least either of said disk units having parity bits carrying data recovery information, comprises at least one backup battery provided for each of said disk unit.

Abstract: An optical storage update module extends the life of re-writable optical medium, such as DVD+RW optical storage disks, by identifying data units having and lacking updates for information writes to commonly used portions of the optical medium and then writing the information by writing data units having updates and restricting the writing of at least some of the data units lacking updates. For instance, a stored file system structure of an optical medium, such as a UDF random writable file system, is read from the optical medium and compared with an updated file system structure to identify and write to the optical medium substantially only those data units changed by the updated file system structure. In one embodiment, file structure updates are written to the optical storage medium with Read Modify Write operations.

Abstract: A clock distribution architecture having clock and power failure protection is disclosed. In one embodiment, a computer system includes a plurality of client boards and a plurality of switch boards, as well as having power distribution boards and clock boards (referred to herein as service processor boards). In one embodiment may include a clock board and a plurality of power distribution boards, while another embodiment may include a power distribution board and a plurality of clock boards. The clock board(s) may generate a global clock signal, which may be distributed to the switch boards and the power distribution board(s). The power distribution board(s) may distribute the global clock signal to the client boards. Clock redundancy may be provide through either having multiple clock boards or multiple power distribution boards.

Abstract: A method and apparatus are provided for preventing data corruption in an information handling system when a server requests the system to perform a system management activity and the amount of battery energy remaining available to the system is not known by the requesting server. After waking up the information handling system from a sleep state, the server interrogates the system to determine the state of charge of the battery. The server considers both the remaining state of charge of the battery and the time and energy required to carry out the requested operation. If the battery has sufficient charge to carry out the particular requested operation, then the server instructs the system to carry out the particular operation. However, if the battery does not have sufficient charge to carry out the particular requested operation, then the server does not continue the requested operation or aborts the operation.

Abstract: A program-controlled unit has debug resources that outputs trace information including selected addresses, data and/or control signals and that can be used to trace the course of the operations occurring within the program-controlled. The debug resources monitor whether a predefined change in the level of one or more predefined bits of the addresses, data and/or control signals contained in the trace information has taken place, and start or terminate the generation of trace information as a function of the result of this check. Additionally or alternatively, the trace information that is output is a component of messages having a variable length portion that contains the trace information. Additionally or alternatively, the trace information that is output is a component of messages, and it is possible to determine which trace information is located at which point within the message.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: Method for diagnosing data packet transfer faults in a system under test (SUT) are provided. A representative method includes: identifying at least some portions of the data transmission paths of the SUT capable of introducing errors in data packet transfer; providing constraints defining data packet transfer relationships of at least some of the portions of the data transmission paths; and diagnosing the SUT with respect to the constraints. Systems, computer-readable media and other methods also are provided.

Abstract: A signal compensation circuit of a bus is disclosed in the present invention, wherein the amplitude of a surge is obtained by inputting a test pattern into the bus and comparing a reference voltage and a peak-value signal filtered out from the bus. For continual correction of the damping resistance, the test pattern can be inputted into the bus repeatedly to optimize the effect of the compensation. Then, a proper damping resistor is selected and connected to the bus in series to absorb the energy of the surge. The signal compensation circuit is embedded in the chip, such as in the south bridge.

Abstract: A computer processor integrated circuit has multiple functional units, where each unit is coupled to a register file for reading and writing operands. An instruction fetch unit receives instructions from a memory system and dispatches commands to the functional units. The processor has a resource status flags register wherein particular units may be marked enabled or disabled. The instruction fetch and decode unit checks the resource status flags register prior to dispatching commands and dispatches commands only to those functional units marked enabled. The instruction fetch and decode unit is capable of dispatching commands to available units, and of stalling and dispatching remaining commands in a following cycle if insufficient resources are available to simultaneously dispatch all commands necessary to execute an instruction or group of instructions.

Abstract: A system and method for identifying problems with a system configuration may evaluate system configuration information against one or more configuration recommendations or rules. The evaluated system configuration may include various types of software and hardware components which may impact the operations of the computer system. Rules may be any information identifying an issue or describing a recommended configuration for the software or hardware component. A knowledge-based language or a programming language analyzer may be used to specify the rules. In one embodiment, a rules engine may be used as part of the problem detection application to evaluate configuration data against associated rules. A rules engine may be any mechanism used to recognize, interpret and process the configuration data against the rules. The results of the evaluation process may be stored for further analysis.

Abstract: Incident report management is provided for managing received incident reports in an enterprise environment. The incident report management includes a correlator configured to determine whether a received incident report correlates with a previously received incident report, wherein received incident reports of new incidents are forwarded to a response queue.

Abstract: A system and associate method handle out-of-order data supplied by a real-time feed, and ingests the real-time feed fast enough to keep up with the feed rate while storing the data in a database in a time-ordered or other sequential manner without discarding any data. The present system adds a second unordered list for out-of-order data received from the feed or from a replay feed. A data element received from the feed, which has a time stamp earlier than the last data element placed in the ordered list, is placed in the unordered list. If replay data is received, the replay data elements are placed in the unordered list without verifying the time stamp. The data is then flushed from these memory lists to a database. Both the ordered list and the unordered list are inputted into the database. The database handles the ordering and merging of these two lists on insertion.

Abstract: A method for calculating an estimate of the clock skew between a sender's clock and a receiver's clock in a packet-based communications network. An adaptive algorithm is employed in which a recursive least squares approach is used to calculate an estimate of the clock skew based on the transmission of a given (i e., the “current”) packet, which estimate is further based on a previous estimate thereof (“a first approximation” thereof). This illustrative process then iterates with each new packet, producing increasingly accurate estimates of the clock skew.

Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.