Patents Issued in September 14, 2006
  • Publication number: 20060202186
    Abstract: A fence system including a fence member and a fence rail having a first surface with a first slot and a second surface above the first surface and having a second slot aligned with the first slot. The fence member is inserted through the first slot and the second slot.
    Type: Application
    Filed: January 18, 2006
    Publication date: September 14, 2006
    Inventors: Michael Rowley, David Kurth
  • Publication number: 20060202187
    Abstract: Embodiments of methods, apparatuses, devices, or systems for forming a photonic device are described.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: Alexander Govyadinov, Robert Bicknell
  • Publication number: 20060202188
    Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.
    Type: Application
    Filed: May 18, 2006
    Publication date: September 14, 2006
    Applicants: SHARP KABUSHIKI KAISHA, SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro Ueta, Teruyoshi Takakura, Takeshi Kamikawa, Yuhzoh Tsuda, Shigetoshi Ito, Takayuki Yuasa, Mototaka Taneya, Kensaku Motoki
  • Publication number: 20060202189
    Abstract: A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: May 30, 2006
    Publication date: September 14, 2006
    Applicant: RJ Mears, LLC
    Inventor: Richard Blanchard
  • Publication number: 20060202190
    Abstract: The present invention relates to aromatic amine derivatives having a specific structure in which a substituted anthracene structure is bonded to an amine structure substituted with benzene rings having substituent groups; and organic electroluminescence devices comprising a cathode, an anode and one or plural organic thin film layers having at least a light emitting layer which are sandwiched between the cathode and the anode wherein at least one of the organic thin film layers contains the above aromatic amine derivative in the form of a single substance or a component of a mixture. There are provided organic electroluminescence devices having a high luminance of light emitted and a high efficiency of blue light emission and exhibiting a long life, as well as novel aromatic amine derivatives capable of realizing such organic electroluminescence devices.
    Type: Application
    Filed: January 13, 2004
    Publication date: September 14, 2006
    Inventor: Masakazu Funahashi
  • Publication number: 20060202191
    Abstract: Semiconductor devices are described that include a semiconductor layer that comprises a perfluoroether acyl oligothiophene compound, preferably an ?,?-bis-perfluoroether acyl oligothiophene compound. Additionally, methods of making semiconductor devices are described that include depositing a semiconductor layer that contains a perfluoroether acyl oligothiophene compound, preferably an ?,?-bis(2-perfluoroether acyl oligothiophene compound.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 14, 2006
    Inventors: Christopher Gerlach, David Ender, Dennis Vogel
  • Publication number: 20060202192
    Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the passive layer and the second electrode. In undertaking an operation on the memory device, ions moves into within and from within the active layer, and the active layer is oriented so that the atoms of the active layer provide minimum obstruction to the movement of the ions into, within and from the active layer.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Juri Krieger, Stuart Spitzer
  • Publication number: 20060202193
    Abstract: Optoelectronic materials are provided that are bistable organic tautomeric compositions that intraconvert dithio or diseleno carbamate esters and cyclic 1,3-dithia- or -diselena-2-iminium salts of ?-conjugated bis-anthracenyl compounds. Specifically disclosed are compounds having the formula: where X is sulfur or selenium; where the R and R1 groups are alkyl or alkyl that together form a ring of carbon atoms; where An is the anion of a strong acid; and where the Z element is a chiral ring-completing system of atoms that changes chirality on tautomerization. These molecules are in themselves molecular-sized optoelectronic switching devices.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 14, 2006
    Inventors: Robert Schumaker, James Marek, James Parakka
  • Publication number: 20060202194
    Abstract: Red phosphorescene compounds and organic electro-luminescence device using the same are disclosed. In an organic electroluminescence device including an anode, a hole injecting layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injecting layer, and a cathode serially deposited on one another, the organic electroluminescence device may use a compound as a dopant of the light emitting layer.
    Type: Application
    Filed: May 13, 2005
    Publication date: September 14, 2006
    Inventors: Hyun Jeong, Chun Park, Jeong Seo, Kyung Lee, Jae Lee, Jung Kim
  • Publication number: 20060202195
    Abstract: Dielectric compositions comprising siloxane and polymeric components, as can be used in a range of transistor and related device configurations.
    Type: Application
    Filed: December 22, 2005
    Publication date: September 14, 2006
    Inventors: Tobin Marks, Antonio Facchetti, Myung-Han Yoon, He Yan
  • Publication number: 20060202196
    Abstract: A thin film field effect transistor is disclosed that includes a gate electrode, a gate insulator film the on gate electrode, and a first organic electronic material film containing a first organic electronic material on the gate insulator film. A source electrode and a drain electrode are spaced apart from each other on the first organic electronic material film. The first organic electronic material film includes a portion between the source electrode and the drain electrode that is in contact with the gate insulator film. This portion provides a current path. The current is controlled by the potential of the gate electrode. There is a second organic electronic material film that is in contact with the surface of first organic electronic material film opposite to the portion that provides the current path. The second organic electronic material film contains a second organic electronic material and an electron acceptor or an electron donor.
    Type: Application
    Filed: January 20, 2006
    Publication date: September 14, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Haruo Kawakami, Hisato Kato, Takahiko Maeda, Nobuyuki Sekine
  • Publication number: 20060202197
    Abstract: A platinum complex represented by the general formula 1, useful as a phosphorescence emission material, a tetradentate ligand useful for synthesizing the platinum complex, and a light-emitting device containing at least one of the platinum complex. In the general formula 1, two of the rings A, B, C, and D each independently represent an aromatic ring or an aromatic heterocyclic ring, while the other two rings each represent a nitrogen-containing heterocyclic ring; RA-D represent the substituents; each the rings A and B, the rings B and C, and the rings C and D may be bound to each other to form a fused ring independently via the substituent RA-D; XA-D each represent a carbon atom or nitrogen atom; Q represents a bivalent atom or atomic group; Y represents a carbon or nitrogen atom; and n is an integer of 0 to 3.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 14, 2006
    Inventors: Yuji Nakayama, Hisanori Ito, Takeshi Iwata, Junji Nakamura, Yoshimasa Matsushima
  • Publication number: 20060202198
    Abstract: Embodiments of the invention relate to an integrated circuit comprising an organic semiconductor, particularly an organic field effect transistor (OFET) that is provided with a dielectric layer. The integrated circuit is produced by means of a polymer formulation consisting of a) 100 parts of at least one crosslinkable basic polymer, b) 10 to 20 parts of at least one electrophilic crosslinking component, c) 1 to 10 parts of at least one thermal acid catalyst that generates an activating proton at temperatures ranging from 100 to 150° C., dissolved in d) at least one solvent. Other embodiments of the invention further relate to a method for producing an integrated circuit, which makes it possible to produce integrated circuits comprising dielectric layers, especially for OFET's at low temperatures.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 14, 2006
    Inventors: Marcus Halik, Hagen Klauk, Guenter Schmid, Andreas Walter, Ute Zschieschang
  • Publication number: 20060202199
    Abstract: An organic thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a data line disposed on the substrate; an insulating layer disposed on the data line and having a contact hole exposing the data line; a first electrode disposed on the insulating layer and connected to the data line through the contact hole; a second electrode disposed on the insulating layer; an organic semiconductor disposed on the first and the second electrodes; a gate insulator disposed on the organic semiconductor; and a gate electrode disposed on the gate insulator.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 14, 2006
    Inventors: Bo-Sung Kim, Yong-Uk Lee, Mun-Pyo Hong
  • Publication number: 20060202200
    Abstract: An organic thin film transistor array panel includes a substrate, a data line disposed on the substrate, a gate line intersecting the data line and including a gate electrode, a gate insulating layer disposed on the gate line and having a contact hole exposing the data line, a first electrode disposed on the gate insulating layer and electrically connected to the data line through the contact hole, a second electrode disposed opposite the first electrode with respect to the gate electrode, an organic semiconductor disposed on and contacting the first and the second electrodes, and a conductive stopper disposed on the organic semiconductor.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 14, 2006
    Inventors: Keun-Kyu Song, Yong-Uk Lee, Bo-Sung Kim, Mun-Pyo Hong
  • Publication number: 20060202201
    Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.
    Type: Application
    Filed: May 15, 2006
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Shigeyuki Maruyama
  • Publication number: 20060202202
    Abstract: A pixel structure includes pixel electrodes and switching elements which correspond to the pixel electrodes. The pixel electrodes and the switching elements are formed on the same substrate, and each pixel electrode is provided in a layer on the substrate, not on a semiconductor layer of the switching element.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 14, 2006
    Inventors: Atsushi Denda, Yoichi Noda
  • Publication number: 20060202203
    Abstract: The invention provides a TFT electrode structure and its manufacturing method that can prevent metal diffusion occurring in the fabrication of a TFT, and thereby reduce the risk of contamination of the chemical vapor deposition process due to metallic ion diffusion. The transparent pixel electrode is formed after the gate electrode metal so that the pixel transparent electrode can be used as a barrier layer to prevent metal diffusion under high temperature from the gate electrode metal to adjacent insulating layers or the active layer. Further, the method used to form the transparent pixel electrode is a low-temperature physical vapor deposition process, which affected less by the processing environment, and the transparent pixel electrode is a conductive layer that is not affected by metal diffusion.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 14, 2006
    Inventors: Cheng-Chung Chen, Yu-Chang Sun, Yi-Hsun Huang, Chien-Wei Wu, Shuo-Wei Liang, Chia-Hsiang Chen, Chi-Shen Lee, Chai-Yuan Sheu, Yu-Chi Lee, Te-Ming Chu, Cheng-Hsing Chen
  • Publication number: 20060202204
    Abstract: The present invention relates to a TFT, a TFT array panel, and a method of manufacturing the TFT array panel. A method of manufacturing the TFT array panel includes the steps of forming a first electrode and a second electrode that are separated from each other on a substrate, forming a silicon layer including amorphous silicon and polycrystalline silicon on the substrate, forming a semiconductor by patterning the silicon layer, forming a gate insulating layer on the semiconductor, forming a third electrode that is opposite to the semiconductor on the gate insulating layer, forming a passivation layer on the third electrode, and forming a pixel electrode on the passivation layer. The TFT array panel has high mobility because the TFT include polycrystalline silicon at the channel region of the TFT.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 14, 2006
    Inventors: Joon-Hoo Choi, Joon-Chul Goh, Beohm-Rock Choi
  • Publication number: 20060202205
    Abstract: An organic electroluminescent device includes first and second substrates facing and spaced apart from each other, the first and second substrates including a pixel region; a gate line on an inner surface of the first substrate; a data line crossing the gate line; a switching thin film transistor connected with the gate line and the data line; a driving thin film transistor connected with the switching thin film transistor; a power line connected with the driving thin film transistor; a first electrode on an inner surface of the second substrate; a first sidewall and a second sidewall on the first electrode at a boundary of the pixel region, the first sidewall and the second sidewall spaced apart from each other; an electroluminescent layer on the first electrode in the pixel region; a second electrode on the electroluminescent layer in the pixel region; and a connection electrode electrically connected to the first and second substrates.
    Type: Application
    Filed: May 9, 2006
    Publication date: September 14, 2006
    Inventors: Jae-Yoon Lee, Kyung-Man Kim, Jae-Yong Park, Choong-Keun Yoo, Ock-Hee Kim
  • Publication number: 20060202206
    Abstract: An object of the present invention is to provide a semiconductor device which has flexibility and resistance to a physical change such as bending and a method for manufacturing the semiconductor device. A semiconductor device of the present invention includes a plurality of transistors provided over a flexible substrate, each of which has a semiconductor film, a gate electrode provided over the semiconductor film with a gate insulating film therebetween, and an interlayer insulating film provided to cover the gate electrode, and a bending portion provided between the plurality of transistors, in which the bending portion is provided by filling an opening formed in the interlayer insulating film with a material having a lower elastic modulus, a material having a lower glass transition point, or a material having a higher plasticity than that of the interlayer insulating film.
    Type: Application
    Filed: February 16, 2006
    Publication date: September 14, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Koji Dairiki, Susumu Okazaki, Yoshitaka Moriya, Shunpei Yamazaki
  • Publication number: 20060202207
    Abstract: The present invention provides an image display device, by which it is possible to prevent dielectric breakdown between a bottom electrode and a top electrode (top electrode bus line), which make up thin-film type electron sources, and which is free of display defect and has longer service life. On a cathode substrate 10, a bottom electrode 11, a tunneling insulator 12, and a top electrode 13 are prepared. On a lower layer of the top electrode 13, a top electrode bus line 16 is formed, and the top electrode 13 is reliably connected to the top electrode bus line 16 via a contact electrode 15. A field insulator 12A, a lower layer 14a of the interlayer insulator deposited by sputtering and an upper layer 14b of the interlayer insulator are laminated between the top electrode 13 and the contact electrode and the bottom electrode 11, and the bottom electrode 11 is insulated from the top electrode 13 (top electrode bus line 16).
    Type: Application
    Filed: January 6, 2006
    Publication date: September 14, 2006
    Inventors: Masakazu Sagawa, Toshiaki Kusunoki, Kazutaka Tsuji, Mutsumi Suzuki
  • Publication number: 20060202208
    Abstract: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line (1). The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular surface provided with dotted or linear protrusions, which makes it possible to control the grain boundary lines. As such, an inexpensive and high-quality silicon plate can be provided. Further, by employing this silicon plate to produce a solar cell, an inexpensive and high-quality solar cell can be provided as well.
    Type: Application
    Filed: April 28, 2006
    Publication date: September 14, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Yoshihiro Tsukuda
  • Publication number: 20060202209
    Abstract: A method and apparatus for limiting net curvature in a substrate is provided. A layer is formed on one side of a substrate to limit curvature that may be introduced in the substrate by formation of a thermal spreading layer on an opposing side of the substrate. For example, introduction of a diamond layer on a substrate to dissipate thermal energy away from a semiconductor layer may introduce tensile or compressive stress in the substrate and result in undesirable bowing and/or warping of the substrate. To limit this curvature, a curvature limiting layer, e.g. another diamond layer, may be formed on subjacent to the substrate.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 14, 2006
    Inventors: Maxim Kelman, Shriram Ramanathan, Kramadhati Ravi
  • Publication number: 20060202210
    Abstract: There is disclosed a system and method for increasing heat dissipation of LED displays by using the current PCB packaging mounted to a LCD panel support structure thereby eliminating the need for a metal core PCB. In one embodiment, reverse mounted LEDs having heat dissipation pads are used to optimize heat transfer to a metal layer which is then placed in contact with the LCD support structure.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Inventors: Thye Mok, Siew Tan, Shin Ng
  • Publication number: 20060202211
    Abstract: A light-emitting device includes an element structure including at least two semiconductor layers having mutually different conductivity types. A transparent p-side electrode of ITO is formed on the element structure. A bonding pad is formed on a region of the p-side electrode. An n-side electrode made of Ti/Au is formed on the surface of the element structure opposite to the p-side electrode. A metal film made of gold plating with a thickness of about 50 ?m is formed, using an Au layer in the n-side electrode as an underlying layer.
    Type: Application
    Filed: May 15, 2006
    Publication date: September 14, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tetsuzo Ueda, Masaaki Yuri
  • Publication number: 20060202212
    Abstract: A semiconductor optical device comprises a lower cladding layer of a first conductive type, an upper cladding layer of a second conductive type, and an active layer. The lower cladding layer has a first region and a second region. The first region extends in a direction of a predetermined axis, and the second region is located adjacent to the first region. The active layer is provided between the first region of the lower cladding layer and the upper cladding layer. The thickness of the active layer is changed in the direction such that TM mode gain and TE mode gain are substantially equal to each other.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 14, 2006
    Inventor: Jun-ichi Hashimoto
  • Publication number: 20060202213
    Abstract: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission test. If a defective device is detected in this test, a repair device is mounted at a position corresponding to a position of the defective device. At this time, after wiring lines connected to the defective device are cut off, the repair device is electrically connected to portions of the wiring lines, the portions of the wiring lines being located at positions nearer to the drive circuit side than the cut-off positions of the wiring lines.
    Type: Application
    Filed: May 25, 2006
    Publication date: September 14, 2006
    Applicant: SONY CORPORATION
    Inventors: Toyoharu Oohata, Toshiaki Iwafuchi, Hisashi Ohba
  • Publication number: 20060202214
    Abstract: Provided are an organic thin film transistor providing smoother movement of holes between a source electrode or a drain electrode and a p-type organic semiconductor layer, and a flat panel display device including the organic thin film transistor. The organic thin film transistor includes a substrate, a gate electrode disposed on the substrate, a p-type organic semiconductor layer insulated from the gate electrode, a source electrode and a drain electrode separated from each other and insulated from the gate electrode, and a hole injection layer interposed between the source and drain electrodes and the p-type organic semiconductor layer.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 14, 2006
    Inventor: Nam-Choul Yang
  • Publication number: 20060202215
    Abstract: A device structure includes a III-nitride wurtzite semiconductor light emitting region disposed between a p-type region and an n-type region. A bonded interface is disposed between two surfaces, one of the surfaces being a surface of the device structure. The bonded interface facilitates an orientation of the wurtzite c-axis in the light emitting region that confines carriers in the light emitting region, potentially increasing efficiency at high current density.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: Jonathan Wierer, M. Craford, John Epler, Michael Krames
  • Publication number: 20060202216
    Abstract: A semiconductor light emitting device comprises: a semiconductor multilayer structure; and an aluminum nitride layer. The semiconductor multilayer structure includes a light emitting layer that emits a light. The aluminum nitride layer is provided on a surface of the semiconductor multilayer structure. The aluminum nitride layer has asperities with an average pitch of not more than half an in-medium wavelength of the light in aluminum nitride. Alternatively, the semiconductor light emitting device may have asperities composed of a plurality of protrusions including the aluminum nitride layer and a plurality of depressions intruding into the semiconductor multilayer structure.
    Type: Application
    Filed: February 23, 2006
    Publication date: September 14, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shuji Itonaga
  • Publication number: 20060202217
    Abstract: A nitride semiconductor light emitting device includes a substrate for growing a gallium nitride-based semiconductor material, an n-type nitride semiconductor layer on the substrate, an active layer on the n-type nitride semiconductor layer such that a predetermined portion of the n-type nitride semiconductor layer is exposed, a p-type nitride semiconductor layer on the active layer, a transparent electrode layer on the p-type nitride semiconductor layer so as to be in an ohmic contact with the p-type nitride semiconductor layer, a p-side bonding pad in the form of a bi-layer of Ta/Au on the transparent electrode layer, and an n-side electrode in the form of a bi-layer of Ta/Au on the exposed portion of the n-type nitride semiconductor layer.
    Type: Application
    Filed: May 10, 2006
    Publication date: September 14, 2006
    Inventors: Jae Ro, Sang Cho, Seung Chae
  • Publication number: 20060202218
    Abstract: A light emitting diode includes a light emitting body, a lead frame supplying power to the light emitting body and a light transmitting resin covering the light emitting body and part of the lead frame. The top surface of the light transmitting resin is formed as a plane at a position that satisfies a condition in which part of radiated light from the light emitting body is totally reflected. An inclined surface is formed at a position that satisfies a condition in which part of the radiated light is refracted in a downward direction away from a line perpendicular to the inclined surface.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 14, 2006
    Inventors: Seiya Uemura, Atsushi Shinohara
  • Publication number: 20060202219
    Abstract: A semiconductor light emitting device comprises: a substrate; a semiconductor stacked structure; a first electrode; a second electrode; and a reflective film. The substrate has a top face and a rear face electrode forming portion opposed thereto, and is translucent to light in a first wavelength band. The rear face electrode forming portion is surrounded by a rough surface. The semiconductor stacked structure is provided on the top face of the substrate and includes an active layer that emits light in the first wavelength band. The first electrode is provided on the semiconductor stacked structure, and the second electrode is provided on the rear face electrode forming portion. The reflective film is coated on at least a portion of the rough surface.
    Type: Application
    Filed: June 3, 2005
    Publication date: September 14, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichi Ohashi, Yasuharu Sugawara, Shuji Itonaga, Yasuhiko Akaike
  • Publication number: 20060202220
    Abstract: A method for manufacturing a display device and a display device manufactured thereby are provided. The above method has the steps of forming a first resin material on a base substrate so as to surround a region in which light-emitting devices are provided, applying a second resin material in the region surrounded by the first resin material, initiating polymerization of at least one of the above resin materials, adhering the base substrate to the sealing substrate with the above two resin materials provided therebetween after the polymerization is initiated so as to seal the light-emitting devices in the second resin material, and curing the first resin material and the second resin material by promoting the polymerization.
    Type: Application
    Filed: February 15, 2006
    Publication date: September 14, 2006
    Inventor: Naoki Hayashi
  • LED
    Publication number: 20060202221
    Abstract: A LED comprises a base body. The base body carries a light generating element. A light guide body is provided in the emitting direction of the light generating element. According to the invention, the light guide body comprises diffractive groups of light guide elements to fix the emission angle of the LED.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 14, 2006
    Inventor: Martin Klenke
  • Publication number: 20060202222
    Abstract: A package structure of organic electroluminescent device comprises at least one isolating wall and at least one squeeze-out channel provided under a package lid. The adhesive coating place and squeeze-out area as laminating are able to be defined in package process due to the isolating wall and squeeze-out channel provided, therefore, which is not only to prevent the adhesive squeezed out from package process to protect the emitting element within the package lid, but also prevent the adhesive squeezing out of the package lid to the saw street to affect the further cutting process.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 14, 2006
    Inventors: Wen-Jeng Lan, Chien-Yuan Feng, Yuan-Chang Tseng, Ting-Chou Chen, Sheng-Hsu Shih, Chien-Chih Chiang, Chih-Ping Lin
  • Publication number: 20060202223
    Abstract: In a method for fabricating a flip-chip light emitting diode device, a submount wafer is populated with a plurality of the light emitting diode dies. Each device die is flip-chip bonded to the submount. Subsequent to the flip-chip bonding, a growth substrate is removed. The entire submount is immersed in the etchant solution, exposed to the light for a prespecified period of time, removed from the solution, dried and diced into a plurality of LEDs., The LEDs are immediately packaged without any further processing.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 14, 2006
    Inventors: Michael Sackrison, Hari Venugopalan, Xiang Gao
  • Publication number: 20060202224
    Abstract: A substrate structure for light-emitting diode module includes a highly heat-radiating metal substrate, a plurality of isolating islands formed on a top surface of the metal substrate only at positions and/or paths for forming required conducting circuits, and a plurality of conduction islands separately formed on the isolating islands to constitute the required circuits on the metal substrate. At least one light emitting diode is mounted on the metal substrate with a heat radiating and conducting package section at a bottom thereof directly attaching to the top surface of the metal substrate, and two external electrode leads at an outer side of the package section electrically connected to corresponding conducting islands, so as to form a light-emitting diode module on the metal substrate.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Inventor: Julian Lee
  • Publication number: 20060202225
    Abstract: Disclosed herein is a submount to mount a light emitting diode in a flipchip-structured light emitting device. The submount including a transistor to mount a nitride semiconductor light emitting diode in a flipchip-structured light emitting device includes: a substrate made of a first conductive semiconductor material; a first region formed on a partial area of the substrate, and made of a second conductive semiconductor material; a second region formed on the remaining regions other than the first region, and made of the second conductive semiconductor material; first and second electrodes formed on the first and second regions, respectively; and a conductive layer formed on the back of the substrate, wherein the first and second electrodes are connected to an n-type electrode and a p-type electrode of the nitride semiconductor light emitting diode through the use of a bump.
    Type: Application
    Filed: May 10, 2006
    Publication date: September 14, 2006
    Inventors: Hyun Kim, Hyuk Lee, Hyoun Shin, In Pyeon
  • Publication number: 20060202226
    Abstract: A single or multi-color light emitting diode (LED) with high extraction efficiency is comprised of a substrate, a buffer layer formed on the substrate, one or more patterned layers deposited on top of the buffer layer, and one or more active layers formed on or between the patterned layers, for example by Lateral Epitaxial Overgrowth (LEO), and including one or more light emitting species, such as quantum wells. The patterned layers include a patterned, perforated or pierced mask made of insulating, semiconducting or metallic material, and materials filling holes in the mask. The patterned layer acts as an optical confining layer due to a contrast of a refractive index with the active layer and/or as a buried diffraction grating due to variation of a refractive index between the mask and the material filling the holes in the mask.
    Type: Application
    Filed: February 28, 2005
    Publication date: September 14, 2006
    Inventors: Claude Weisbuch, Aurelien David, James Speck, Steven DenBaars
  • Publication number: 20060202227
    Abstract: Disclosed herein is a vertical type nitride semiconductor light emitting diode. The nitride semiconductor light emitting diode comprises an n-type nitride semiconductor layer, an active layer formed under the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed under the active layer, and an n-side electrode which comprises a bonding pad formed adjacent to an edge of an upper surface of the n-type nitride semiconductor layer and at least one extended electrode formed in a band from the bonding pad. The bonding pad of the n-side electrode is formed adjacent to the edge of the upper surface of the n-type nitride semiconductor layer acting as a light emitting surface, thereby preventing a wire from shielding light emitted from the active layer. The extended electrode can be formed in various shapes, and prevents concentration of current density, thereby ensuring effective distribution of the current density.
    Type: Application
    Filed: June 16, 2005
    Publication date: September 14, 2006
    Inventors: Dong Kim, Yong Kim, Hyun Kim
  • Publication number: 20060202228
    Abstract: A semiconductor device is provided which comprises a heat-radiative support plate 5; and first and second semiconductor elements 1 and 2 mounted and layered on support plate 5 for alternate switching of first and second semiconductor elements 1 and 2. The arrangement of piling and securing first and second semiconductor elements 1 and 2 on support plate 5 improves integration degree of semiconductor elements 1 and 2, and reduces the occupation area on support plate 5. Alternate switching of first and second semiconductor elements 1 and 2 controls heat produced from first and second semiconductor elements 1 and 2 because one of first and second semiconductor elements 1 and 2 is turned on, while the other is turned off.
    Type: Application
    Filed: May 27, 2004
    Publication date: September 14, 2006
    Inventor: Masaki Kanazawa
  • Publication number: 20060202229
    Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).
    Type: Application
    Filed: February 12, 2004
    Publication date: September 14, 2006
    Inventors: Rob Van Dalen, Prabhat Agarwal, Jan Slotboom, Gerrit Koops
  • Publication number: 20060202230
    Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.
    Type: Application
    Filed: March 1, 2006
    Publication date: September 14, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hidekichi Shimura
  • Publication number: 20060202231
    Abstract: Disclosed are a design method and apparatus in which information regarding a cell is input, the cell having taps in a substrate surface, for supplying the potentials of respective ones of wells in which active elements are formed, and source diffusion regions in the substrate surface, conductivity types thereof being opposite those of the wells. The taps are converted to conductivity types identical with those of the source diffusion regions to obtain source regions and freely set the well potentials of the cell to any potentials. If the cell is one having shorting portions electrically connecting taps and sources and the shorting portions are diffusion regions of the same conductivity type as that of the taps, then the shorting portions are converted to conductivity types identical with those of the source diffusion regions to obtain source regions.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 14, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroshi Yamamoto
  • Publication number: 20060202232
    Abstract: A memory control unit includes fuses that are selectively blown to set a manufacturer's identification code (ID), and a further fuse that is selectively blown to designate the memory control unit as a general-purpose unit or a custom unit. When designated as a custom unit, the memory control unit uses the manufacturer's ID to protect data in the memory by scrambling the data, or by comparing the manufacturer's ID with an input ID and disabling access to the memory if the ID's do not match. A semiconductor integrated circuit chip including the memory control unit can thus be fuse-programmed for either general-purpose use or custom use.
    Type: Application
    Filed: February 9, 2006
    Publication date: September 14, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Isao Takami
  • Publication number: 20060202233
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer having a channel region, a strain generating layer to cause strain in the channel region by applying a stress to the channel region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity region containing nitrogen, oxygen, or boron as impurities is provided in the semiconductor layer or the strain generating layer.
    Type: Application
    Filed: June 28, 2005
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Publication number: 20060202234
    Abstract: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm?3 to 5.0×1019 cm?3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018 cm?3 to 5.0×1019 cm?3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.
    Type: Application
    Filed: February 27, 2006
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Publication number: 20060202235
    Abstract: A solid-state imaging apparatus includes a semiconductor substrate, a photoelectric converter which is formed in a surface region of the semiconductor substrate and converts light into signal charges, and reading electrodes which read out the signal charges and supply the signal charges to a signal sensor. At least some of the reading electrodes are arranged adjacent to the circumference of an image-forming region with a fixed distance between the circumference and the center of the photoelectric converter.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 14, 2006
    Inventor: Hisanori Ihara