Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

Abstract: A lateral metal-insulator-metal capacitor fabricated with consistent dummy fill and slotting patterns that assure predictable and controlled performance from the metalization layout while conforming to process design rules.

Abstract: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.

Abstract: A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a device isolation region; burying a first oxide film at a side wall of the pillar on the device isolation region; forming a second oxide film on an upper part of the pillar; and removing an upper part of the first oxide film using the second oxide film as a mask, thereby exposing an upper surface and an upper part of the side wall of the pillar; and the method, comprising forming a conductive material on the exposed upper surface and the exposed upper part of the side wall of the pillar, thereby forming a surface strap that electrically connects the capacitor and the second activation region.

Abstract: An atomic layer deposited ZrAlxOy dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a zirconium-containing precursor onto a substrate, pulsing a first oxygen-containing precursor, pulsing an aluminum-containing precursor, and pulsing a second oxygen-containing precursor to form ZrAlxOy by atomic layer deposition provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide and with a relatively low leakage current. Dielectric layers containing atomic layer deposited ZrAlxOy are thermodynamically stable such that the ZrAlxOy will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.

Abstract: Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Abstract: A method of forming a MOS transistor is disclosed. An example method forms an insulating film and a first silicon layer on a semiconductor substrate in order. The example method forms an impurity region by injecting impurity ions into a predetermined region of the first silicon layer, forms a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer. The example method also forms a gate oxide over whole surfaces of the first silicon layer and the common source line, forms side walls made of insulating film on the gate oxide film positioned at sides of the common source line, forms drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line, and forms gate electrodes on sides of the side walls.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract: A semiconductor device of MCM type allowing high-density assembly and a process of fabricating the same is provided. There are provided semiconductor chips mounted on a supporting substrate and incrusted in an insulation film on the supporting substrate and wiring formed in the insulation film so as to connect to each semiconductor chip through connection holes provided in the insulation film. Then, an interlayer dielectric covers such wiring that is connected to an upper layer wiring, through connection holes provided in such interlayer dielectric. In addition, an upper layer insulation film covers the upper layer wiring, and an electrode, connected to such upper layer wiring through another connection hole, is provided on such upper layer insulation film.

Abstract: A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.

Abstract: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented.

Abstract: A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.

Abstract: Disclosed is a method of in-wafer testing of integrated optical components and in-wafer chips with photonic integrated circuits (PICs).

Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.

Abstract: A semiconductor element is formed in a semiconductor wafer, and a groove is formed by performing half-cut dicing on the semiconductor wafer along a dicing line. A dicing region of the semiconductor wafer is irradiated with a laser beam to melt or vaporize a cutting streak formed by dicing. An adhesive tape is adhered to the semiconductor element formation surface of the semiconductor wafer, and the other side of the semiconductor element formation surface is ground to at least a depth reaching the groove.

Abstract: A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.

Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

Abstract: The present invention relates to a method for fabricating a single crystal silicon thin film at the desired location to the desired size from an amorphous or polycrystalline thin film on a substrate using laser irradiation and laser beam movement along the substrate having the semiconductor thin films being irradiated. This method comprises the steps of: forming a semiconductor layer or a metal thin film on a transparent or semi-transparent substrate; forming a single crystal seed region on the substrate of the desired size by a crystallization method using laser irradiation; and converting the desired region of the semiconductor layer or metal thin film into a single crystal region, using the single crystal seed region.

Abstract: A laser irradiation method using a laser crystallization method which can heighten an efficiency of substrate processing as compared to a conventional one and also heighten mobility of a semiconductor film is provided. It is an irradiation method of a laser beam in which, pattern information of a sub-island formed on a substrate is stored, and a beam spot of a laser beam is condensed so as to become linear, and by use of the stored pattern information, a scanning path of the beam spot is determined so as to include the sub-island, and by moving the beam spot along the scanning path, the laser beam is irradiated to the sub-island, characterized in that on the occasion of scanning the beam spot, when the beam spot has reached to the sub-island, the beam spot and the sub-island are contacted at a plurality of points.

Abstract: In annealing a non-single crystal silicon film through the use of a linear laser beam emitted by a YAG laser of a light source, it is the object of the present invention to prevent heterogeneity in energy caused by an optical interference produced in the linear laser beam from having an effect on the silicon film. The laser beam is divided by a mirror 604 shaped like steps into laser beams which have an optical path difference larger than the coherence length of the laser beam between them. The divided laser beams are converged on an irradiate surface 611 by the action of a cylindrical lens array 605 and a cylindrical lens 606 to homogenize the energy of the laser beam in the length direction and to determine the length of the linear laser beam.

Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.

Abstract: A method for forming P-N junctions in a semiconductor wafer includes ion implanting dopant impurities into the wafer and annealing the wafer using a thermal flux laser annealing apparatus that includes an array of semiconductor laser emitters arranged in plural parallel rows extending along a slow axis, plural respective cylindrical lenses overlying respective ones of the rows of laser emitters for collimating light from the respective rows along a fast axis generally perpendicular to the slow axis, a homogenizing light pipe having an input face at a first end for receiving light from the plural cylindrical lenses and an output face at an opposite end, the light pipe comprising a pair of reflective walls extending between the input and output faces and separated from one another along the direction of the slow axis, and scanning apparatus for scanning light emitted from the homogenizing light pipe across the wafer in a scanning direction parallel to the fast axis.

Abstract: A gate electrode is formed above an n-type well including an n-type threshold voltage adjustment region, ions of p-type impurity are implanted with a low acceleration energy to form extension regions in the n-type well on both sides of the gate electrode, side wall spacers are formed on the side walls of the gate electrode, ions of p-type impurity are implanted with a small dose causing substantially no abnormal tailing in the gate electrode and with a relatively high acceleration energy to form p-type source/drain regions deeper than the threshold adjustment region, ions of atoms are implanted into the semiconductor substrate to change the upper parts of the gate electrode and the source/drain regions to amorphous state, ions of p-type impurity are implanted with a large dose to form high-concentration parts in the source/drain regions, and the impurities introduced by the ion implantation are activated.

Abstract: Methods for forming conductive layers. A layer of metal composite is applied on a substrate, comprising a plurality of metal flakes, a plurality of nanometer metal spheres, and a plurality of mixed metal precursors. The plurality of mixed metal precursors comprises a mixture of inorganic salts and organic acidic salts. The layer of metal composite is cured to induce an exothermic reaction, thereby forming a conductive layer on the substrate at a relatively low temperature (<200° C.

Abstract: A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

Abstract: Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Abstract: According to one embodiment of the invention, a method of packaging ball grid arrays includes providing a substrate having a plurality of holes formed therein. Each hole is associated with a respective one of a plurality of contact pads formed on a first surface of the substrate. The method further includes disposing a plurality of balls within respective ones of the plurality of holes such that at least a portion of each ball projects outwardly from the first surface, and applying a force to each of the balls from above the first surface to couple the balls to the substrate.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: An Al3Ti film having a large amount of dissolved Si is deposited on a semiconductor substrate to form a laminate with an Al wiring film, and heat treatment is performed at a temperature of at least 400° C., to thereby absorb excessive Si into the Al3Ti film and so prevent the occurrence of Si nodules. By depositing Al film at a temperature of at least 400° C. at the time of depositing the Al wiring film on the Al3Ti film, excessive Si is caused to be absorbed in the Al3Ti film. Further, at the time of depositing a Ti film on the semiconductor substrate and depositing the Al wiring film, the Al film is deposited at a temperature of a least 400° C., there is reaction between the Ti film within the laminate, causing an Al3Ti film to be produced, and excessive Si is absorbed in the Al3 Ti film produced.

Abstract: A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k?2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.

Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

Abstract: A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CxHy layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.

Abstract: Disclosed is a method for forming a metal interconnection line in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate, the inter-layer insulation layer having at least one contact hole exposing a portion of the substrate; forming a barrier metal layer on a bottom of said at least one contact hole and an upper surface of the inter-layer insulation layer; forming an amorphous seed layer on said at least one contact hole; converting portions of the seed layer disposed on an upper part of said at least one contact hole into a metal deposition blocking layer; selectively forming at least one adhesion layer on the bottom and sidewalls of said at least one contact hole by using the seed layer; and selectively forming at least one plug inside of said at least one contact hole.

Abstract: The present invention is directed to a process for producing structures containing metallized features for use in microelectric workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and the metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming an interconnect are described.

Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.

Abstract: In a method of manufacturing a semiconductor device, a tungsten layer pattern having an oxidized surface is formed on a substrate. A source gas including silicon is provided to the oxidized surface of the tungsten layer pattern to form a protecting layer on the oxidized surface of the tungsten layer pattern. The protecting layer prevents an abnormal growth of oxide contained in the oxidized surface. The protecting layer prevents a whisker from growing from the oxidized surface of the tungsten layer pattern.

Abstract: A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to initially deposit a thin underlying, first component of the barrier layer, while an atomic layer deposition (ALD), procedure is then employed for deposition of an overlying second barrier layer component. The underlying, thin barrier layer component obtained via PVD procedures is comprised with the desired properties needed to interface the porous, low k layer, while the overlying barrier layer component obtained via ALD procedures exhibits excellent thickness uniformity.

Abstract: The present invention relates to plasma etching in which O2 gas is added with He gas as a main component. At an early stage of a plasma discharge, Cl2 gas is added and thereafter the supply of the Cl2 gas is stopped. A small amount of Cl2 gas is added in advance before the discharge start and thereafter the discharge is started.

Abstract: A method for etching a feature in an etch layer through a mask over a substrate. The substrate is placed in a process chamber. An etch plasma is provided to the process chamber, where the etch plasma begins to etch. A feature is etched in the etch layer with the etch plasma. At least one etch plasma parameter is ramped during the etching of the feature to optimize plasma parameters with the changing etch depth and the feature is etched with the ramped plasma until the feature is etched to a feature depth.

Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

Abstract: In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of corresponding lot is for an etching process after a predetermined RF time of etching apparatus. RF time of the etching apparatus is compared with the predetermined RF time, and it is decided whether the etching process of corresponding lot can be performed in the etching apparatus if the etching process for the corresponding lot should be performed after a lapse of the predetermined RF time.

Abstract: A cleaning solution for use in removing a damaged portion of a ferroelectric layer, and a cleaning method using the solution. The cleaning solution includes a fluoride, an organic acid with carboxyl group, an alkaline pH adjusting agent and water.