Patents Issued in January 16, 2007
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Patent number: 7164549Abstract: A system and method for loading a head onto a specified load zone of a disk includes reading positional index information for determining a position of a pre-specified load zone of a disk. When to load a head is determined based on the positional index information so that the head will load onto the load zone, the load zone having an arc of less than 360 degrees. The head is loaded from a ramp onto the load zone at the proper time.Type: GrantFiled: March 6, 2006Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Karl Arthur Flechsig, Donald Ray Gillis, Shozo Saegusa, Reinhard F. Wolter
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Patent number: 7164550Abstract: Embodiments of the invention compensate for repeatable run-out errors without causing servo system instability. In one embodiment, HDD has a peak filter on a feedback route of a servo system. The peak filter is designed so that a rotating frequency of a magnetic disk, the high-frequency components contained in the rotating frequency and a peak match the rotating frequency and the high-frequency components. Insertion of a required peak filter into the servo system allows compensation for a repeatable run-out (RRO) error due to an event such as a deviation from the roundness of a track. Also, since a Nyquist diagram of the system satisfies required characteristics, a repeatable run-out error may be compensated for without causing instability of the servo system due to use of the peak filter.Type: GrantFiled: July 26, 2005Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: Masashi Kisaka
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Patent number: 7164551Abstract: A tape drive apparatus employing a tape cassette including a solid-state memory in a cassette half unit that accommodates a magnetic tape. When recording application data on the magnetic tape, the application data is written in an area of a preset size of the memory, beginning from a leading end of the application data. In this manner, it is assured that the management information located at the leading end of the application data can be stored in the memory. In reproducing the application data from the tape cassette, the management information stored in the memory is exploited to save time in accessing the management information recorded on the magnetic tape.Type: GrantFiled: February 27, 2003Date of Patent: January 16, 2007Assignee: Sony CorporationInventors: Masahiro Urano, Yoshihisa Takayama, Hiroshi Ishibashi, Tatsuya Kato
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Patent number: 7164552Abstract: A technique for setting the initial servo track pitch for a servo system of a hard disk drive (HDD) is based on using a secondary actuator, such as a microactuator or a milliactuator. The actuator of the HDD is positioned against a crash stop and a burst pattern is written on a hard disk while the read/write head is in a first position. A bias voltage of the secondary actuator is incrementally changed to change the position of the read/write head and a burst pattern is written for each change. The overlap is determined as a sum of the averaged amplitudes of the burst patterns that are adjacent to a selected burst pattern divided by the averaged amplitude of the selected burst pattern. The process is terminated when the determined overlap for each selected burst pattern is within a selected criterion of a target overlap value.Type: GrantFiled: September 29, 2003Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: Satoshi Yamamoto
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Patent number: 7164553Abstract: A magnetic recording and reproduction apparatus includes a main chassis having a rotatable head cylinder provided thereon; and a sub chassis on which a tape cassette is mountable. The sub chassis is movable relative to the main chassis. A pivotable body is provided on the main chassis. The pivotable body has a projection provided thereon. The projection is engaged with a cam groove in the sub chassis so as to pivot the pivotable body. Thus, the cam groove is restricted by the projection, so that the sub chassis moves with respect to the main chassis. The cam groove has a width substantially identical to the diameter of the projection. The cam groove includes first and second arc portions continuous with each other, and a straight portion continuous with the second arc portion. The first and second arc portions have identical radii, and are projected in opposite directions.Type: GrantFiled: March 24, 2004Date of Patent: January 16, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Saito, Koichiro Hirabayashi, Hiroshi Kurumatani
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Patent number: 7164554Abstract: A disk clamp for securing a data storage disk to the hub of a spindle motor in a disk drive prevents the migration of lubricant into sensitive areas of the disk drive. The problem of lubrication migration due to the use and presence of fastener lubricant is resolved by using a rib on a composite disk clamp. The rib strengthens the clamp structure and has a sealing ring. The ring has a semi-circular sectional profile with a flat surface that is used to bond the ring to the rib. The ring has elastic properties that compensate for hub vibration to isolate the disk clamp from the hub, and also provides damping between the hub and the disk clamp.Type: GrantFiled: June 30, 2004Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands BVInventors: Andre Sirilutporn, Jr-Yi Shen
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Patent number: 7164555Abstract: In one embodiment, a magnetic write/read device comprising a magnetic read element and a magnetic write element is formed in a thin film magnetic head portion of a magnetic head slider. A heat generating resistor is formed between a substrate portion and the magnetic reproducing device for heating thereby thermally expanding and protruding a portion of the magnetic head slider to control the flying height. The heat generating resistor is positioned between the substrate portion and the magnetic reproducing device being apart from the magnetic reproducing device for making the response speed for the flying height control of the magnetic head slider as high as possible and decreasing the effect caused by the heat generation of the heat generating resistor on the magnetic reproducing device as little as possible.Type: GrantFiled: August 10, 2005Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Atsushi Kato, Toshiya Shiramatsu, Masahiko Soga
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Patent number: 7164556Abstract: A magnetic head slider includes a magnetic head mounting surface, a slider rail surface, a step air bearing surface, and a negative pressure groove. The magnetic head mounting surface is arranged in a center area with respect to a width of the slider near an air flow-out edge on the slider and mounts a magnetic head. The slider rail surface has a first depth from the magnetic head mounting surface and its width on an air flow-in side for the magnetic head is wider that its width on an air flow-out side for the magnetic head. The step air bearing surface is formed on an air flow-in side of the slider rail surface and has a second depth from the slider rail surface. The negative-pressure groove which formed on an air flow-in side of the step air bearing surface and has a third depth from the step air bearing surface.Type: GrantFiled: August 11, 2005Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Japan, Ltd.Inventors: Hidekazu Kohira, Masaaki Matsumoto, Hideaki Tanaka, Teruyoshi Higashiya, Kiyoshi Hashimoto, Akira Matsuda, Takanori Yamazaki
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Apparatus for burnishing small asperities and cleaning loose particles from magnetic recording media
Patent number: 7164557Abstract: An air bearing burnish slider burnishes very small asperities and cleans the loose particles that adhere to the magnetic recording media. The slider applies a controllable contact force to effectively burnish disk asperities or partially attached particles. In addition, the slider cleans the loose particles effectively while flying in a stable fashion. In a low pitch design, diagonal rails push particles away from the disk surface and trailing edge pads contact the disk at lower linear velocities. Rail pads retain loose contamination and debris in their pockets and burnish asperities. Another design provides a milder burnish force and flies in a high pitch configuration. The trailing edge pads provide stable contacts and the rails help in sweeping away debris. In both designs, the contact forces can be controlled by adjusting linear velocities. A step taper at the leading edge provides a pitch-producing lift force.Type: GrantFiled: February 23, 2004Date of Patent: January 16, 2007Assignee: Hitachi Global Storage Technologies Netherlands BVInventors: Parul Agrawal, Hang Fai Ngo, Charles Lee, Li-Chung Lee, Ullal Vasant Nayak, Stephen Olson, Robert N. Payne, Christopher Ramm -
Patent number: 7164558Abstract: An actuator supporting apparatus of a hard disk drive includes a pivot bearing including an inner ring, an outer ring, and a rolling member, which are installed coaxially, to support an actuator arm to pivot. The actuator supporting apparatus also includes a support structure to support upper and lower surfaces of the inner ring, and a buffer member interposed between at least one of the upper and lower surfaces of the inner ring and the support structure, to buffer vibrations and impacts. Thus, a feature of buffering vibrations and impacts by the buffer member is not changed and is constantly maintained, regardless of accumulation of manufacture allowance or a change in the environment. Also, a problem in reliability of a product due to deterioration of structural strength, which occurs in the conventional actuator supporting apparatus, does not occur in the actuator supporting apparatus of the present invention.Type: GrantFiled: June 1, 2005Date of Patent: January 16, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-tag Jeong
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Patent number: 7164559Abstract: A head actuator is made thinner without sacrificing its strength to thereby achieve the thinning of a hard disk apparatus. On the base end of each of two suspensions is provided a boss that protrudes in the direction of the side on which a magnetic head is provided, and a suspension fixing section having a hole into which the bosses are inserted is formed towards the tip of an arm. The boss of one of the suspensions is inserted into the hole from the upper end section thereof, and the boss of the other suspension is inserted into the hole from the lower end section thereof. Thus, the arm is fixed in place by being held by the two suspensions from above and below.Type: GrantFiled: October 15, 2003Date of Patent: January 16, 2007Assignee: Sony CorporationInventors: Kazuyuki Yamamoto, Takashi Yamada, Masami Miike, Kazutoshi Yamamoto, Toshio Mamiya
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Patent number: 7164560Abstract: A spin-valve magnetoresistive thin film element comprises an antiferromagnetic layer and a pinned magnetic film. The pinned magnetic film contacts the antiferromagnetic layer, wherein a magnetizing direction is pinned by an exchange coupling magnetic field between the pinned magnetic layer and the antiferromagnetic layer. The spin-valve magnetoresistive thin film element further comprises a free magnetic layer and a nonmagnetic electrically conductive layer. The nonmagnetic electrically conductive layer is formed between the free magnetic layer and the pinned magnetic layer, wherein a magnetizing direction of said free magnetic layer is aligned so as to intersect with said magnetizing direction of said pinned magnetic film.Type: GrantFiled: July 22, 2003Date of Patent: January 16, 2007Assignee: Alps Electric Co., Ltd.Inventors: Masamichi Saito, Naoya Hasegawa
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Patent number: 7164561Abstract: A step down voltage regulator including devices designed to operate over a maximum rated voltage lower than the supply voltage. The regulator comprises an output regulation device coupled to the supply voltage and an output; and an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output device is not exceeded. Also provided is a method for operating a voltage regulator in a memory system. The method includes the steps of: providing a voltage regulator having an input and an output, and including a plurality of devices operating at a maximum rated voltage less than the voltage provided at the input; and controlling the gate voltage of the output device responsive to a load on the regulator output, so that the maximum rated voltage is not exceeded.Type: GrantFiled: March 31, 2004Date of Patent: January 16, 2007Assignee: Sandisk CorporationInventors: Yongliang Wang, John Pasternak
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Patent number: 7164562Abstract: A protection configuration for converter means which comprise a plurality of controllable switches, the protection configuration comprising a protection circuit coupled to the alternating voltage side of the converter means, which protection circuit comprises at least one protective switch configured to short-circuit the alternating voltage side of the converter means, wherein the protection configuration, in predetermined failure situations, is configured to close the protective switch and thus to short-circuit the alternating voltage side of the converter means. After the failure situation has cleared up, the protection configuration is configured to short-circuit the alternating voltage side of the converter means by means of the controllable switches to enhance commutation of the protective switch.Type: GrantFiled: March 31, 2004Date of Patent: January 16, 2007Assignee: ABB OYInventor: Reijo Virtanen
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Patent number: 7164563Abstract: A resettable circuit interrupting device such as a GFCI that, when reverse wired during installation, will trip and prevent power being applied to the load side of the GFCI when powered up. A current limiting circuit is connected between the phase and a ground terminal on the line side of the differential transformer of the GFCI. When the GFCI is connected correctly, the current through the current limiting circuit will have no significant effect on the GFCI, and it will operate normally. When, however, the line conductors are connected to the load terminals of the GFCI and the load conductors are connected to the line terminals of the GFCI, the current through the current limiting circuit will appear as a ground fault and cause the GFCI to trip.Type: GrantFiled: January 22, 2004Date of Patent: January 16, 2007Assignee: Leviton Manufacturing Co., Inc.Inventors: David Y. Chan, Bernard J. Gershen
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Patent number: 7164564Abstract: The present invention is directed to a protective device that includes a plurality of line terminals and a plurality of load terminals. A fault detection circuit is coupled to the plurality of line terminals. The fault detection circuit is configured to provide a detection output signal in response to a detected condition. A switching device is coupled to the fault detection circuit. The switching device is configured to provide a trip signal in response to the detection output signal, the switching device being characterized by at least one device parameter. A circuit interrupting assembly is configured to electrically connect the plurality of line terminals and the plurality of load terminals in a reset state and disconnect the plurality of line terminals from the plurality of load terminals in response to the trip signal in a tripped state. An indicator circuit assembly is coupled to the switching device.Type: GrantFiled: May 13, 2005Date of Patent: January 16, 2007Assignee: Pass & Seymour, Inc.Inventors: David A. Finlay, Sr., Kent Morgan, Jeffrey C. Richards
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Patent number: 7164565Abstract: An ESD protection circuit for an integrated circuit includes an ESD clamping circuit, an ESD triggering circuit, and an ESD disabling circuit. The ESD clamping circuit is operably coupled to a first power pin of the integrated circuit and a second power pin of the integrated circuit. The ESD triggering circuit is operably coupled to the ESD clamping circuit, wherein, when enabled and when sensing an ESD event, the ESD triggering circuit provides a clamping signal to the ESD clamping circuit such that the ESD clamping circuit provides a low impedance path between the first and second power pins. The ESD disabling circuit is operably coupled to disable the ESD triggering circuit when the integrated circuit is in a normal operating mode.Type: GrantFiled: November 26, 2003Date of Patent: January 16, 2007Assignee: Sigmatel, Inc.Inventor: Fujio Takeda
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Patent number: 7164566Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.Type: GrantFiled: March 19, 2004Date of Patent: January 16, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Beth A. Baumert, Richard T. Ida
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Patent number: 7164567Abstract: A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).Type: GrantFiled: June 22, 2004Date of Patent: January 16, 2007Assignee: Infineon Technologies AGInventors: Andrej Litwin, Ola Pettersson
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Patent number: 7164568Abstract: A bi-directional low capacitance TVS using a PIN or NIP diode is disclosed. Bi-directional low capacitance TVS protection circuit (1000) consists of two pairs of TVS diodes (1001), (1003) and LC PIN or NIP diodes (1002), (1004). Diodes (1003) and (1004) are in parallel and in opposite direction from a first series of TVS and LC diode pair. This circuit provides transient protection in both directions for a bi-directional low capacitance TVS.Type: GrantFiled: March 3, 2005Date of Patent: January 16, 2007Assignee: Microsemi CorporationInventor: Cecil Kent Walters
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Patent number: 7164569Abstract: A bulk degaussing system for the erasure of magnetic storage media by means of permanent magnets. The bulk degaussing system includes a rotatably mounted carousel and an angular displacement means that angularly displaces the carousel through a predetermined angle after passage of the carousel through a degaussing gap.Type: GrantFiled: June 30, 2004Date of Patent: January 16, 2007Assignee: Data Security, Inc.Inventors: LeRoy D. Thiel, Robert A. Schultz
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Patent number: 7164570Abstract: An excitation control circuit for suitably exciting a solenoid while current consumption and heating are effectively reduced. The control circuit has a driving circuit for driving a coil of a solenoid in response to a pulse signal supplied from an external device; a counter-electromotive force absorbing circuit, inserted in a path of a return current of the coil, for absorbing counter-electromotive force produced by the coil; and a return current circuit, connected in parallel to the counter-electromotive force absorbing circuit, for intermittently bypassing the return current. The return current circuit may have a field effect transistor switched on according to a signal for defining the timing of bypassing the return current, where the current path of the transistor is connected between a positive electrode and a negative electrode of the coil.Type: GrantFiled: August 20, 2003Date of Patent: January 16, 2007Assignee: Keihin CorporationInventor: Yasuharu Hourai
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Patent number: 7164571Abstract: A wafer stage for holding a wafer in a chamber of a plasma processing system, the wafer stage includes an electrode on which a wafer is placed, to which electrical current is supplied, a diameter of the electrode is larger than a diameter of said wafer, a plurality of magnets separately arranged on an outermost region of said electrode and said magnets are arranged such that alternate magnetic poles face towards the inside of the chamber, and an outer-ring placed around said wafer, the outer ring having a magnetic metal ring at a lower side.Type: GrantFiled: February 19, 2005Date of Patent: January 16, 2007Assignee: Anelva CorporationInventors: Sunil Wickramanayaka, Yoshikazu Nozaki
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Patent number: 7164572Abstract: An electrical feedthrough assembly according to the invention can be used as a component of an implantable medical device (IMD) and/or or electrochemical cell. An IMD includes implantable pulse generators, cardioverter-defibrillators, physiologic sensors, drug-delivery systems, etc. Such assemblies require biocompatibility and resistance to degradation under applied bias current or voltage. In some forms of the invention, such assemblies are fabricated by using electrically common, multiply-interconnected electrical pathways including metallized vias and interlayer structures of conductive metallic material within bores and between ceramic layers. The layers are stacked together and sintered to form a substantially monolithic dielectric structure with at least one electrically common embedded metallization pathway extending through the structure.Type: GrantFiled: September 15, 2005Date of Patent: January 16, 2007Assignee: Medtronic, Inc.Inventors: Jeremy W. Burdon, Joyce K. Yamamoto
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Patent number: 7164573Abstract: A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.Type: GrantFiled: August 31, 2005Date of Patent: January 16, 2007Assignee: Kemet Electronic CorporationInventor: John D. Prymak
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Patent number: 7164574Abstract: A capacitor including a capacitor stack. The capacitor includes one or more substantially planar anode layers, and one or more substantially planar cathode layers. The capacitor includes a case with a first opening and a second opening, the first opening sized for passage of the capacitor stack and the second opening defined by walls having a first thickness. Additionally, the capacitor has a cover substantially conforming to the first opening and sealingly connected to the first opening, and a plate substantially conforming to the second opening, the plate adapted for attachment of a terminal, and sealingly connected to the second opening. The plate has a second thickness which is approximately greater than the first thickness of the walls defining the second opening. The capacitor stack is disposed in the case, and the terminal is in electrical connection with the case and at least one capacitor electrode.Type: GrantFiled: July 15, 2005Date of Patent: January 16, 2007Assignee: Cardiac Pacemakers, Inc.Inventors: A. Gordon Barr, James A. Taller, Brian L. Schmidt
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Patent number: 7164575Abstract: For a data card unit (1), in which the data cards (68) are transported by motor into the reading/writing position, a two-armed rocker (13), on one arm of which a closing element (57) is arranged, is provided for closing the insertion opening. The other arm of the rocker (13) has a sensing element (66, 67). The distance between the closing element (57) and the sensing element (66, 67) is chosen to be equal to or greater than the length of the data card (68) and the assignment of the closing element (57) and the sensing element (66, 67) to the plane of movement of the data card (68) is set up such that, during the insertion/ejection of a data card (68), the rocker (13) is pivoted by the data card (68) and either the closing element (57) or the sensing element (66, 67) enters the plane of movement of the data card (68).Type: GrantFiled: November 27, 2001Date of Patent: January 16, 2007Assignee: Siemens AktiengesellschaftInventor: Klaus Hug
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Patent number: 7164576Abstract: A portable speaker system for use with a laptop computer is configured for attachment to a screen of a laptop computer or alternatively for a free standing configuration. The speaker system includes an acoustic chamber for containment of the sound reproducing mechanism, a second chamber, and a damped hinge mechanism for movable connecting the acoustic chamber and the second chamber.Type: GrantFiled: May 6, 2004Date of Patent: January 16, 2007Assignee: Creative Technology LtdInventors: Susimin Suprapmo, Aik Hee Goh, Chiew Foon Celia Wong, Hua Chung Ho
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Patent number: 7164577Abstract: An electronic apparatus includes a housing, a case, a storage device, and a cable. The housing has a bottom wall and convex portions projecting upward from the bottom wall. The case has a top wall and is accommodated inside the housing while being supported by the convex portions. The storage device is supported by the case. The cable has a connector connected to the storage device. Gaps are formed between the bottom wall of the housing and the storage device and between the top wall of the case and the storage device, respectively. The cable passes through the gap.Type: GrantFiled: November 23, 2004Date of Patent: January 16, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Minaguchi, Hidemi Itakura, Takayuki Arisaka
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Patent number: 7164578Abstract: A common lock used in a dual-usage portable computer formed of a base member and a display is disclosed to include a left-side hook and a right-side hook respectively pivoted to the base member on the inside, and an elongated operating frame bar axially slidably mounted inside the base member of the portable computer and coupled between the left-side hook and the right-side hook for operation by the user to bias the left-side hook and the right-side hook by means of a lever action and to further force the left-side hook and the right-side hook out of a respective through hole at the base member into engagement with a respective retaining block at the display to lock the display to the base member.Type: GrantFiled: June 6, 2005Date of Patent: January 16, 2007Assignee: Tatung Co., Ltd.Inventors: Wen-Chieh Wang, Chin-Ming Chang, Chin-Ku Chuang
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Patent number: 7164579Abstract: A disk drive unit mounting device is adapted to carry one or plural disk drive units. The mounting device includes a temperature control module and a carrier module secured together y a releasable fastener device so that the temperature control module controls the temperature of the disk drive unit. The temperature control module has an air flow control device for controlling the flow of air across the disk drive unit appropriately according to the required temperature for the disk drive unit. The mounting device may be used in testing disk drive units.Type: GrantFiled: July 1, 2003Date of Patent: January 16, 2007Assignee: Xyratex Technology LimitedInventors: Timothy John Muncaster, William Albert Saville
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Patent number: 7164580Abstract: A system for using a plenum to cool components of the system is described. The plenum distributes air to local hot spots of the system which are remote from a fan source. A central processing fan, a separate system fan, or an external air source may be used to generate the air to be distributed.Type: GrantFiled: March 25, 2003Date of Patent: January 16, 2007Assignee: Intel CorporationInventor: Eric DiStefano
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Patent number: 7164581Abstract: A chassis divides vertically, with front and rear sections of the chassis joined immediately adjacent a midplane printed circuit board that supports interconnectivity of electronic circuits. Wiring within the chassis is eliminated through directed connections of all components to the midplane. Minimal hardware is required for securing the front and rear sections together, and therefore accessing the midplane for assembly and service is convenient. All components except the midplane are installed and removed from either the front or rear of the chassis without opening or disassembling the chassis. The chassis layout and features facilitate effective cooling of the components in the chassis.Type: GrantFiled: June 21, 2004Date of Patent: January 16, 2007Assignee: Computer Network Technology Corp.Inventors: Thomas J. Carullo, Arthur G. Willers, Ryan K. Goodenough
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Patent number: 7164582Abstract: A cooling system for dissipating heat from a component is disclosed. The cooling system includes a cooling device that includes a core and a plurality of spaced apart fins connected with the core with each fin including at least two vanes. A trailing edge of the fins define a chamber. A fan mount is connected with the vanes and supports a stator of a fan. A rotor connected with the stator includes a plurality of fan blades and the fan mount positions the stator over the chamber with the fan blades submerged in the chamber. A height of the cooling system is reduced because the fan does not include a housing and a substantial portion of the fan is positioned in the chamber. The submerged position of the fan blades allows for a high fan capacity with reduce air shock noise.Type: GrantFiled: October 29, 2004Date of Patent: January 16, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Shankar Hegde
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Patent number: 7164583Abstract: A mounting device (10) for mounting a heat sink (20) to a circuit board (40), includes a locking member (16) extending through the heat sink and including a through hole (162) and barbs (172) formed in one end portion thereof for engaging with the circuit board, an operation member (12) including a cylinder (122) and a rod (128) extending from the cylinder into the through hole of the locking member. First and second bumps (178, 179) are formed in the locking member, and a pair of slots (126) is defined in the cylinder for engaging with the first and second bumps at first and second positions respectively. A spring (14) is received in the cylinder, surrounding the rod and compressed between an end of the cylinder and the first bumps. The rod expands the barbs outwardly at the second position and releases the barbs at the first position.Type: GrantFiled: September 21, 2004Date of Patent: January 16, 2007Assignees: Fu Zhun Precision Ind. (Shenzhen) Co., Ltd., Foxconn Technology Co., Ltd.Inventors: Hsieh Kun Lee, Wan-Lin Xia, He-Ben Liu
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Patent number: 7164584Abstract: An electromagnetic device (10) includes a core (12) having first and second arms (16, 18) connected by at least one body (14), a first winding (40) having multiple turns (41a, 41b) on the first arm (16) and a second winding (42) having multiple turns (43a, 43b) on the second arm (18), and a heatsink (50) having a first plurality of U-shaped heatsink elements (52) each including first and second legs (56, 58) aligned with the first and second arms (16, 18) and having a first thickness connected by a base (54) having a second thickness greater than the first thickness, the base (54) of each of the plurality of elements (52) being in contact with the base (54) of an adjacent heatsink element (52).Type: GrantFiled: October 19, 2004Date of Patent: January 16, 2007Assignee: Honeywell International Inc.Inventor: Andrew A. Walz
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Patent number: 7164585Abstract: An apparatus and system, as well as fabrication methods therefor, may include a die having a surface and a primary material comprising tin, pure tin, or substantially pure tin coupled to the surface. A heat dissipating element may be coupled to the primary material.Type: GrantFiled: March 31, 2003Date of Patent: January 16, 2007Assignee: Intel CorporationInventors: Susheel G. Jadhav, Carl Deppisch, Fay Hua
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Patent number: 7164586Abstract: A plasma display. The plasma display comprises a first circuit board and a second circuit board disposed in a space formed by a base plate and a back cover thereof. The first circuit board is mounted on the base plate and bears a first electronic element, the second circuit board is mounted on the first circuit board and bears a second electronic element requiring heat dissipation different from the first electronic element. A thermal conductive device is disposed between the second electronic element and the back cover to dissipate heat from the second electronic element to the back cover. Thereby, the electronic elements requiring different heat dissipation are positioned in divided areas to enhance heat dissipation efficiency.Type: GrantFiled: March 3, 2004Date of Patent: January 16, 2007Assignee: AU Optronics Corp.Inventor: Yu-Kai Lin
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Patent number: 7164587Abstract: An electromagnetic (EM) shielding assembly shields an electronic component mounted on a circuit board. The assembly includes a shielding portion that is electrically conductive and can be mounted adjacent an electronic component that it is desired shield. The shielding portion at least partially surrounds the component, thereby providing a degree of EM shielding. The assembly also includes at least one resiliently biased electrically conductive connection member in electrical communication with the shielding portion. The connection member is operable electrically to connect the shielding portion to a predetermined voltage by bearing down upon an electrically conductive contact of the circuit board.Type: GrantFiled: January 14, 2004Date of Patent: January 16, 2007Assignee: Sun Microsystems, Inc.Inventors: Paul J. Garnett, Sean Conor Wrycraft
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Patent number: 7164588Abstract: A printed circuit board (PCB) holder having a pair of spaced apart frames with captivating mechanisms for supporting one or more PCBs independent of the number and geometry of the PCBs. Each frame is defined by a ridge member surrounding the periphery of the frame and the ridge member has at least one captivating mechanism to engage a portion of at least one PCB. One frame holds one end of a PCB and the other frame holds the opposite end of the PCB.Type: GrantFiled: September 27, 2005Date of Patent: January 16, 2007Assignee: Leviton Manufacturing Co., Inc.Inventors: Danilo F. Estanislao, Paul Soccoli
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Patent number: 7164589Abstract: A circuit is provided for converting power from an AC power source to DC power. The circuit including bi-directional switches capable of conducting and blocking a current flow in both directions. One or more control switches are coupled to a bi-directional switch to enable and disable the current flow through the bi-directional switch, the control switches are controlled by a signal voltage to turn a bi-directional switch ON by discharging a threshold voltage on one of the bi-directional switch gates and turning a bi-directional switch OFF when the threshold voltage is not discharged by the control switches. Additionally, the circuit includes a transformer having one or more primary windings and a secondary winding, each primary winding being coupled to one of the bi-directional switch sources. The current flow through the primary winding is disabled when the current flow through the corresponding bi-directional switch source is disabled.Type: GrantFiled: June 26, 2006Date of Patent: January 16, 2007Assignee: International Rectifier CorporationInventors: Marco Soldano, Maurizio Salato
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Patent number: 7164590Abstract: A power inverter control adjusts input power to track with output power to reduce energy handling requirements for an inverter DC bus. Input power to the power inverter circuit is measured and compared with a measurement of inverter output power. The comparison result is applied to a power factor correction circuit to adjust input power to track with output power, while obtaining a good power factor for the power inverter circuit. The energy requirements and ripple voltages or ripple currents on the DC bus are reduced, leading to a reduction in rating specifications for passive energy storage elements on the DC bus.Type: GrantFiled: July 28, 2003Date of Patent: January 16, 2007Assignee: International Rectifier CorporationInventors: Yong Li, Toshio Takahashi
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Patent number: 7164591Abstract: The bridgeless boost topology reduces the power dissipation, cost, and size of prior PFC systems by eliminating the intrinsic loss of the input rectifier bridge. Sensing of the input line voltage by the controller is unnecessary. The use of One Cycle Control (also known as Single Cycle Control) allows the Power Factor Correction function to be performed without complex rectification networks to obtain the AC line voltage reference. The use of bi-directional switches makes it possible to control inrush current (the startup over-current due to the charging of the output bulk capacitor), which allows elimination of over-current limiting devices and reduction of the diode surge capability requirements. Moving the boost inductor to the system input adds an additional filtering function, reducing the cost of input EMI filtering.Type: GrantFiled: September 29, 2004Date of Patent: January 16, 2007Assignee: International Rectifier CorporationInventor: Marco Soldano
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Patent number: 7164592Abstract: A wiring board includes a plurality of wiring layers, and one surface formed with a plurality of chip connecting electrodes and another surface formed with a plurality of external connecting electrodes of a semiconductor device. The wiring board has wiring layers and vias. The plurality of chip connecting electrodes include first chip connecting electrodes, each used for a first signal whose logic value changes, and second chip connecting electrodes, each used for a second signal that changes after a change timing of the first signal. A wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is performed, are made different from each other.Type: GrantFiled: May 24, 2005Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroaki Nambu
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Patent number: 7164593Abstract: A storage section, at least one writing section, and at least one reading section are provided on a substrate. A storage-section substrate region in which the storage section is formed, at least one writing-section substrate region in which each writing section is formed, at least one reading-section substrate region in which each reading section is formed are insulatedly isolated from each other on the substrate. Independent substrate potentials are applied to each substrate region.Type: GrantFiled: May 21, 2004Date of Patent: January 16, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yuuichirou Ikeda
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Patent number: 7164594Abstract: A nonvolatile ferroelectric memory device features a multi-bit serial cell structure where read bit lines and write bit lines are divided to control read/write paths individually, thereby improving a transmission operation of serial data. In the nonvolatile ferroelectric memory device, a serial cell that comprises a plurality of switching devices and a plurality of ferroelectric capacitors is connected serially between a write switching device and a read switching device. The serial cell stores cell data applied from the write bit line sequentially in the plurality of ferroelectric capacitors at a write mode, and outputs the cell data stored in a plurality of ferroelectric capacitors to the read bit line at a read mode.Type: GrantFiled: March 29, 2005Date of Patent: January 16, 2007Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Jin Hong Ahn
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Patent number: 7164595Abstract: A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are each configured in series for individual respective coupling between a first digit line and a second digit line. The first and second pass transistors are further configured for respective control by first and second wordlines. The first pass transistor and first capacitor are symmetrically configured with the second pass transistor and the second capacitor. The memory cell further includes an interconnection formed on a cell plate conductor between a terminal end of the first capacitor and a terminal end of the second capacitor. Furthermore, the interconnection is electrically isolated from other portions of the cell plate conductor.Type: GrantFiled: August 25, 2005Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventors: Michael A. Shore, Brian P. Callaway
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Patent number: 7164596Abstract: An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.Type: GrantFiled: July 28, 2005Date of Patent: January 16, 2007Assignee: Texas Instruments IncorporatedInventors: Xiaowei Deng, Theodore W. Houston
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Patent number: 7164597Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.Type: GrantFiled: August 5, 2005Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7164598Abstract: Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.Type: GrantFiled: August 11, 2005Date of Patent: January 16, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Cheol Jeong, Ki-Nam Kim, Hong-Sik Jeong, Gi-Tae Jeong, Jae-Hyun Park