Abstract: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a ball grid array package. Also, a method for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A method of fabricating a semiconductor device comprising: a step (a) of attaching a plurality of semiconductor chips to a tape; a step (b) of cutting the tape; and a step (c) of providing a plurality of external terminals on an insulating film cut from the tape, wherein the steps (a) and (b) are carried out in a reel-to-reel transport system.

Abstract: A transcutaneous electrode is disclosed having a sheet electrode of an electrically-conductive material with an electrically conductive layer affixed to a major portion of the lower surface thereof. A pad of electrically-conductive gel is applied to the lower surface of the sheet electrode over the electrically-conductive layer. An electrical conductor having an unsheathed end portion is secured to the upper surface of the sheet electrode by an electrically-conductive adhesive. A high dielectric cover overlays the end out portion of the electrical conductor, and is secured to the sheet electrode by the conductive adhesive. A method for making the electrode is also disclosed.

Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.

Abstract: Interconnect assemblies and methods for forming and using them. In one example of the invention, an interconnect assembly comprises a substrate, a resilient contact element and a stop structure. The resilient contact element is disposed on the substrate and has at least a portion thereof which is capable of moving to a first position, which is defined by the stop structure, in which the resilient contact element is in mechanical and electrical contact with another contact element. In another example of the invention, a stop structure is disposed on a first substrate with a first contact element, and this stop structure defines a first position of a resilient contact element, disposed on a second substrate, in which the resilient contact element is in mechanical and electrical contact with the first contact element. The stop structure may be formed as a sheet with openings and applied to an unsingulated semiconductor wafer with resilient contacts located in the openings.

Abstract: A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Abstract: A process for producing a resin-sealed semiconductor device having high reliability which is produced more easily and efficiently without voids, the process comprising the steps of: (a) providing a semiconductor wafer having circuits on a surface; (b) applying a resin sheet composed of a support and an adhesive resin layer releasable from the support, on the circuit surface of the semiconductor wafer, and fixing an outer periphery of the resin sheet with a ring frame; (c) cutting the semiconductor wafer and the resin layer by each circuit to form chips; (d) picking up each chip together with the resin layer from the support; (e) mounting each chip on a predetermined position of a chip mounting substrate through the resin layer; and (f) firmly bonding the chip on the chip mounting substrate so as to achieve conduction between the chip and the chip mounting substrate.

Abstract: Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural component is formed using standard lithographic processes and electrodeposition of a structural layer. A second sacrificial wafer is separately processed using similar lithographic and electrodeposition processes to form a corresponding second three dimensional structural component. The wafers are placed in a flip-chip bonder and aligned. Once aligned, the structural components are bonded together. The bonded wafers are then removed from the bonder and the second sacrificial wafer substrate removed. The resultant die includes a three dimensional structural component with a substantially enclosed cavity as well as MEMS and IC elements.

Abstract: To accommodate high power densities associated with high performance integrated circuits, an integrated circuit package includes a heat-dissipating structure in which heat is dissipated from a surface of a die to an integrated heat spreader (IHS) through a high capacity thermal interface formed of metal that has been injected in a semi-solid state. In one embodiment, vacuum and a shear-controlled viscosity enable semi-solid metallic material to fill a narrow chamber between the die surface and a specially shaped mold plate that doubles as an IHS, without inducing voids in the solidified metal. In another embodiment, an injection machine is disclosed. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

Abstract: The invention enhances a production yield of a display device (an electro-optical device). The invention provides a method of manufacturing an electro-optical device including a display region in which a plurality of basic pixels are arranged, each basic pixel including a plurality of color pixels. The method includes: forming on a first substrate lines to drive a plurality of electro-optical elements respectively constituting the color pixels, correspondingly to the arrangement of the basic pixels; forming on a second substrate, as a chip to be transferred to each basic pixel, a drive circuit to drive the plurality of electro-optical elements which constitutes the plurality of color pixels of the basic pixels to obtain a plurality of basic-pixel driving chips; and transferring step of transferring the respective basic-pixel driving chips from the second substrate onto the first substrate, and connecting the drive circuits to regions of the lines corresponding to the basic pixels.

Abstract: A method of fabricating a liquid crystal display panel is provided, which comprises the steps of providing a substrate; forming a mask layer over the substrate, wherein the mask layer has a reverse-tapered opening exposing a predetermined conductive line area; depositing a metal layer on the substrate within the predetermined conductive line area to form a conductive line with a tapered sidewall by performing an anisotropic deposition process; and removing the mask.

Abstract: A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to a CMOS electronic device portion. The openings are formed using a dual trench process, forming openings or shallow trenches in the non-MOS transistor device portion to a first depth, and openings in the CMOS electronic device portion to a second depth greater than the first depth.

Abstract: FETs and methods for fabricating FETs are disclosed. An illustrated method comprises forming a first insulating layer on a semiconductor substrate; forming a first conductive layer for a fin on the first insulating layer; etching the first conductive layer so that an area of a lower part of the first conductive layer is wider than an area of an upper part of the first conductive layer; forming voltage adjust regions through an ion implantation method; forming a gate insulating layer through a forming gas annealing method; forming a second conductive layer; forming LDD regions by implanting ions into the first conductive layer; forming sidewall spacers adjacent the gate insulating layer; and forming source/drain regions adjacent to the sidewall spacers by implanting ions into the first conductive layer.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: A process for laser processing an article which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof, said article being made from a material selected from a semiconductor, a metal, an insulator, and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity, thereby allowing the impurity to physically or chemically diffuse into, combine with, or intrude into said article.

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

Abstract: A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second dielectric layer over the polysilicon layer, forming a third dielectric layer over the second dielectric layer, etching a dielectric window through the third dielectric layer, forming a fourth dielectric layer into the dielectric window and over the third dielectric layer, the fourth dielectric layer being of a material dissimilar to the second dielectric layer, etching the fourth dielectric layer anisotropically using an etchant with a high selectivity ratio between the fourth dielectric layer and the second dielectric layer thereby forming a spacer, and etching portions of the first and second dielectric layers and the polysilicon layer anisotropically, the portions underlying an area bounded by a periphery of the spacer thereby forming the opening.

Abstract: A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional masking. An n-well is firstly formed in a p-type silicon substrate. A nitride film is then deposited and patterned to form a patterned mask layer. The patterned mask layer serves as a mask. A p-field region is formed in the n-well to form a CMOS resistor. The CMOS resistor according to the present invention has a resistance of 10 k?–20 k? per square.

Abstract: Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: (a) forming a first inter-level insulating film on a semiconductor substrate formed with semiconductor elements; (b) forming a contact hole through the first inter-level insulating film; (c) forming a plug made of conductive material capable of being nitrided, the plug being embedded in the contact hole; and (d) heating the semiconductor substrate in a nitriding atmosphere to nitride the plug from a surface thereof. This semiconductor device manufacture method can prevent breakdown of a plug when a capacitor is formed on the plug.

Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.

Abstract: In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving as the capacitor dielectric is deposited after which a triple layer of passivation is created over a substrate. The compound passivation layer is first etched, using a fuse mask, to define and expose the capacitor dielectric and a fuse area after which the passivation layer is second etched to define and expose the contact pad. A layer of AlCu is then deposited, patterned and etched to create a capacitor upper plate and a contact interconnect over the contact pad. Under a second embodiment of the invention, a triple layer of passivation is created over a layer of etch stop material deposited over a substrate, a contact pad and a lower capacitor plate have been provided over the substrate.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160).

Abstract: A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. Afterward, a composite dielectric layer is formed on the substrate and covers the conductive lines. Finally, a plurality of word lines are formed on the composite dielectric layer.

Abstract: A thin layer of single-crystal silicon is produced by forming first trenches in a silicon substrate having (111) orientation; forming narrower second trenches at the bases of the trenches; anisotropically etching lateral channels (4) from the second trenches, until adjacent etch fronts (16) substantially meet; and detaching said layer from the substrate. The trenches may be arranged so that the resultant layer has rows of slots, whit the slots in adjacent rows being mutually offset. Solar cells may be formed on strips (5) between the trenches, having lengths of more than 50 mm, widths of up to 5 mm, and thicknesses of less than 100 microns, and having two electrical contacts on the same face (6) of each strip (5).

Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and t

Abstract: A nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. Each resistance-change portion is of a second conductivity type having impurity concentration lower than that of the first and second main electrode regions. The charge-accumulation portions are provided on the associated resistance-change portions. Each charge accumulation portion has an insulating layer, and is capable of accumulating charge.

Abstract: A method for fabricating a nonvolatile memory device comprises the steps of: defining an active region in a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer on the active region; patterning the capping layer to form a pair of caps; forming a first conducting pattern having a width defined by the pair of caps; depositing a second conducting layer on the substrate to cover the first conducting pattern; forming a first photoresist pattern on the second conducting layer, the first photoresist pattern having an opening over a portion of the active region between the pair of caps; selectively etching the second conducting layer using the first photoresist pattern as an etch mask, and at the same time selectively etching the first conducting pattern with the pair of caps as an etch mask, to form a pair of first gates.

Abstract: A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor followed by the formation of ZrO2 on the HfO2 layer.

Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Abstract: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.

Abstract: Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped region within the substrate. A first spacer is formed on a first side and a second spacer on a second side of the gate electrode. An ion is implanted into the first spacer with an angle greater than zero from an axis perpendicular to the surface of the substrate. The first spacer is etched to remove a portion thereof and a silicon film is deposited overlying a remainder of the first spacer, the impurity doped region and the second spacer. The silicon film is etched, forming a silicon spacer, and a silicide-forming metal is deposited to form a silicide contact that electrically couples the gate electrode and the impurity doped region.

Abstract: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

Abstract: Semiconductor devices and methods for fabricating a silicide of a semiconductor device are disclosed. An illustrated method comprises: forming a gate electrode; depositing an insulating layer; removing a predetermined portion of the insulating layer in order to expose a portion of the gate electrode; forming silicide on the exposed portion of the gate electrode; and etching the insulating layer while using the silicide as an etching mask.

Abstract: A varactor has a plurality of alternating P? wells and N+ regions formed in a silicon layer. Each of the P? wells forms a first N+/P? junction with the N+ region on one of its side and a second N+/P? junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P? wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Abstract: A method for fabricating a capacitor is disclosed. First, a dielectric layer is disposed on a semiconductor substrate. Next, at least one dual damascene opening and at least one capacitor opening are formed in the dielectric layer. Next, a first conductive layer is disposed on the surface of the dielectric layer, the bottom and sidewall of the capacitor opening, and the dual damascene opening. Next, an insulating layer is formed on the first conductive layer and a second conductive layer is disposed on the insulating layer. Following that, a planarization process is performed to remove the second conductive layer, the insulating layer, and the first conductive layer on the dielectric surface for forming a capacitor and a dual damascene conductor.

Abstract: A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, but leaving this layer on a first region; and forming a second dielectric layer having a dielectric constant higher than that of the first dielectric layer, on the first and second regions.

Abstract: A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multilayered film containing the silicon nitride oxide film on the silicon nitride film; a second step of forming a photoresist film having an opening portion located at the position corresponding to an element isolation area of the silicon substrate on the silicon nitride film or the multilayered film according to a photolithography method; a third step of forming a trench having a pair of tapered side surface portions on the confronting side surfaces thereof on the silicon nitride oxide film or the multilayered film by using the photoresist film as a mask, the tapered side surface portions being inclined toward the substrate side so as to approach each other; and a fourth step of patterning the silicon nitride film and the silicon oxide film by dry etching by using the photoresist fi

Abstract: A preventive treatment method for a multilayer semiconductor structure having a support substrate, at least one intermediate layer and a surface layer in which the surface layer is to be subjected to a subsequent chemical treatment. The method includes forming a protective layer between the intermediate layer and the surface layer. The protective layer is made from a material chosen to be sufficiently resistant to the chemical treatment to protect the intermediate layer from chemical attack.

Abstract: An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be formed of a low-k dielectric material, and a connection portion may be provided to connect the inductors and capacitors in the support layer. The inductors and capacitors are disposed in a stacked structure on the upper and lower sides of the low-k dielectric support layer on the substrate, so that space efficiency may be maximized on the substrate. The low-k dielectric support layer provides support between the inductors and capacitors so that substrate loss is minimized and a Q factor of the inductors is enhanced.

Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhance marking method.

Abstract: An apparatus for cutting at least one thin layer from a substrate or ingot forming element for an electronic or optoelectronic or optical component or sensor. This apparatus includes a device for directing a pulse of energy into the substrate or forming element wherein the pulse has a duration shorter than or of the same order as that needed by a sound wave to pass through the thickness of the weakened zone, and the energy of the pulse is sufficient to cause cleavage to take place in the weakened zone as the energy of the pulse is absorbed therein. The apparatus also includes an assembly for holding or orienting the substrate or ingot forming element so that the energy pulse is completely uniformly directed over the entire surface, through the face and into the substrate or ingot forming element to cause cleavage to take place in the weakened zone as the energy of the pulse is absorbed therein.

Abstract: A method is described for laser scribing or dicing portions of a workpiece using multi-source laser systems. In one embodiment, a first laser uses multiphoton absorption to lower the ablation threshold of portions of the workpiece prior to a second laser ablating the portions of the workpiece. In an alternative embodiment, a first laser uses high energy single-photon absorption to lower the ablation threshold of portions of the workpiece prior to a second laser ablating the portions of the workpiece.

Abstract: A method and system for cutting a wafer comprising a semiconductor substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafer during and after cutting by vacuum pressure through the pores. The wafer is cut by directing UV pulses of laser energy at the substrate using a solid-state laser having controlled polarization. An adhesive membrane can be attached to the separated die to remove them from the mounting surface, or the die can otherwise be removed after cutting from the wafer.

Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.

Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.

Abstract: A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.