Abstract: A flexible circuit has a roll-molded thermoplastic resin base sheet with an integrally molded mounting structure located to receive a light emitting diode device in an illuminating position. The mounting structure is a pin receptacle constructed to receive a pin of the light emitting diode device. An electrically conductive portion is carried by the resin base and positioned for electric connection to conductors of the device. Another flexible circuit carries discrete integrated circuit chips and a field of fastener elements extending from a surface of a resin strip carrying conductive traces interconnecting the chips.

Abstract: The invention presents a new design of C7 or C9 type LED bulb and its embedded PCB electronic circuit board structure, comprising a lamp cover, LEDs, a PCB circuit board and a base. The bulb houses one or multiple number of LEDs. The LEDs are soldered on the PCB board that is embedded inside of the base. The PCB board power input ports connect to the brass base or are directly wired to outside the base. The base and the lamp cover may be attached together by means of bonding (thermal, sonic or solvent), friction interference fit, adhesive or simply by screwing the lamp cover into the threaded base. The PCB board, utilizing a bridge design, allows the LED bulb to be directly powered by 110-120V AC voltage power sources. The simple bulb design significantly reduces the weight of the entire product and power consumption.

Abstract: A mounting assembly (100) for a lamp socket (105) that is adjustable, comprises a bracket (101) configured to be mechanically coupled to a luminaire assembly and a mounting plate (103) configured to attach to the lamp socket and be mechanically coupled to the bracket and selectively engage the bracket at one of a multiplicity of angular rotations. A corresponding method of aligning a lamp to a desired rotational position with respect to a luminaire, includes disengaging a mounting plate from a bracket, where the mounting plate and the bracket are coupled about a common axis of rotation, rotating the mounting plate about the axis to a rotational position corresponding to the desired rotational position of the lamp and re-engaging the mounting plate and the bracket.

Abstract: An adjustable mounting assembly (100, 1201) for a lamp socket (105) comprises a bracket (1203) configured to be mechanically coupled to a luminaire assembly and a mounting plate (1205, 1207) configured to attach to the lamp socket and be mechanically coupled to the bracket and to selectively engage the bracket at one of a plurality of angular positions relative to a lamp socket axis, and at one of a plurality of axis locations relative to the bracket. The mounting plate can include a socket mounting plate and positioning bushing. The positioning bushing has a surface configured with an angular locking member to engage a complimentary locking member on a surface of the socket mounting plate. An opposite surface of the positioning bushing has a complimentary axis locating member configured to engage one of a plurality of axis locating members on the bracket.

Abstract: The invention relates to a device for automatically adjusting the headlight range of a motor vehicle, comprising at least vertically adjustment headlights comprising a control unit provided with a sensor device which is used to detect vehicle and/or ambient data and an evaluation and control device which is used to determine control data for controlling the at least vertically adjustable headlights. The sensor device is embodied as a non-predictable working sensor which is used to detect the vertical roadway curving.

Abstract: A vehicle light apparatus has a lamp bulb that is not visible from the outside and a reflecting area that is not conspicuous when the light is on. An inner lens reflects light, from the lamp bulb toward a lens opening and an outer lens attached to the lens opening covers the lamp bulb. A reflecting area having a lower light transmission rate than the outer lens is provided on the tail lens where it opposes the lamp bulb. Light transmission areas having a higher light transmission rate than the reflecting area are provided on the reflecting area.

Abstract: A motorcycle wherein it is possible to easily identify the state of a headlight and flasher lamps covered with a common outer lens. A a headlight is disposed in a central portion of a light unit in a transverse direction of the motorcycle. A pair of left and right flasher lamps is disposed on left and right sides of the headlight. A common outer lens covers the left and right flasher lamps and the headlight. An upper edge of a light opening in a handlebar cover has left and right interposed parts extending downward to be interposed between the headlight and the left and right flasher lamps.

Abstract: In the bulb cassette in the related art, a mounting fixture can be prevented from coming off a case. However, when a space in the case for accommodating a light bulb is small, there arises a problem such that a wall surface which defines the space is thermally deformed by heat from the light bulb, and hence the product value is lowered, and in the worst case, the entire case may become unusable due to thermal deformation of the wall surface. In a case in which a case formed of resin material having low thermal resistant property such as polypropylene and a wall surface which is in the proximity with a light bulb built in the case exist, a bulb cassette for mounting the light bulb in the case is formed of thermal resistant resin, and a heat shield wall interposed between the light bulb and the wall surface is formed so as to continue from the bulb cassette.

Abstract: A vehicle headlamp is provided with a projection lens disposed on an optical axis extending in a longitudinal direction of the vehicle; a light source disposed at a rear side of a rear side focal point of the projection lens; a reflector which reflects a light emitted from the light source to a front direction toward the optical axis; and an auxiliary lens disposed in front of a peripheral portion of the projection lens. The auxiliary lens controls a deflection of a light reflected from the reflector and transmitted through the projection lens.

Abstract: A headlamp including a metal bracket and a plurality of light source units 50, each unit having a light source, being mounted on the metal bracket 20, and being disposed within a lamp chamber. Irradiation light patterns of the light source units 50 are combined together to form a predetermined light distribution pattern. Each of the light source units 50 includes a resin shade 58, which is fastened to the bracket 20 by a fastening portion and is disposed forwardly of the light source, and a resin lens 52 connected to the shade 58. Part of the fastening portion is made of metal.

Abstract: A light source is situated on a headgear device and placed to direct light toward the pupil of the eye at an intensity that causes the iris to constrict, resulting in a smaller pupil. This prevents the light scattering due to ophthalmic surgery or eye injury from entering the eye, thereby reducing or eliminating visual aberrations.

Abstract: An LED module is disclosed to include a light guide tube, two LEDs provided at the two ends of the light guide tube, a reflector strip, which has an arched reflecting surface for reflecting light from the LEDs, and a converter for converting input power supply to the desired working voltage level for the LEDs.

Abstract: The present invention provides an illuminated decorative item, a decorative item made of ribbon and an illumination circuitry for a decorative item made of ribbon. The illuminated decorative item comprises a decorative body created with at least one elongated strip of material, the body having a base; a light source disposed at the base; an energy source electrically connected to the light source to supply energy to the light source; and at least one optic fiber, each optic fiber comprising an elongated body having a base end and a free end, the base end being close to and oriented towards the light source, the free end being arranged to visually complement the decorative body; wherein the energy source supplies energy to the light source, at least some light emitted by the light source enters the optic fiber at the base end, propagates inside the optic fiber, and exits from the free end thus generating an illumination at the free end and creating a illumination effect for the decorative item.

Abstract: A surface light source comprising a light emitting part (11) consisting of a single spot light source, and a light guide plate (12), wherein a reflection plane (13) is provided on the back side of the light guide plate and a prism pattern (15) is also provided. A directional light diffusion film (14) consisting of at least two light scattering/transmitting phases having different refractive indexes, where one phase having a larger refractive index includes a large number of regions having a columnar structure extending in the thickness direction of the film and the columnar structure is inclining against the normal direction of the film at an angle of 5-60°, is arranged on the light exit surface side of the light guide plate (12) such that the scattering direction of the directional light diffusion film becomes the direction of uneven luminance.

Abstract: An electrical circuit and method for switching an input voltage onto a load by way of an AC control voltage is provided. A voltage magnitude reduction circuit is configured to be driven by the AC control voltage. A rectifier circuit is operably coupled with the voltage magnitude reduction circuit. Also, a voltage limiter circuit is operably coupled with the rectifier circuit, and an energy storage circuit is operably coupled with the voltage limiter circuit. The voltage magnitude reduction circuit, the rectifier circuit, the energy storage circuit and the voltage limiter circuit cooperatively generate a switch control voltage. An electronic switching unit is then configured to switch the input voltage across the load when the switch control voltage is active. In one embodiment, the input voltage is a DC voltage generated by an AC-to-DC voltage converter circuit configured to convert an AC supply voltage to the DC voltage.

Abstract: Embodiments of isolated gate driver circuits are disclosed for driving high- and low-side switching devices for half- and full-bridge power converter topology. Disclosed circuits provide sufficient dead-time, operate over a wide range of duty cycles, and require a single power supply (Vcc). Typical applications for such circuits include cold cathode fluorescent lamp (CCFL) inverters that are powered by a high voltage DC rail.

Abstract: The present invention relates to a switched mode power supply with programmable digital control and to a power supply system comprising a plurality of switched mode power supplies. The input terminals and the output terminals of the switched mode power supply system are separated by an insulation barrier, and the switched mode power supply comprises a conversion stage having at least one switching element. The switching element of the conversion stage, as well as any switching elements of a possible pre-regulator, is digitally controlled by a programmable digital circuit. In one embodiment of the switched mode power supply, the programmable digital circuit is located on the primary side of the insulation barrier.

Abstract: The present invention provides a switching power supply unit capable of suppressing a surge voltage generated in a rectifier element more effectively. A first resonance circuit is constructed by capacitors in a surge voltage suppressing circuit and an inductor, and resonance time of the first resonance circuit is set to be longer than recovery time of a diode in a rectifier circuit. According to at least one of a DC input voltage and an output current, either a first bridge circuit or a second bridge circuit is selectively allowed to perform switching operation. At the time of forward-direction operation, the first resonance circuit is formed by the capacitors in the surge voltage circuit and the inductor on the high voltage side. At the time of reverse-direction operation, a second resonance circuit is formed by the capacitors and an inductor on the low voltage side.

Abstract: A converter circuit is specified for switching a large number of switching voltage levels, which has n first switching groups for each phase, with the n-th first switching group being formed by a first power semiconductor switch and a second power semiconductor switch, and with the first first switching group to the-th switching group each being formed by a first power semiconductor switch and a second power semiconductor switch and by a capacitor, which is connected to the first and second power semiconductor switches, with each of the n first switching groups being connected in series to the respectively adjacent first switching group, and with the first and the second power semiconductor switches in the first first switching group being connected to one another.

Abstract: A switched current power converter includes an input power source, an output terminal, and a plurality of current stages. Each of the current stages includes a converter coupled to the input power source for providing a current and a switch circuit that selectively couples the current in such current stage to the output terminal. A control circuit decouples the input power source from the current stage converters upon detection of a low load condition. Optionally, the power converter includes a low load circuit responsive to the control circuit that selectively couples current to the output terminal during the low load condition.

Abstract: A power supplying apparatus to supply DC power for driving an electronic device, and an electronic device using the same that includes an AC/DC converter which converts input AC power into the DC power; and an AC switch which switches the AC power input to the AC/DC converter, based on a switching signal supplied from the electronic device. Thus, the power supplying apparatus receives information on an operation state of the electronic device from the electronic device to control an input of AC (alternating current) power according to the operation state of the electronic device.

Abstract: Systems and methods for operating a pulse width modulation (PWM) circuit in a direct current (DC) to alternating current (AC) power inverter to reduce the magnitude of harmonics. The PWM circuit operates using a reference signal having an irregular period. This irregular periodicity may comprise a sequence of periods uniformly distributed about a target period.

Abstract: The present invention relates to a method for controlling a polyphase voltage inverter the inverter being designed to control a load in terms of pulse width modulation and to be connected upstream to a voltage source via a DC bus and downstream to an electrical load. It is connected to a control logic which implements said method. A geometric structure is produced while taking account of the constraints downstream and upstream of the inverter. More particularly, an upstream constraint relates to the voltage of the supply source at the input of the inverter. An error vector is also produced.

Abstract: The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

Abstract: Disclosed are improved layouts for memory cell and memory cell arrays. A memory cell array of multiple memory cells connected by signal lines that twist in connecting the array. Further, an eight transistor memory cell that comprises different resistive paths as seen by the signal lines electrically connected to the cell and asymmetric pass devices associated with those resistive paths. Furthermore, an eight transistor memory cell that includes butt contacts.

Abstract: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Abstract: A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.

Abstract: A CPU 52 detects respective voltages across unit cells B1 to Bn and extracts a minimum unit cell having a minimum voltage from the plurality of unit cells B1 to Bn based on the detected voltages. The CPU 52 sets one of cell groups each including two unit cells connected in series except the minimum unit cell as a discharge cell group, and connects the both ends of the discharge cell group to a capacitor C to transfer electric charge from the discharge cell group to the capacitor C and connects the both ends of the minimum unit cell to the capacitor C to transfer electric charge from the capacitor C to the minimum unit cell such that the respective voltages across the unit cells are equalized.

Abstract: A method of operating a ferroelectric random access memory (FRAM) can include reading a low-voltage FRAM monitoring memory array and preventing a read/write-back of an FRAM memory cell array if data read from the low-voltage FRAM monitoring memory array is corrupted.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.

Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract: A solar cell includes a substrate having a horizontal surface, and an electrode layer on the substrate. The electrode has a plurality of vertical surfaces substantially perpendicular to the horizontal surface, and light-harvesting rods are coupled to the vertical surface of the electrode.

Abstract: An SRAM memory cell structure utilizing a read driver transistor for isolating the read current from the latch nodes of the cell during read operations and a column select write transistor for selection of a single cell during write operations, and a method of operating the same is discussed. The SRAM memory cell structure (single-ended or differential cell) allows independent optimization of the static noise margin, trip voltage, and read current, thereby avoiding some of the static noise margin and trip voltage problems of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM memory cell comprises a 7T single-ended cell including first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline.

Abstract: An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from being destructed by a latch-up phenomenon to maintain the stored data certainly even when a soft error occurs due to a neutron.

Abstract: A loadless static random access memory (SRAM) may have transfer transistors with at least two threshold voltages. In some embodiments, the transfer transistors may have gate structures with different portions that produce electric fields in different directions. In some embodiments the transfer gate structures may extend down the sidewalls of an active region. In other embodiments, the transfer transistors may have gate structures with different portions that have different gate lengths.

Abstract: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.

Abstract: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.

Abstract: A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

Abstract: A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number of serial connected resistive devices and provides several reference voltages by voltage division; a data saving circuit outputs a data voltage; a comparing circuit compares the data voltage with the several reference voltages to output a comparing signal; a decoder receives and then decodes the comparing signal to output the data.

Abstract: Charge is trapped into a charge trapping region of one of two reference cells so as to achieve a state equivalent to memory cell characteristics having a smallest amount of current. Charge is trapped into a charge trapping region of the other reference cell so as to achieve a state equivalent to memory cell characteristics having a largest amount of current. Currents output from these reference cells are averaged by a current averaging circuit, and the resultant average current is output as a reference current R_REF 1.

Abstract: A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer adapted to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units. Each read/program unit is associated with at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. Each group comprises at least one signal track shared by the at least two read/program units of the group.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is divided into two electrically isolated word lines that are arranged in the column regions. The memory device further includes a determining circuit for judging which column region a data loaded on a register belongs to during a program operation, and a selecting circuit for choosing one of the rows in response to the row address information and driving one or all of the word lines in the selected row with a program voltage according to the judging.

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.

Abstract: A non-volatile semiconductor memory device comprise a memory cell array having a plurality of memory cell units each having a plurality of electrically-programmable memory cell connected in series, a plurality of word lines each connected to each of control gates of said plurality of memory cells, said plurality of word lines including a selected word line connected to a control gate of selected one of said memory cells for programming, and a plurality of unselected word lines different from said selected word line, a bit line connected to one end of said memory cell unit, and a source line connected to another end of the memory cell unit, wherein, when data is programmed into the selected memory cells, a first potential is supplied to said selected word line, and a first unselected word line adjacent, toward a source line side, to said selected word line is set to floating state, and thereafter, a second potential which is higher than said first potential is supplied to said selected word line.

Abstract: A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

Abstract: A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).

Abstract: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

Abstract: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also Teach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

Abstract: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.