Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristic with high yield. In a method for manufacturing a semiconductor device according to the present invention, a semiconductor layer is formed, a gate insulating film is formed on the semiconductor film, a first conductive layer is formed on the gate insulating film, a second conductive layer is formed on the first conductive layer, the first conductive layer and the second conductive layer are etched to form a first conductive-layer pattern, the second conductive layer in the first conductive-layer pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen to form a second conductive-layer pattern, and a first impurity region and a second impurity region are formed in the semiconductor layer.

Abstract: A process for producing an image display device using a thin film semiconductor device is provided which includes forming a polycrystalline semiconductor thin film on a substrate. A substantially belt-shaped crystal is formed which is crystallized so as to grow crystal grains in a direction substantially parallel to a scanning direction of a CW laser beam by scanning the CW laser beam along the substrate, thereby irradiating the CW laser beam on portions of the polycrystalline semiconductor thin film formed onto the substrate.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.

Abstract: A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a portion of the cap poly layer from the PMOS region. Subsequently, the same resist mask and/or remaining portion of the cap poly layer is employed to form source/drain regions within the PMOS region by implanting a p-type dopant. Afterward, a cap poly thermal process is performed that causes tensile strain to be induced only in channel regions of devices located within the NMOS region. As a result, channel mobility and/or performance of devices located in the PMOS region is not substantially degraded.

Abstract: The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack and a mask formed on the ONO stack, providing a first etching process to form a first spacer surrounding the mask, removing portions of the first spacer and the ONO stack that are not covered by the first spacer and the ONO stack, forming an electrical connection layer between the masks, forming a second spacer surrounding the mask, removing the second spacer to form a gate and removing the mask and the ONO stack which is under the mask.

Abstract: A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

Abstract: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate.

Abstract: A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting an element for promoting a forming speed of each gate oxide film into a region for forming the second gate oxide film of the substrate; and simultaneously forming the first gate oxide film and the second gate oxide film by a thermal oxidation method, wherein in the element implanting step, the element is implanted in space of a depth equal to half the thickness of the second gate oxide film placed in predetermination of its formation from the surface of the substrate in such a manner that with the peak of a concentration distribution of the element as the center, a concentration distribution in which both sides of the peak is given twice as large as a standard deviation of the concentration distribution

Abstract: In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.

Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.

Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: In manufacturing thinned semiconductor chips by grinding a semiconductor wafer supported on a rigid support substrate, in order to remove the semiconductor wafer or semiconductor chips from the support substrate without damage to the semiconductor wafer or semiconductor chips, a semiconductor wafer at its surface is bonded on a light-transmissive support substrate through an adhesive layer having an adhesion force that is reduced upon exposure to light radiation, thereby exposing the back surface of the semiconductor wafer. A tape is bonded to the backside of the semiconductor wafer integrated with the support substrate after grinding, wherein the tape is supported at the periphery. Before or after bonding of the tape, light radiation is applied to the adhesive layer at a side close to the support substrate to reduce the adhesion force in the adhesion layer.

Abstract: An apparatus and a system for separating dice from a substrate are described herein.

Abstract: A method of crystallizing polysilicon, a method of fabricating a thin film transistor using the same, and a method of fabricating a liquid crystal display thereof form a polysilicon layer having uniformly oriented crystalline grains with high quality. A polysilicon crystallizing method includes forming a polysilicon layer on a substrate, making grains of the polysilicon layer amorphous except a portion of the grains having specific orientation, and crystallizing the polysilicon layer using the grains having the specific orientation.

Abstract: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.

Abstract: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0?y<1.

Abstract: A group III nitride underlayer including at least Al, having a dislocation density of ?1×1011/cm2 and a (002) plane X-ray rocking curve half-width value of ?200 seconds is formed on a set base material. A p-type semiconductor layer group is formed above the group III nitride underlayer and includes a group III nitride in which the Ga content relative to the total group III elements is ?50% and in which a carrier density is ?1×1016/cm3. A light-emitting layer is formed on the p-type semiconductor layer group and includes plural mutually isolated insular crystals. An n-type semiconductor layer group is formed on the light-emitting layer and includes a Ga content relative to the total group III elements of ?50%.

Abstract: An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.

Abstract: A high-frequency wiring structure includes a microstrip line having a ground conductor, a dielectric disposed on the ground conductor, and a transmission conductor that is at least partially disposed in the dielectric. The transmission conductor is defined by a flat bottom parallel to the ground conductor, a pair of flat sides that are perpendicular to the ground conductor and are positioned on both sides of the flat bottom in the wiring width direction, and curved parts that continuously join the flat bottom and the pair of flat sides. The curved parts have a radius of curvature within the range of 5% to 50% of the thickness of the transmission conductor.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating film. A sacrificial film is formed to fill the via hole. Portions of the intermetal insulating film and the sacrificial film are removed to form a trench. The sacrificial film is removed to expose the portion of the surface of the etch stop film. A plasma etching process is performed at a predetermined temperature using an etching gas to remove the exposed portion of the etch stop film and to prevent or suppress generation of a polymer. A diffusion barrier film is formed within the trench and the via hole such that the diffusion barrier contacts the lower metal film. An upper metal film is formed on the diffusion barrier.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within a CVD reactor is carried out to deposit a low-k dielectric film stack on the first dielectric barrier until thickness of the low-k dielectric film stack reaches a desired value, wherein each of the CVD cycles comprises: (1) chemical vapor depositing a low-k dielectric film having a pre-selected thickness; and (2) cooling down the low-k dielectric film within the CVD reactor. A second damascened copper interconnect structure is formed in the low-k dielectric film stack.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent, which controls the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less, is used as the slurry, and the pad which is made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253 and which is comprised of the foam including non-uniform pores with a diameter of about 150 ?m or larger and a density of about 0.4–0.16 g/cm3, is used as the polishing pad.

Abstract: A method comprises forming a low-dielectric constant (low-k) layer over a semiconductor substrate, forming an anti-reflective layer over the low-k layer, forming at least one opening in the anti-reflective layer and in the low-k layer, forming a nitrogen-free liner in the at least one opening, and forming at least one recess through the nitrogen-free liner, the anti-reflective layer, and at least partially into the low-k layer, the at least one recess is disposed over the at least one opening.

Abstract: After forming a stopper film on a semiconductor substrate having a copper wiring layer therein, an interlayer insulating film made of a low dielectric constant material is formed on the stopper film. Then, after forming a capping film on the interlayer insulating film, a resist film having a predetermined pattern is formed on the capping film. The capping film and the interlayer insulating film are etched using the resist film as a mask to form an opening reaching the stopper film. After that, the stopper film exposed by the opening is etched, with the resist film left in place, to form a via hole. Then, the resist film is removed by ashing.

Abstract: The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.

Abstract: A method and system is described for preparing a film stack, and forming a feature in the film stack using a plurality of dry etching processes. The feature formed in the film stack can include a gate structure having a critical dimension of approximately 25 nm or less. This critical dimension can be formed in the polysilicon layer using four mask layers.

Abstract: A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: A semiconductor device manufacture method includes the steps of forming a resist layer above a work target layer; exposing and developing the resist layer to form resist patterns including isolated pattern and dense patterns; monitoring widths of isolated and dense pattern of the resist patterns to determine trimming amounts of linewidths to be reduced; determining etching conditions for realizing the trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching; trimming the resist pattern under said determined etching conditions; and etching the work target layer by using said trimmed resist patterns. A desired pattern width an be realized stably by trimming using plasma etching.

Abstract: A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.

Abstract: Provided is a method for forming a fine pattern of a semiconductor device by controlling the amount of flow of a resist pattern, including forming a resist pattern having a predetermined pattern distance on a material layer to be etched, forming a flow control barrier layer on the resist pattern to control the amount of flow during a subsequent resist flow process and to make the profile of the flowed pattern be vertical, optionally forming the flow control barrier layer by coating a material including a water-soluble high-molecular material and a crosslinking agent on the resist pattern, mixing and baking the coated material layer, and processing the resultant structure using deionized water, carrying out the flow resist process to form a hyperfine pattern and etching the lower material layer, and thereby forming fine patterns having the shape of contact holes or lines and spaces to have a critical dimension of about 100 nm or less, even with use of a KrF resist.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

Abstract: Disclosed is a method for non-destructive removal of cured epoxy from a wafer backside. A wafer back-coated with epoxy is soaked in an acetone bath for a period of time, allowing degradation of the epoxy coating adhesion strength. The epoxy coating is then peeled or scraped away, leaving the wafer backside ready for a rework or for a reapplication of a new epoxy coating.

Abstract: A method of depositing polymer thin films on a MEMS device having a wafer stack includes depositing one or more protection films on a polymer thin film layer on the wafer stack, fabricating the MEMS device, and removing the one or more protection films.

Abstract: A substrate processing apparatus has a substrate holder for detachably holding a substrate so that a surface, to be processed, of the substrate faces downward, and a sealing ring for sealing a peripheral portion of the surface, to be processed, of the substrate held by the substrate holder. The substrate processing apparatus also has a plurality of ejection nozzles disposed below the substrate holder for ejecting a treatment solution toward the surface, to be processed, of the substrate held by the substrate holder, and a mechanism for rotating and vertically moving the substrate holder and the ejection nozzles relative to each other.