Abstract: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.

Abstract: A method of detaching a thin film from a source substrate comprises the steps of implanting ions or gaseous species in the source substrate so as to form therein a buried zone weakened by the presence of defects; and splitting in the weakened zone leading to the detachment of the thin film from the source substrate. Two species are implanted of which one is adapted to form defects and the other is adapted to occupy those defects, the detachment being made at a temperature lower than that for which detachment could be obtained with solely the dose of the first species.

Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer.

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1?x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10–25 ?m and more particularly 15–18 ?m, or a frequency ranging from 12–30 THz and more particularly 16.5–20 THz.

Abstract: The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

Abstract: The invention generally encompasses a method for forming a pattern on a substrate. The method comprises applying a precursor comprising at least one metal to a substrate to form a precursor layer, exposing a predetermined portion of the precursor layer and developing the predetermined portion of the precursor layer. The developing step removes, or at least substantially removes, the predetermined portion from the substrate, thereby forming a pattern on the substrate that comprises a remaining portion of the precursor. In one embodiment, the precursor layer comprises Ti(PriO)2(EAA)2.

Abstract: The present invention provides a manufacturing method that allows a Group III nitride substrate with a low dislocation density to be manufactured, and a semiconductor device that is manufactured using the manufacturing method. The manufacturing method includes, in an atmosphere including nitrogen, allowing a Group III element and the nitrogen to react with each other in an alkali metal melt to cause generation and growth of Group III nitride crystals. In the manufacturing method, a plurality of portions of a Group III nitride semiconductor layer are prepared, selected as seed crystals, and used for at least one of the generation and the growth of the Group III nitride crystals, and then surfaces of the seed crystals are brought into contact with the alkali metal melt.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

Abstract: A method for mounting a passive component on a wafer. A passivation layer is disposed on a wafer having at least one first metal pad and at least one second metal pad thereon, which substantially exposes the first and second metal pads. A capping layer is formed on the exposed first metal pad, and an under ball metallurgy (UBM) layer is formed on the exposed second metal pad. A photoresist pattern layer is formed overlying the wafer to cover the capping layer and the passivation layer and expose the UBM layer. A solder bump is formed on the exposed UBM layer. After the photoresist pattern layer and the capping layer are successively removed, a passive component is mounted on the wafer through the solder bump.

Abstract: The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially amorphous region and at least one substantially crystalline region is provided over the substrate. The at least one substantially amorphous region of the first material is replaced with a second material, while the at least one substantially crystalline region is not replaced. The invention also includes a circuit construction comprising an electrically conductive material extending within openings in a substantially crystalline electrically insulative material, and in which the electrically conductive material corresponds to quantum dots.

Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Abstract: A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the second mask layer; forming a connection hole pattern for forming connection holes in the second and first mask layers and the organic sacrificing layer; forming a wiring groove pattern in the first mask layer and the organic sacrificing layer and forming the connection holes in the second insulation film, by etching conducted by use of the second and first mask layers as an etching mask; and forming the wiring grooves in the second insulation film and forming the connection holes in the second and first insulation films, by use of the first mask layer and the organic sacrificing layer as a mask.

Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.

Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.

Abstract: The present invention discloses methods for manufacturing a metal line of a semiconductor device that can prevent undesirable etching of an edge of an interlayer insulating film. In accordance with the method, a lower metal line exposed by a via contact hole is covered by a photoresist film pattern which is formed via an exposure and development process using an upper metal line mask. An etching process is performed using the photoresist film pattern as a mask to form the upper metal line region that is then filled to form an upper metal line after removing the photoresist film pattern.

Abstract: A method for fabricating an electronic device includes: a step of forming a first conductor to become a wiring or a wiring plug in a first insulating film; a step of forming a second insulating film on the first insulating film and the first conductor and, after that, forming a hole reaching the top face of the first conductor in the second insulating film; a step of forming a first barrier metal film on a bottom and side walls of the hole and on the second insulating film; a step of removing a portion formed on the bottom of the hole in the first barrier metal film to thereby expose the top face of the first conductor; a step of performing a plasma process using a reducing gas after the step of exposing the top face of the first conductor; and a step of forming a second conductor to become a wiring plug or a wiring by filling a conductive film in the hole after the step of performing the plasma process.

Abstract: An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The contact plugs are preferably formed in a different process step than the interconnects.

Abstract: In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.

Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.

Abstract: A method for producing a contact structure on a structured surface comprising producing a first conductive layer on the structured surface, wherein the first conductive layer comprising tungsten. A conductive seed layer is produced on the first conductive layer, the contact structure being produced by electroplating on the seed layer. The first conductive layer serves as an etch stop for selectively removing substrate material from the backside.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.

Abstract: An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.

Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A manufacturing method of a semiconductor device includes forming a cobalt film on a silicon substrate on which a diffusion layer is formed, forming a titanium film on the cobalt film using a titanium target having a surface from which a nitride film has previously been removed, forming a titanium nitride film containing titanium on the cobalt film by a reactive sputtering process using a nitrogen gas and the titanium target, and performing an annealing to react the cobalt film with the silicon substrate, thereby accomplishing silicification.

Abstract: In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

Abstract: The semiconductor device fabrication method comprises the step of forming a conducting film 22 by CVD, so as to cover a first surface and a second surface of a silicon substrate 10; the step of removing the conducting film 22 at least in a first region of the first surface of the silicon substrate 10; and the step of forming a gate insulation film 28 in the first region of the first surface of the silicon substrate 10. The semiconductor fabricating device further comprises after the step of forming a conducting film 22 and before the step of forming a gate insulation film 28 the step of removing the conducting film 22 on the second surface of the silicon substrate 10. In the step of forming a gate insulation film 28, the gate insulation film 28 is formed with the silicon substrate 10 exposed over the second surface of the silicon substrate 10.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: Methods and apparatus for cleaning a semiconductor substrate that significantly reduce the number of particles falling onto the substrate during cleaning by coating all interior surfaces within a processing chamber with an adhesion film that has an increased sticking coefficient for any subsequently arriving etched species to promote a continuous film growth and improve adhesion of such etched species. Due to its increased sticking coefficient, this adhesion film reduces surface mobility of any arriving by-products to enable the growth of the continuous film of etched species. The continuous film of etched species adheres firmly to the adhesion film such that the etched species are prevented from flaking off and falling onto the substrate being cleaned. The methods and apparatus may clean a plurality of semiconductor substrates, whereby a plurality of adhesion films are sequentially deposited over a plurality of continuous film growths of removed materials for cleaning the substrates.

Abstract: A method for plasma treating an etched opening formed in a porous low-K material to improve barrier layer integrity including providing a substrate comprising an etched opening formed in an insulating dielectric layer including porous low-K silicon oxide according to an overlying patterned resist layer; plasma treating according to a plasma process the etched opening to remove the resist layer and increase a surface density of the insulating dielectric layer within the etched opening; and, blanket depositing a barrier layer over the etched opening.

Abstract: A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so as to form a prescribed circuit pattern in the resist film. Then, the wafer W is etched so as to form a via hole in the porous low-k film, followed by processing the wafer with a hydrogen peroxide solution so as to denature the resist film. Further, the sacrificial film is dissolved in a pure water so as to strip the resist film and the antireflection film from the water. As a result, a via hole excellent in the accuracy of the shape is formed without doing damage to the dielectric film.

Abstract: The present invention provides a method for evaluating a solution for a coating film for semiconductor, which comprises measuring Clogging Degree of a solution for a coating film for semiconductor when the solution is filtrated through a filter having an average pore size of 0.01 to 0.4 ?m, and estimating quality of the coating film formed from the solution, wherein the Clogging Degree is defined by the following formula: Clogging Degree=V2/V1 V1: A value of linear velocity of filtrate (filtrating rate per 1 cm2 of filter (g/(cm2·min)) at initial standard point in the case that a solution is filtrated at a fixed pressure and temperature V2: A value of linear velocity of filtrate at the point the predetermined weight of filtrate discharged from the initial standard point According to the present method, quality of coating films can be figured out without actual formation of the coating films, and solutions for coating films can be evaluated thereby.

Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.

Abstract: In forming a high density plasma oxide film, a projection shaped like the mesa, the peaked roof, the cone or the like is formed on an element formation region. This projection gives rise to a problem of producing a polishing scar when the CMD (Chemical Mechanical Polishing) with a ceria slurry is performed. A film having a polishing rate equivalent to the one of the high density plasma oxide film is formed on the high density plasma oxide film to reinforce a projection in the shape of a triangular prism, a cone or such, and, thereafter, the polishing is carried out, using a ceria slurry. In another method, after the first CMP polishing is performed, using a silica slurry containing grains of small particle size which make no aggregation, the second CMP polishing is performed, using a ceria slurry.

Abstract: This invention is generally related to a method of making a molecule-surface interface comprising at least one surface comprising at least one material and at least one organic group wherein the organic group is adjoined to the surface and the method comprises contacting at least one organic group precursor with at least one surface wherein the organic group precursor is capable of reacting with the surface in a manner sufficient to adjoin the organic group and the surface.

Abstract: A semiconductor structure including an insulator layer formed of a first polymer. The structure also includes an organic semiconductor layer formed of a second polymer. The polymers self-assemble into a well-ordered co-polymer structure with the semiconductor layer positioned adjacent the insulator layer. The structure may be an organic, thin-film semiconductor device including, without limitation, a transistor, a multi-gate transistor, a thyristor, and the like. Also disclosed is a process of manufacturing the semiconductor structure.

Abstract: A commercially available product, of a type having a batting with a softness and flexibility and configured for use in the formation of a quilt, where the quilt has at least one cover to be securably attached to the batting, includes a composite member sold in at least one desirable size for making a quilt and formed of the batting and an adhesive material as an article of manufacture, is disclosed. The batting consists of a fibrous material and the adhesive material includes a water-soluble material and is effective to form a removable bond at the opposing faces of the batting, so that the quilt may be formed by at least temporary attachment of the cover to the batting by the bond and the bond is removable after formation of the quilt.

Abstract: Disclosed is an absorbent structure having wet integrity greater than about 4.0 mN/gsm, softness greater than 8.0/J, pliability greater than about 70/N, and providing a substantially dry liquid-accepting surface after receiving a quantity of liquid. The structure includes an upper ply having an upper fluid receiving surface and a lower surface and including (i) a top stratum including synthetic matrix fibers bonded with a binder, the matrix fibers having length from about 2 to about 15 mm; (ii) a middle stratum in fluid communication with the top stratum, the middle stratum including natural fibers, superabsorbent particles and a binder; and (iii) a bottom stratum in fluid communication with the middle stratum, the bottom stratum including natural fibers and a binder.

Abstract: The present invention provides an internally-tufted laminate adapted to provide improved softness and cloth-like feel.

Abstract: The invention relates to a laminate comprising a first web of fibers and a first film that together form a first ply and a second web of fibers and a second film that together form a second ply, wherein an adhesive layer is disposed between the plies and serves as a grease barrier. A laminate according to the invention serves as a grease barrier without the need for fluorochemical treatment. The invention also relates to a method of making a laminate comprising forming a first ply and a second ply and applying an adhesive layer between the plies. The invention also relates to an article comprising a laminate and a charge of oil and popcorn.

Abstract: Thick film conductive copper pastes that are lead-free and cadmium-free. The inventive copper pastes possess desirable characteristics, including good solderability, good wire bondability, a low firing temperature, and a wide temperature processing window, and provide excellent adhesion to a variety of substrates, including alumina and glass coated stainless steel substrates, as well as low resistivity, and a microstructure after firing that is dense and substantially free of pores.

Abstract: A refractory system for glass melting furnaces includes alumina, zirconia, and silica mixed with a silica binder. The refractory may be formed as refractory blocks or directly onto the wear portion of a glass melting furnace. The refractory may be formed using casting, pumping, or shotcreting methods.

Abstract: To provide a ceramic composition and a ceramic wiring board that can be formed by the firing at a low temperature of 1,000° C. or less, has high strength and is advantageous when electronic component regions utilizing a ceramic layer are formed thereon. A raw ceramic material or calcined powder thereof having a composition consisting of 100 parts by mass of a main component that consists of 52 to 62% by mass of SiO2, 12 to 22% by mass of MgO, and 21 to 32% by mass of CaO and 0.5 to 3 parts by mass of a boron component in terms of the oxide form is molded and fired to obtain a ceramic composition that contains a diopside crystal as a primary crystal. By forming a wiring layer with conductive material on a substrate made of the ceramic composition, a ceramic wiring board is obtained.

Abstract: A piezoelectric/electrostrictive ceramic composition containing, as a major component, a Pb(Mg1/3Nb2/3)O3—PbTiO3—PbZrO3 ternary solid solution system composition and further containing Ni in an amount of 0.05 to 3.0% by mass in terms of NiO and Si in an amount of 0.003 to 0.01% by mass in terms of SiO2. The piezoelectric/electrostrictive ceramic composition can constitute a piezoelectric/electrostrictive body or a piezoelectric/electrostrictive portion both having an excellent piezoelectric/electrostrictive property and durability even under high-temperature and highly humid conditions.

Abstract: A production method of a dielectric ceramic composition having a step of firing dielectric material including a main component ingredient and a subcomponent ingredient, wherein said main component ingredient before firing is barium titanate ingredient powder having the perovskite type crystal structure expressed by ABO3, and a ingredient powder having a ratio A/B of A site components and B site components of 1.006?A/B?1.035 and the specific surface area of 8 to 50 m2/g is used. According to the invention, a dielectric ceramic composition having preferable electric characteristics and temperature characteristic can be provided even in the case of being composed of fine particle and a capacitor made to be a thin layer.