Abstract: A compact radio equipment includes internal circuits on two or more printed circuit boards electrically connected to each other and securely mounted in structure. With this structure, a first metal shield frame is mounted on a first printed circuit board to cover components mounted on the first printed circuit board. A second printed circuit board is mounted on the first metal shield frame.

Abstract: An electronic device that includes a housing that defines an envelope and that defines a horizontal routing channel within the envelope. A plurality of boards is arranged horizontally within the housing and at least one board includes input-output ports. At least one communication conduit is coupled to an input-output port. The boards that include input-output ports are recessed with respect to the envelope and are arranged such that the input-output ports are adjacent to the routing channel. Communication conduits are routed through the routing channel.

Abstract: Rectifying elements are connected in parallel with switching elements 4-1 through 4-4 in a switching section 4 for the lower voltage side and rectifying elements are connected in parallel with switching elements 5-1 through 5-4 in a switching section 5 for the higher voltage side. An LC resonant circuit 6 is provided between the winding wire 3-2 for the high-voltage side in the transformer 3 and the switching section 5 for the higher voltage side; currents which flows on the primary side and the secondary side is changed into a sinusoidal one; and switching is executed in the vicinity of the zero crossing points of the currents.

Abstract: A low power, high voltage power supply system includes a high voltage power supply stage and a preregulator for programming the power supply stage so as to produce an output voltage which is a predetermined fraction of a desired voltage level. The power supply stage includes a high voltage, voltage doubler stage connected to receive the output voltage from the preregulator and for, when activated, providing amplification of the output voltage to the desired voltage level. A first feedback loop is connected between the output of the preregulator and an input of the preregulator while a second feedback loop is connected between the output of the power supply stage and the input of the preregulator.

Abstract: Independent phase output voltage control for a 3-phase 4-wire DC/AC inverter, for example, is provided. With the independent phase output voltage control, all three phase output voltages from the DC/AC inverter can be separately and effectively controlled to provide balanced 3-phase voltages from the DC/AC inverter to an unbalanced load, and/or to provide unbalanced 3-phase voltages from the DC/AC inverter to a balanced or unbalanced load. The independent phase output voltage control method can be applied to an inverter power system, with outputs of N-phase (N+1) wire configurations. Here, N can be any integer number greater than zero.

Abstract: A switch mode power supply has pulse width modulation (PWM) frequency dithering of a PWM clock frequency. The PWM frequency dithering circuit may change the frequency of the PWM clock based upon each of a plurality of frequencies. A PWM time base circuit may comprise a period register containing a PWM period value, a comparator, and a PWM counter, wherein a PWM count value may be incremented in the PWM counter by the variable frequency PWM clock, the comparator may compare the PWM period value with the PWM count value and when the PWM period value and the PWM count value are substantially equal the PWM count value may be reset.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, and a charge pump type step-up circuit formed in the semiconductor substrate. The step-up circuit includes a charge pump circuit and a bipolar transistor. The charge pump circuit has an input line to which a power supply voltage is to be applied, and an output line through which an output voltage is to be output. The bipolar transistor is formed in the semiconductor substrate so as to be provided between the input line and the output line. The bipolar transistor is constituted so as to be turned ON when an absolute value of the output voltage is lower than an absolute value of the power supply voltage, and so as to be turned OFF when the absolute value of the output voltage is higher than the absolute value of the power supply voltage.

Abstract: AC module makers must prepare two types of AC modules for the 100-V and 200-V outputs only for domestic supply. For foreign countries, the makers must manufacture AC modules compatible with more system voltages. To solve these problems, the control circuit of an AC module controls the operation of an inverter circuit and/or the transformation ratio of a transforming circuit, and ON/OFF-controls a switch on the basis of the system voltage and connection state of an electric power system.

Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Abstract: The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.

Abstract: Each of switching circuits included in each of semiconductor memory chips performs switching among interface functions of predetermined second external connecting electrodes by bonding options in accordance with states of potentials applied to first external connecting electrodes. The second external connecting electrodes intended for interchange of the interface functions are electrodes for plural-bit parallel input/output and electrodes for the input of control signals. For example, the switching circuit interchanges interface functions among the predetermined second external connecting electrodes and switches between valid and invalid states of the interface functions of the predetermined second external connecting electrodes.

Abstract: A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a direction perpendicular to the bit line at an average array pitch greater than eight times the pitch of the bit lines.

Abstract: A semiconductor device includes a memory cell array, word lines, a selector, driving lines and transfer transistors. The memory cell array includes electrically rewritable nonvolatile memory cells. The word lines are commonly connected to memory cells arranged in the same row. The selector configured to select memory cells corresponding to the plurality of word lines in the array. Each driving line is corresponding to one of the word lines. Transfer transistors selectively connect one of the word lines and one of the driving lines. A first word line is connected to a first control gate, a second word line next to the first word line connect to a second control gate, and a third word line next to the second word line connected to a third control gate which is arranged next to first control gate.

Abstract: A ferroelectric memory device includes a plurality of memory cells, each memory cell includes a ferroelectric capacitor and a transistor, a plate line drive unit capable of providing a first voltage to the memory cell array in response to a plate line drive signal, and a reference voltage generating device. The reference voltage generating includes a reference cell block having a plurality of reference cells, each reference cell including a ferroelectric capacitor and a transistor, and a reference plate line drive to provide a reference plate line voltage to at least one reference cell in response to a plate line drive signal and a reference voltage generation signal, where each reference cell generates a reference voltage in response to the reference plate line voltage.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

Abstract: An eight transistor static random access memory (SRAM)device includes first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.

Abstract: A ferromagnetic thin-film based digital memory having a bit structures therein a magnetic material film in which a magnetic property thereof is maintained below a critical temperature above which such magnetic property is not maintained, and may also have a plurality of word line structures each with heating sections located across from the magnetic material film in a corresponding one of the bit structures. These bit structures are sufficiently thermally isolated to allow selected currents in the adjacent word lines or in the bit structure, or both, to selectively heat the bit structure to approach the critical temperature. Such bit structures may have three magnetic material layers each with its own critical temperature for maintaining versus not maintaining a magnetic property thereof.

Abstract: A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.

Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract: Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays.

Abstract: A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

Abstract: A non-volatile memory device having a unit cell, the unit cell including a transistor, word lines, a first bit line and a second bit line. The transistor includes a gate oxide layer on a substrate, polysilicon gate, sidewall floating gates, block oxide layers formed between the polysilicon gate and sidewall floating gates, the block oxide layers also comprising first block oxide layer and second block oxide layer, and source and drain regions. The word lines are vertically placed on the substrate and connected to the polysilicon gate. The first bit line is orthogonally placed to the word lines and connected to the source region and a second bit line is orthogonally placed to the word lines and connected to the drain region.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: A data processor includes an authentication circuit for judging access right. The data processor further includes a nonvolatile memory cell array formed on an insulator film of a chip, and a conductor layer provided between a logic circuit of the authentication circuit and the nonvolatile memory cell array. The nonvolatile memory cell array can store at least part of authentication information or an authentication program.

Abstract: A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).

Abstract: A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (?18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.

Abstract: A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical characteristic, such as the number of series-connected devices forming the NAND string, but both groups are disposed in a region of the memory array traversed by a plurality of global array lines. The memory array may include a three-dimensional memory array having more than one memory plane. Some of the NAND strings of the first group may be disposed on one memory plane, and some of the NAND strings of the second group may be disposed on another memory plane. In some cases, NAND strings of both groups may share global array lines.

Abstract: A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.

Abstract: P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic hole-electron pairs to be generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Various circuits incorporating such fuse or antifuse elements are also disclosed.

Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.

Abstract: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

Abstract: Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines.

Abstract: A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.

Abstract: The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

Abstract: A datum is stored in a memory by placing a memory cell in a first state that is indicative of the datum, and later placing the same or a different cell in a second state that is indicative of the same datum. If a different cell is placed in the second state, both cells are programmed to store the same number of bits, and then preferably the first cell is erased. Preferably, the first cell is placed in the first state by the application thereto of a first train of voltage pulses until the cell's threshold voltage exceeds a first reference voltage, and the first or second cell is placed in the second state by the application thereto of a second train of voltage pulses until the cell's threshold voltage exceeds a second reference voltage.

Abstract: An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. In an exemplary sense amplifier circuit having matched cross-coupled PMOS load devices, a data dependent threshold mismatch between the PMOS devices resulting from a Negative Bias Temperature Instability (NBTI) effect may be reduced by biasing both of the matched PMOS devices so that both experience an initial NBTI Vt shift, and so that any expected further Vt shift in either device over the product lifetime is reduced.

Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.

Abstract: A data readout circuit for reading memory data from a resistance change memory disposed at a point where a bit line and a word line intersect by setting a potential of the bit line to a predetermined bias potential and detecting a current value flowing in the resistance change memory, includes a capacitance device connected to the bit line via a switching device; and a current supply circuit connected to both ends of the switching device to provide a current to the bit line such that the potential of the bit line is equal to a potential of the capacitance device.

Abstract: It is capable of adjusting the pulse width regardless of an amount of delay in a delaying part by controlling pulse width of an output signal based on an externally provided control signal. A pulse width adjusting circuit for use in a semiconductor memory device comprises a unit operable at least partially by a pulse width control signal that is provided externally. The unit has an ability of adjusting pulse width of an output signal by using the pulse width control signal in test mode of the semiconductor memory device.

Abstract: In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.

Abstract: A delay locked loop (DLL) power supply circuit for use in a semiconductor memory device, including: a DLL power supplier for supplying a DLL power supply voltage to a DLL in response to a reference voltage and a clock enable exit pulse signal; and a pulse signal generator for generating the clock enable exit pulse signal in response to a clock enable signal.

Abstract: Systems and methods provide sense amplifier timing techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of memory cells and a sense amplifier that provides a sense amplifier output signal based on data provided by the plurality of memory cells, with the sense amplifier output signal provided under control of a sense amplifier enable signal. A delay control circuit provides a delay to the sense amplifier enable signal based on a value provided by at least one configuration fuse.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: Provided is directed to a semiconductor memory device and a method of driving the same capable of improving a repair efficiency with comparison to the conventional method which repairs all the redundancy row even when a defective cell is occurred in only one cell, by including: a memory cell array which is comprised of at least more than one redundancy block and redundancy segment by means of dividing it into a plurality of blocks toward a row direction and then dividing the blocks into a plurality of segments; a control circuit for storing a repair information of a defective cell and for repairing the segment generating the defective cell to the redundancy segment according to the repair information by inputting a row address signal and a column address signal.

Abstract: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a host-side memory channel port and a downstream memory channel port, allowing multiple modules to be chained point-to-point. In the present disclosure, a separate bus, such as a low-speed system management bus, connects to a memory module buffer. In response to commands received over the system management bus, the memory module can initiate commands and transmit those commands over its downstream memory channel port as if the commands originated from a host connected to the host-side memory channel port. This functionality allows module-to-module memory channels and memory modules to be tested independent of a host memory controller and host memory channel. Other embodiments are described and claimed.