Abstract: A photovoltaic device includes at least a first electrode, a first-conductivity-type layer composed of non-single-crystalline silicon, a second-conductivity-type layer composed of polycrystalline silicon, a third-conductivity-type layer composed of non-single-crystalline silicon, and a second electrode, wherein the contact surface of the first electrode with respect to the first-conductivity-type layer has a shape interspersed with a plurality of projections, and the lower limit and the upper limit of the density of the projections interspersed on the surface of the first electrode satisfy the following equations, provided that the thickness of the second-conductivity-type layer is t ?m: Lower limit=0.312 exp(?0.60t) pieces/?m2 Upper limit=0.387 exp(?0.

Abstract: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the foregoing, for the download of information to the device.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

Abstract: A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces 110b remain unencapsulated. A copper heat slug (404) may be attached to chip surface (101b) using thermally conductive adhesive (403). Chip surface (101a), protected by an overcoat (103) has metallization traces (102). Copper-filled windows (107) contact the traces and copper layers (105) parallel to traces (102). Copper bumps (108) are formed on each line in an orderly and repetitive arrangement so that the bumps of one line are positioned about midway between the bumps of the neighboring lines. A substrate has elongated leads (110) oriented at right angles to the lines; the leads connect the corresponding bumps of alternating lines.

Abstract: A chip coil has a chip format including a rectangle substrate of an insulating resin material and a coil portion having a solenoid structure a part of which is embedded within the substrate and in which adjacent coils are insulated from each other by the substrate. The resin material contains a magnetic filler. The chip coil has a thickness of 50 ?m or less.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1.0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1.0-?m thick and its surface dislocation density is less than 106/cm2.

Abstract: The invention relates to a wafer inspection device. The device comprises an air-cushion stage which can be displaced in two directions (X,Y) that are perpendicular to one another. Several air nozzles are provided for this purpose. At least one valve is connected to at least one electric control unit, the valve being configured in such a way that a normal pressure prevails in the air nozzles when the electric control unit delivers a corresponding signal.

Abstract: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Abstract: An insulating target material for obtaining a conductive complex oxide film represented by a general formula ABO3, the insulating target material including an oxide of an element A, an oxide of an element B, and at least one of an Si compound and a Ge compound.

Abstract: It is an object of the present invention to provide a substrate for sensors and a container, wherein the adhesiveness of the substrate to a thin film is improved, a physiologically active substance can be immobilized without the peeling of the thin film from a plastic substrate, and non-specific adsorption during the analysis of interaction among biomolecules is small. The present invention provides a substrate for sensors, which has a thin film layer on a plastic substrate, wherein the plastic substrate has been treated with an organic primer before formation of the thin film.

Abstract: An anisotropically conductive sheet that can surely achieve necessary electrical connection even to an object to be connected, the arrangement pitch of electrodes to be connected of which is extremely small, a production process thereof, and applied products equipped with the anisotropically conductive sheet. The anisotropically conductive sheet according to the present invention has an insulating sheet body formed of an elastic polymeric substance, in which a plurality of through-holes for forming conductive paths, each extending in a thickness-wise direction of the insulating sheet body, have been formed, and conductive path elements integrally provided in the respective through-holes for forming conductive paths of the insulating sheet body.

Abstract: A touch pad module with electrostatic discharge protection is disclosed. The touch pad module comprises a casing, a metal sheet, a touch pad and a metal holder, wherein the casing covers the metal sheet and has a first opening to expose a portion of the touch pad. The metal sheet is disposed on the touch pad and has a second opening corresponding to the first opening. The extension of the metal sheet contacts the metal holder and the metal holder is disposed under the touch pad.

Abstract: The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.

Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.

Abstract: A chip type LED which is capable of laterally emitting light from the light emitting diode chip and having a relatively small thickness is provided. The chip type LED includes an insulating substrate 12, a light emitting diode chip 15 mounted on the upper surface of the insulating substrate, and a transparent package 16 provided on the upper surface of the insulating substrate to hermetically seal the light emitting diode chip. The light emitting diode chip 15 is mounted on the upper surface of the insulating substrate with the anode electrode 15f of the light emitting diode chip oriented downward and the cathode electrode 15a oriented upward.

Abstract: A clip-less packaged semiconductor device includes at least one semiconductor die having bottom and top surfaces each having at least one electrode. A leadframe comprising a sheet of conductive material having top and bottom surfaces, the top surface being substantially planar, the bottom surface having a recessed region having a thickness less than the thickness of the sheet of conductive material formed in the sheet and defining a plurality of planar lead contacts, is electrically coupled to the top surface of the die at its bottom surface in the recessed region. An encapsulating layer partially encloses the leadframe and die, wherein the encapsulating layer occupies portions of the recessed region not occupied by the die, wherein the bottom surface of the die and the plurality of leadframe contacts are exposed through the encapsulating layer at least at the bottom surface of the packaged semiconductor device.

Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.

Abstract: The semiconductor device (11) of the invention comprises a circuit and a protecting structure (50). It is provided with a first and a second security element (12A, 12B) and with an input and an output (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. The device is further provided with measuring means, processing means and connection means. The processing means transform any first information received into a specific program of measurement. Herewith a challenge-response mechanism is implemented in the device (11).

Abstract: This invention discloses a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure; and at least one packaging layer which is sealed over the microstructure by means of an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer. A method of producing a crystalline substrate based device is also disclosed.

Abstract: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary substrate. With the surface of the chips coplanar with the surface of the complete structure without any gaps, interconnect metal lines can be easily placed on the uninterrupted surface, connecting the chips and other components.

Abstract: A bumpless chip package including at least a panel-shaped component, a chip, an interconnection structure and a conductive channel is provided. The chip is disposed on the panel-shaped component. The chip has a plurality of chip pads disposed on an active surface of the chip. The interconnection structure is disposed on the panel-shaped component and the chip. The interconnection structure has an inner circuit and a plurality of contact pads. The contact pads are disposed on a contact surface of the interconnection structure. At lease one chip pad is connected electrically to at least one contact pad by the inner circuit. The conductive channel extends from the active surface of the chip to a side surface thereof adjacent to the active surface. One end of the conductive channel is electrically connected to at least one chip pad and the other end thereof is electrically connected to the panel-shaped component.

Abstract: A power semiconductor device has a power field effect transistors connected in a bridge circuit (16), parallel circuit or series circuit (18), the power semiconductor device (30) having a base power semiconductor chip (1) with large-area external contacts (S1, D1) on the top side (31) and rear side (32) and carrying at least one stacked power semiconductor chip (2). The stacked power semiconductor chip (2) is surface-mounted with at least one large-area external electrode (D2) on a correspondingly large-area external electrode (S1) of the top side (31) of the base power semiconductor chip (1). At least one metallic structured spacer (33) is arranged between the surface-mounted external electrodes (S1, D2) of the base power semiconductor chip (1) and the stacked power semiconductor chip (2). The structure of the spacer (33) has at least one cutout (34) for a non-surface-mountable connecting element (35) of the base power semiconductor chip (1).

Abstract: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

Abstract: The invention discloses a flexible substrate including a flexible insulating film and a plurality of leads formed on an upper surface of the flexible insulating film. Each of the leads includes a first portion, a second portion, and a connection portion connecting the first portion and the second portion. The connection portion of at least one of the leads is designed as being crooked to provide a deformability to resist a tensile force once suffered by said one lead.

Abstract: A power system for cooling backup computer storage facilities having eight independent levels of redundancy for the power supply to allow the storage facility to survive even extreme and debilitating events and having redundant communications. If power from the existing gas or electric grid is lost, a series of back-up energy sources provide energy to run the micro-turbines and generate the power to run the servers and the HVAC system that cools the servers. In the event that the existing power grid is interrupted, the redundant power supplies are automatically engaged without disruption of the load. If the existing gas and/or electric power grids are disrupted, the storage facility is powered/cooled by a micro-grid having its own independent redundant sources of power.

Abstract: An apparatus and method for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff therebetween. Wire bonds may then be formed between bond pads on the semiconductor die to conductive pads or terminals on the carrier substrate. With this arrangement, a dielectric filler material is disposed in the gap or standoff to form a permanent bonding agent between the semiconductor die and the carrier substrate. By applying the dielectric filler material after forming the wire bonds, the dielectric filler material coats at least a portion of the wire bonds to stabilize the wire bonds and prevent wire sweep in an encapsulation process, such as transfer molding, performed thereafter.

Abstract: A substrate support comprises top, middle and bottom plates which are brazed together. The top plate has a top surface with a plurality of outwardly projecting mesas dispersed across a recessed pocket, a network of recessed grooves, a vacuum port terminating in the recessed grooves, and plurality of gas ports. The middle plate has a plurality of middle feedthroughs aligned to corresponding top feedthroughs of the top plate, and the bottom plate has a plurality of bottom feedthroughs aligned to the middle feedthroughs of the middle plate. The top and middle plates are joined by a first brazed bond layer and the middle and bottom plates are joined by a second brazed bond layer.

Abstract: The invention relates to a heat-conducting coating of electronic circuit assemblies (102), comprising a coating agent (100), which encloses the electronic circuit assembly (102) and which is electrically insulating, with dispersed particles in the coating agent (100) which have a high thermal conductivity, whereby the particles dispersed in the coating agent (100) are embodied as nanoelements (101).

Abstract: Methods, systems, and apparatuses for attaching heat sinks to integrated circuit packages using thermally conductive adhesive materials are described. The adhesive materials can be shaped to conform to surfaces of the integrated circuit package and/or heat sink, prior to hardening, such as by curing the adhesive material.

Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.

Abstract: A thermally-enhanced cavity down ball grid array (CDBGA) package is provided. In one embodiment, the CDBGA package comprises a heat dissipating substrate having a heat spreader and a chip carrier, the chip carrier having a cavity therethrough to allow a chip to be attached to the heat spreader. A chip having an active surface and a corresponding back surface, has the back surface of the chip mounted on the heat spreader. A dummy chip is attached to the active surface of the chip. The dummy chip has a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the chip. An encapsulant encapsulates the chip and portions of the dummy chip. Dummy chip 90 has a coefficient of thermal expansion (CTE) approximately equal to the coefficient of thermal expansion of the chip 40.

Abstract: The electronic device comprises a semiconductor device (10), particularly an integrated circuit, and a carrier substrate (20) with conductive layers on the first side (21) and the second side (22), and voltage supply (62) and ground connections (61) mutually arranged according to a chessboard pattern. These connections (61,62) extend in a direct path through vertical interconnects and bumps (41,42) to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections (62) form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: An integrated circuit package comprising: an substrate having a first main surface and a second main surface which are opposite to each other; a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and a second plurality of external terminals disposed on the second main surface of said interconnection substrate; wherein said second plurality of external terminals comprises a predefined selection of shared external terminals defining a first interface for an integrated circuit memory package having type NAND or type NOR memory.

Abstract: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The ball-pads of one array, for example, are electrically coupled to the bond-pads of the corresponding die. The microelectronic workpiece of this embodiment further includes a protective film over the dielectric layer.

Abstract: An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.

Abstract: Provided are a semiconductor device including a diffusion barrier and a method for manufacturing the same. In the method, an interlayer insulating layer on a semiconductor substrate is formed. The interlayer insulating layer is selectively removed, so that a via hole is formed therein. A first diffusion barrier is formed on sidewalls and a bottom of the via hole using PEALD. A copper layer is formed above the first diffusion barrier, and CMP is performed on the copper layer until the interlayer insulating layer is exposed to form a copper line.

Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Abstract: A multifunctional material having a carbon-doped titanium oxide layer, which has carbon doped in the state of Ti—C bonds, is excellent in durability (high hardness, scratch resistance, wear resistance, chemical resistance, heat resistance) and functions as a visible light responding photocatalyst, is provided. The multifunctional material of the present invention is obtained, for example, by heat-treating the surface of a substrate, which has at least a surface layer comprising titanium, a titanium alloy, a titanium alloy oxide, or titanium oxide, in a combustion gas atmosphere of a gas consisting essentially of a hydrocarbon such that the surface temperature of the substrate is 900 to 1,500° C.; or by directly striking a combustion flame of a gas consisting essentially of a hydrocarbon, against the surface of the substrate for heat treatment such that the surface temperature of the substrate is 900 to 1,500° C.

Abstract: A switching device provided on a package substrate for altering the built-in function of an IC chip includes a first contact, a second contact, and a conductive layer. The first contact is electrically connected to a signal-receiving end of the package substrate, and the second contact is electrically connected to a voltage source of the package substrate. The conductive layer is used for electrically connecting the first contact with the second contact.

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

Abstract: To provide a semiconductor device configured that a micro device having a device substrate, a function element provided on the device substrate and having an oscillator or a movable part, first lands provided on a surface of the device substrate by being arranged on its outer circumference portion of the function element, and bumps provided to the first lands is mounted on the circuit board having second lands formed to correspond to the bumps, from the bump formation surface side, so that the bumps and the second lands are electrically connected; on which a sealing resin layer is formed to go round the outer circumference portion of the function element to fix connection portions of the bumps and the second lands, and to seal a clearance between the device substrate and the circuit board; and a cavity portion is formed between the function element and the circuit board.

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance.