Abstract: The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate and a source of the booster transistor, and boosts gate voltage with respect to the source of the booster transistor, wherein gate dimensions of the selection transistor are smaller than gate dimensions of the booster transistor. According to this configuration, the semiconductor device can realize increasing an action of a circuit, decreasing a chip size and simplifying processes.

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.

Abstract: A computer program product for verifying an asynchronous circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps of (a) and (b). The step (a) includes the step of carrying out a function simulation of an asynchronous circuit based on circuit information of the asynchronous circuit including a sequential circuit stored in a storage device. The step (b) includes the step of monitoring an output value from an output node of the sequential circuit every unit time, and setting the output value in n time as a value of a metastable state, when the output vale in the n time is changed from the output value in (n?1) time.

Abstract: The disclosure relates to a hysteresis comparator of a first input voltage and a second input voltage. The comparator includes a first differential stage whose first and second inputs are respectively powered by the said first and second input voltages, and at least one second differential stage symmetrical to the said first differential stage. Two inputs of the said second differential stage are respectively powered by first and second reference voltages. At least one first current, dependent on the difference between the first and second input voltages, is compared with at least one second current dependent on the difference between the second and first reference voltages.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A signal generating circuit that enables to set an initial oscillation signal level to zero is provided. The circuit includes an adder 11, a first multiplier 12 with an multiplication coefficient of A1, a second multiplier 13 with an multiplication coefficient of A2, a first and second delay element 14, 15 and an initializing circuit 16. Output signal from an output terminal of the circuit is supplied to the first delay element 14, the output of it is supplied to the second delay element and the first multiplier 12. The output signal of the second delay element 15 is supplied to the second multiplier 13, the output signal of the first and second multiplier are supplied to the adder 11. The output of it is supplied to the output terminal. The initializing circuit outputs an initial value y1 and y2 of the first and second delay element such that it satisfies an equation y1*A1+y2*A2=0.

Abstract: A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that is configured to receive input signals and generate output signals. In one embodiment, the differential buffer of the memory device includes adjustment circuitry coupled to the differential pair to enable adjustment of the amount of current dissipated by the differential buffer. Other memory devices, differential buffers, and methods are also disclosed.

Abstract: A source-follower-type analogue buffer with an active load, a new compensating operation and a display with the source-follower-type analogue buffers are developed to reduce an error voltage which is the difference between an input voltage and an output voltage of the analogue buffer. The source-follower type analogue buffer can also minimize the variation from both the charging time and the device characteristics and maximize the range of the input voltage.

Abstract: To provide a circuit that has a high multiplication ratio and low jitter and that operates stably. A multiplication circuit 10 comprises a selector circuit 15 for selecting an input clock signal CLK or a clock signal obtained by multiplying the input clock signal CLK by m and outputting it.

Abstract: The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz.

Abstract: A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.

Abstract: A delay circuit includes a constant current source, a delay stage, and a compensating circuit. The delay circuit may compensate for a variation in a delay characteristic of the delay stage due to a variation in temperature, supply voltage and/or process.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the low voltage being equal to the lower voltage and the higher voltage being greater than the high voltage, including an inverter circuit receiving the first signal and being connected to a higher voltage source through first diodes and being directly connected to the lower voltage, each of the first diodes having a threshold voltage; a conversion and storage element formed of first and second inverters head-to-tail supplied between said higher and lower voltages, the first inverter receiving the output of the inverter circuit and providing the second signal; wherein the number of said first diodes is such that the difference between the higher voltage and the high voltage is smaller than or equal to the sum of the threshold voltages of said first diodes.

Abstract: A squaring cell comprises a first circuit responsive to an input voltage to produce a corresponding current, and a second circuit, preferably in the form of an absolute modulator circuit, responsive to the current produced by the first circuit and to the input voltage to produce an output current that corresponds to the square of the input voltage. In one embodiment, the first circuit comprises an absolute value voltage-to-current converter; in another, the first circuit comprises a linear voltage-to-current converter. Techniques to improve accurate square law performance of the cell, independent of temperature, and of broad input voltage range and frequency, are presented.

Abstract: A semiconductor integrated circuit device includes: a boost circuit configured to boost power supply voltage so as to generate a boosted voltage; a voltage detecting circuit configured to detect the boosted voltage of the boost circuit and control ON/OFF of the boost circuit for keeping the boosted voltage at a certain level; and a gate circuit configured to set the voltage detecting circuit to be in such an inactive state that current passage thereof is shut off, thereby stopping the operation of the boost circuit while a load is separated from an output node of the boost circuit.

Abstract: A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.

Abstract: A voltage converting circuit is able to convert an input voltage generated by a system to a voltage capable of being utilized by a chip, avoids the defects of conventional switching regulators and linear regulators, and achieves voltage regulation with extremely high power efficiency and without off-chip components. The voltage converting circuit is adapted in systems with a plurality of similar or identical circuits.

Abstract: A circuit for reference current and voltage generation is provided. The circuit comprises a current bias circuit and a voltage reference circuit. Wherein, the current bias circuit receives an enable signal, provides a reference current, a bias signal and a startup signal when the enable signal is in an enabling state, and provides a first predetermined voltage and a second predetermined voltage when the enable signal is in a disabling state. The voltage reference circuit is electrically coupled to the current bias circuit. In addition, the voltage reference circuit enters into a turned-on state and provides a reference voltage after receiving the bias signal and the enable signal, and enters into a turned-off state after receiving the first and the second predetermined voltages.

Abstract: In some embodiments, regulator circuits are provided.

Abstract: The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential outp

Abstract: The present invention provides methods and apparatuses for a shared filter transceiving system. A shared filter transceiving system having a capacitor bank to adjust the time constant of the shared filter comprises a first input configured to receive a first signal. The capacitor bank is coupled to the first input having a plurality of selectable capacitors including a reference capacitor. A second input is coupled to the capacitor bank configured to receive a second signal. A configurable switch is coupled to the capacitor bank configured to couple a first selectable capacitor with the reference capacitor when the first input is active and couple a second selectable capacitor with the second reference capacitor when the second input is active. The second selectable capacitor is a predetermined offset value of the first selectable capacitor.

Abstract: A circuit for amplitude modulating a carrier signal includes a carrier signal input, circuitry for splitting the carrier signal into first and second paths, circuitry for phase modulating the carrier signal on the first path, circuitry for phase modulating the carrier signal on the second path, and circuitry for combining the phase modulated carrier signal on the first path with the phase modulated carrier signal on the second path for generating an amplitude modulated output signal. Feedback loops virtually eliminate residual phase shift and make the amplitude modulated output signal linearly proportional to the baseband signal.

Abstract: A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

Abstract: A feedback controller in a PWM amplifier comprises a signal input for receiving a pulse width modulated (PWM) input signal (Vin) whose duty cycle represents a desired analogue output signal. A feedback loop filter 518 generates a filtered error signal (Vint) comprising a filtered representation of differences between the input signal (Vin) and a feedback signal (Vfb). A comparator (520) compares the filtered error signal with a reference to generate a provisional PWM switching control signal (C) for controlling the PWM amplifier (500). A pulse conditioner (532) receives both the provisional PWM switching control signal (C) and the PWM input signal (X=Vin) and outputs to the amplifier (500) a conditioned PWM switching control signal (Y), modified in accordance with predetermined constraints in relation to the PWM input signal.

Abstract: Embodiments related to low noise amplification of electrical signals are presented herein.

Abstract: An automatic gain controller includes a variable gain amplifier for amplifying an input signal having a specified DC level on the basis of the DC level, and outputting a first differential signal having a specified gain ?, a second differential signal having a 180° phase difference from the first differential signal, and an output signal obtained by subtracting the second differential signal from the first differential signal; a full-wave-rectifying unit for full-wave-rectifying the first differential signal and the second differential signal; a low-pass filter for extracting the DC component from the output signal of the full-wave-rectifying unit and outputting the extracted DC component; a reference voltage level adjustment unit for adjusting a DC level of a reference voltage; and a comparison unit for comparing the output signal of the low-pass filter with the output signal of the reference voltage level adjustment unit to adjust a gain of the variable gain amplifier.

Abstract: A protection circuit of a digital amplifier includes a DC voltage detection circuit for detecting a DC voltage occurring in a loudspeaker output terminal; a control circuit for performing protection operation when the DC voltage detection circuit outputs a detection signal; and a midpoint potential detection circuit for detecting midpoint potential shift between a positive power supply voltage and a negative power supply voltage. Output of the midpoint potential detection circuit is connected to input of the DC voltage detection circuit and when the midpoint potential shift is detected, the DC voltage detection circuit outputs a detection signal.

Abstract: The push-pull amplifier with transformational negative feedback is provided for amplification of variable electrical signals. It includes a signal input and a signal output, a transformational negative feedback connected with the signal input and the signal output and an amplifier circuit. The amplifier circuit includes an input and an output as well as a first transistor and a second transistor. The input of the amplifier circuit is thereby connected with the signal input and the output of the amplifier circuit is thereby connected with the signal output via the transformational negative feedback.

Abstract: A biasing circuit is described for a radio frequency (RF) amplifier that provides a stable signal source. The described bias circuit has two or more transistors coupled in at least one feedback loop, with a buffering transistor providing the output biasing signal and buffering the feedback loops from the output of the of the biasing circuit. This arrangement provides thermal compensation, reduces fluctuations in the feedback loops that stabilize the biasing circuit, and allows for higher biasing current demand.

Abstract: A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is coupled to a charge pump. Furthermore, the phase locked loop includes an oscillator whose input side is coupled to the charge pump and which is coupled at one output for emission of an oscillator signal to a first input of the phase detector. The circuit arrangement further includes a counter whose input side is supplied with an input signal which can be derived from the phase signal, and which is coupled to the output of the oscillator. The counter emits an output signal from the counter as a function of a value which represents a pulse length of the phase signal.

Abstract: A direct digital synthesizer (DDS) has reduced spurious signals and includes a DDS core that produces a digital representation of a signal to be synthesized. A plurality of DDS circuits are operatively connected to the DDS core, each having a digital-to-analog converter connected to the DDS core for receiving the digital representation and converting it into a signal. A modulator is operatively connected to an oscillator circuit and digital-to-analog converter for receiving signals from the digital-to-analog converter and producing a modulated output signal. The individual frequencies of the respective DDS circuits are randomly and continuously changed from each other. A mixer receives and mixes the modulated output signals from the plurality of DDS circuits to create a mixed output signal at a selected and fixed frequency.

Abstract: An oscillator and a radar apparatus that includes a resonator electro-magnetically connected to a micro strip line and a rotor connected to the resonator by capacitance. The bottom surface of the rotor has a changing height in the circumferential direction of the rotor. As the rotor is rotated, an actual oscillation frequency is recognized from the rotating angle of the rotor when an output of a detector has a peak. A modulation voltage supplied to a VCO is corrected in accordance with the result.

Abstract: A method and apparatus for a fast and automatic setting of the phase locked loop (PLL) output frequency that significantly improves linearity, locking range as well as spectrum purity, jitter and phase noise performances is disclosed. In one embodiment, a PLL frequency synthesizer is disclosed having a reconfigurable voltage controlled oscillator VCO with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During a first tuning operation, the VCO work in a linear high gain mode, enabling a totally analogue self-calibration of the PLL over a wide frequency tuning range and with a fast settling time. During this operation the control voltage at the input of the VCO is varied by the PLL until the appropriate output frequency is found. A method for providing a linear variation of the frequency over all the voltage tuning range during this mode is disclosed. When the loop is locked, the VCO is automatically switched to the Zero-gain mode while keeping its frequency unchanged.

Abstract: A system and method for modulating a phase component of an electromagnetic signal includes a phase/frequency detector having first and second inputs and an output. The first phase/frequency detector input may be configured to receive a reference signal. The system may include an oscillator having an input and an output. The oscillator may be configured to generate a desired oscillator output signal at its output. A divider may be configured to receive the oscillator output signal. The divider may have a divider count input and a divider carryout output that may be connected to the second phase/frequency detector input. A loop filter may be connected in series between the phase/frequency detector output and the oscillator input. The loop filter has a transfer function including at least two frequency response rate change points, where each of the frequency rate change points corresponds to a pole or a zero in the transfer function.

Abstract: A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.

Abstract: A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input.

Abstract: A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.

Abstract: A differential amplifier circuit for use in a ring oscillator includes first and second MOS transistors to each source of which an operating power source voltage is applied, and which individually respond to first and second input signals with mutually contrary phases applied to gates thereof; cross-coupled first and second-stage transistors of which each drain-source channel is connected between each drain of the first and second MOS transistors and a ground voltage level; a first variable resistance, which is connected between a drain of the first MOS transistor cross-connected to a second gate of the cross-coupled second-stage transistors, and a first gate of the cross-coupled first-stage transistors, and which is controlled by the operating power source voltage applied to a gate thereof; and a second variable resistance, which is connected between a drain of the second MOS transistor cross-connected to a second gate of the cross-coupled first-stage transistors, and a first gate of the cross-coupled second

Abstract: Conductor segments are positioned within a transmission line structure in order to generate microwave pulses. The conductor segments are switchably coupled to one or the other of the transmission lines or to each other, in parallel with the transmission line structure. Microwave pulses will be induced in the transmission line by closing the switches in a controlled manner to discharge successive segments or successive groups of segments into the transmission lines. The induced waves travel uninterrupted along the transmission lines in a desired direction.

Abstract: An apparatus for oscillating a surface is described. The apparatus comprises an oscillator circuit having: a) a piezoelectric crystal connected to the surface; b) a variable frequency generator for generating a driving signal which is supplied to the crystal to cause the crystal to oscillate, thereby causing the surface to oscillate; and, c) an analyser for monitoring the phase shift between the voltage across the crystal and the current flowing through it and, in response generating an adjustment signal which relates to the difference between the oscillation frequency and a resonant frequency of the crystal, the variable frequency generator being responsive to the adjustment signal to vary the frequency of the driving signal to cause the crystal to oscillate at the resonant frequency.

Abstract: A frequency fine tuning circuit for use in a voltage-controlled oscillator is provided. The frequency tuning circuit includes a first varactor, a second varactor and a center bias unit. The second varactor is coupled to the first varactor at a first node. The center bias unit maintains a node voltage of the first node at a constant bias voltage level.

Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure. The cable can be coupled to destination components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract: A transmission line pair has two transmission lines placed adjacent to each other in parallel to a signal transmission direction of the transmission lines as a whole. Each of the transmission lines includes a first signal conductor which is placed on one surface of a substrate formed from a dielectric or semiconductor and which is formed so as to be curved toward a first rotational direction within the surface, and a second signal conductor which is formed so as to be curved toward a second rotational direction opposite to the first rotational direction and which is placed in the surface so as to be electrically connected in series to the first signal conductor. A transmission-direction reversal portion in which a signal is transmitted along a direction reversed with respect to the signal transmission direction of the transmission lines as a whole is formed so as to include at least part of the first signal conductor and part of the second signal conductor.

Abstract: In a transmission line pair including a first transmission line and a second transmission line which is so placed in adjacency that a coupled line region to be coupled with the first transmission line is formed, in the coupled line region, the first transmission line includes a first signal conductor which is placed on one surface which is either a top face of a substrate formed from a dielectric or semiconductor or an inner-layer surface parallel to the top face and which has a linear shape along its transmission direction, and the second transmission line includes a second signal conductor which is placed on the one surface of the substrate and which partly includes a transmission-direction reversal region for transmitting a signal along a direction having an angle of more than 90 degrees with respect to the transmission direction within the plane of the placement, and which has a line length different from that of the first signal conductor.

Abstract: In order to realize with a low loss a hybrid structure in which an NRD guide is used for a transmission part and a microstrip line is used for a circuit element loading part, the present device includes: a dielectric waveguide (1) which is sandwiched between parallel conductor plates and has a gap which is less than a ½ wavelength; a microstrip line (4) which is provided on a side surface of a metal rod (3) opposite to the dielectric waveguide (1), the metal rod (3) being adjacently arranged in parallel with the dielectric waveguide (1); and a coaxial line (5) which pierces the metal rod (3) and connects the dielectric waveguide (1) with the microstrip line (4).

Abstract: In an electronic circuit unit for transmitting power through a transmission line 103 formed of a conductor pattern, a matching circuit 101 is connected to an output end of a power amplifier 102. The matching circuit 101 comprises a first conductor pattern 14 having bend portions P1 to P4 provided on a first dielectric substrate 11 of a laminated substrate 10 which has a plurality of dielectric layers 11 to 13, and a second conductor pattern 15 disposed opposite the first conductor pattern 14 on an adjacent second dielectric layer 12, and connecting conductors 16 to 20 provided at at least bend portions P1 to P4 of the first and second conductor patterns.

Abstract: An apparatus and method for providing an electrically adjustable RF delay in which a splitter splits an input signal into two signal paths, one signal path providing a delay fixed at an integral number of wavelengths of a desired center frequency and both signal paths providing electrically adjustable attenuation. A combiner combines the signals passing through the signal paths, such that the sum of the electrically-adjustable attenuation provided by the signal paths adds to unity, whereby the input signal is delayed by an adjustable time depending upon the attenuations provided by the signal paths.

Abstract: A cancellation circuit to remove the anti-resonance signal from a resonator. Micro-mechanical and surface and bulk acoustic wave resonators include an anti-resonance in an output signal. This has an undesirable effect on certain types of systems in their function and performance. An anti-resonance cancellation circuit removes the anti-resonance from the output of the resonators by providing a signal which is subtracted from the output of the resonator. The cancellation circuit includes a capacitor which is matched to the static capacitance of the resonator. The loads of the resonator and cancellation network are also matched.