Abstract: To provide a method for the self-testing of a reference voltage in electronic components, by means of which method there is defined a circuit arrangement for a self-test of the reference voltage that can be implemented in the form of an on-chip test, i.e. for which no external reference-voltage source is required, provision is made for the reference voltage (Uref) to be the variable of a function f(Uref) that has an extreme at the point where the selected nominal value (Uref.

Abstract: The invention provides a method of detecting partial discharges in an electrical appliance insulated in a receptacle and a system of diagnosing the state of the appliance using this method. With the help of an UHF antenna placed in the receptacle of the appliance, the method includes analyzing the spectrum (RS1) of the electromagnetic signal picked up by the antenna and of identifying within the spectrum one or more frequencies of interest (B1, B2), for each of which the signal has an amplitude greater than a predetermined threshold value. To identify the frequency/frequencies of interest, the spectrum of the signal received by the antenna is compared with a reference spectrum (RS2).

Abstract: Disclosed are systems and methods for determining when a heat sink is installed. In one embodiment, a system comprises an electrically-conductive heat sink retainer clip that is adapted to maintain contact between a heat sink and a heat-producing component, the retainer clip further being adapted to electrically connect to ground, and a heat sink detection circuit adapted to provide voltage to the retainer clip, the heat sink detection circuit being configured to provide a logic value that indicates one of presence or absence of a heat sink.

Abstract: A partial discharge sensing system and method for conducting testing inside an enclosure includes a partial discharge sensor, an access port, and a signal cable. The partial discharge sensor is permanently installed at a test location inside the enclosure. The access port is configured so that an analyzer can be connected to the access port from an exterior of the enclosure. The signal cable operably connects the partial discharge sensor and the access port to enable an analyzer connected to the access port from outside the enclosure to interface with the partial discharge sensor for generating test data.

Abstract: The invention relates to a capacitive sensor system for measuring environmental parameters by activating a capacitive array and causing fringe electric fields to intersect the surrounding environment. An oscillator is coupled to the capacitive array and the frequency of oscillation depends upon the capacitance of the array, which represents an environmental parameter. The sensor is suitable for measuring resistivity and dielectric constant parameters in geophysical, environmental, hydro-geological and related applications. The conductors of the capacitive array can be arranged around a perimeter for use, for example, in a borehole or the conductors can be arranged in the same plane for use, for example, beneath a raft in shallow water. In the situation where the boreholes are fluid-filled, there are economic and technical advantages in using the metal plugs (normally used to seal the probe housings at each end), as the capacitive array in galvanic contact with the fluid.

Abstract: An apparatus for measuring fluid resistivity includes a flow line adapted to be in fluid communication with formation fluids, wherein the flow line includes a first section comprising a first conductive area, a second section comprising a second conductive area, and an insulating section disposed between the first section and the second section to prevent direct electrical communication between the first section and the second section; a first toroid and a second toroid surrounding the flow line around the first section and the second section, respectively, wherein the first toroid is configured to induce an electrical current in a fluid in the flow line and the second toroid is configured to measure the electrical current induced in the fluid in the flow line; and an electronic package to control functions of the first toroid and the second toroid.

Abstract: A device for measuring one or more different properties of soil or a soil-related substance is provided. The device includes a probe that is inserted into the soil or soil-related substance. The probe includes a tip. The tip is electrically insulative and defines apertures. Electrodes are fitted into the apertures. The tip and electrodes are machined together to have a desired shape that is suitable for insertion into a sample. A printed circuit board (“PCB”) is located inside the probe. The electrodes are soldered directly to the PCB in one embodiment. A temperature sensing element is also located in the tip, near the electrodes, and is connected electrically to the PCB.

Abstract: An apparatus for measuring alignment of polysilicon shapes to a silicon area. Each polysilicon shape in a first plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. Each polysilicon shape in a second plurality of polysilicon shapes has a bridging vertex positioned near the silicon area. The second plurality of silicon shapes is positioned on the opposite side of the silicon area from the first plurality of silicon shapes. An electrical measurement of how many of the polysilicon shapes in the first plurality of polysilicon shapes and in the second plurality of polysilicon shapes provides a measurement of alignment of the polysilicon shapes and the silicon area.

Abstract: An isolation resistor is incorporated into the plunger of a probe tip spring pin by, for example, doping a ceramic that is used to form the plunger, or forming the plunger of first and second electrically coupled materials, at least a first of which has a resistivity sufficient to serve as an isolation resistor. Alternately, an isolation resistor is embedded in a printed circuit board trace that is used to couple either an upper or lower blind plated hole to a via. A probe tip spring pin is then inserted into the upper blind plated hole.

Abstract: A stage for placing a target object thereon includes, on a side surface of a stage main body having an upper surface, a lower surface, and the side surface, a side surface protection cover layer. The side surface protection cover layer isolates at least part of the side surface of the stage main body from an ambient atmosphere of the stage main body. The stage main body further includes an upper electrode on its upper surface and a lower electrode on its lower surface. At least the surface of the side surface protection cover layer is conductive. The stage can further include a potential control mechanism and a guard potential setting mechanism.

Abstract: A control unit of a wafer prober for implementing wafer examination, using a probe card including a multiple number of probes, executes a multiple number of measuring operations by bringing the probes of the probe card into contact with bonding pads formed on a wafer and by measuring the electric characteristics between predetermined pads of the bonding pads, each of the measuring operations being implemented after varying the relative position between the probe card and the wafer, in directions parallel to the face of the wafer. The control unit, upon execution of each of the measuring operations, implements the measuring operation after adjusting the relative position between the probe card and the wafer so that the contact position of each probe of the probes against each pad of the bonding pads is separated from all the positions at which the probes have already touched that pad of the bonding pads for a predetermined number of different times.

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract: A system for testing with an automated test equipment (ATE). The ATE includes a tester, an interface board connected to the tester, a first socket and a second socket of the interface board, a first manipulator arm connected to the tester, and a second manipulator arm connected to the tester. The first socket and the second socket are parallel-wired to the tester. The ATE also includes a switch connected to the tester and the interface board. The switch selectively effects communicative connection of the tester to either of the first socket or the second socket at each instant. During testing via one of the sockets, one of the manipulator arms moves post-test devices and replaces next devices for testing in the other of the sockets. After testing via one of the sockets is completed, the switch immediately connects the other socket and testing of next devices commences and continues for those devices.

Abstract: A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection structures. The method includes disconnecting a first one of the connection structures from the plane, and connecting the first connection structure to an external package connection, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

Abstract: A device for measuring resistances associated with electrical contacts of a contact ring used in a semiconductor wafer electroplating process. The device includes a substrate and a conductive pattern on the substrate. The conductive pattern is electrically contactable with the electrical contacts of the contact ring. Resistance measurement circuitry is connected to the conductive pattern. The resistance measurement circuitry is configured to send test signals to the conductive pattern, receive signals from the conductive pattern, and measure the resistances associated with the electrical contacts of the contact ring. A method of using such a device to measure resistances associated with electrical contacts of a contact ring used in a semiconductor wafer electroplating process is also provided.

Abstract: The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.

Abstract: A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically.

Abstract: Systems are provided for reducing electromagnetic emissions from a controller area network transceiver. A driver circuit is operative to transmit communications across an associated bus. A static driver replica circuit approximates a common-mode voltage associated with a dominant state associated with the bus. A receiver attenuator bias circuit forces a common-mode voltage associated with the driver circuit to be equal to the approximated dominant state common-mode voltage during a recessive state associated with the bus.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.

Abstract: A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30?). This provides for a reduction in memory area of the reconfigurable processing unit (1).

Abstract: Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

Abstract: Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.

Abstract: A programmable logic device may comprise a metric circuit operable to repeatedly perform a function and emit a first signal dependent upon its advancement into the function. A comparator may compare the first signal from the metric circuit to a predetermined reference signal. A controller may then selectively disable a portion of the programmable logic device dependent upon the results of the comparison. In a particular case, the weakened circuit may be a counter that repeatedly advances its count with a rate dependent upon an aging characteristic of a vulnerable element.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to a first load path. The load path couples to a latch ring, which receives configuration data from the first memory. An array of configuration latches receives the configuration from the latch ring and effects a configuration of the programmable device. A write-back path couples the latch ring and first configuration memory. A write-back controller manages write-back operations of configuration data from the latch ring to the configuration memory. A second configuration controller is coupled to a second configuration memory, which is coupled to a second load path. The second controller and second memory operate like the first. The write-back controller can be configured to couple to the second memory and facilitate development processes by a writing-back developmental configurations.

Abstract: The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

Abstract: Disclosed is an input device for a semiconductor device that optimizes the performance characteristic of the semiconductor device using off-chip driver information. The input device includes at least two buffers, connected in parallel to an electrostatic discharge (ESD) circuit, for buffering an input signal applied through the ESD circuit. The buffers have delay times different from each other, one of the buffers is selected using off-chip driver information detected from an output driver and the input signal is transferred through the selected buffer. The signal transfer path of the input device is optionally be selected using the off-chip driver information of the output drivers, and a stable input/output operation of the semiconductor device is achieved even if the performance characteristic of the semiconductor device is changed due to the skew occurring in the fabricating process of the semiconductor device.

Abstract: To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a result of line capacitances of a transmission line, because of the current limited according to the standard the edge steepness and hence the maximum transmittable bit rate can deteriorate. According to the invention, therefore, at least essentially in synchronization with a triggering of the driver stage, at least one current increase signal is generated which via a capacitor causes an additional current increase in the output current of the driver stage. Preferably, the current increase signal via the respective capacitor is switched directly to an output of the driver stage. By using a capacitor, with very little expenditure a limited current pulse can be switched in a temporally targeted manner on the switching processes of the driver stage.

Abstract: Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

Abstract: Since voltages of two input terminals of an output unit having an online download function are decided by voltages which are not correlative to each other, a value of an incoming current on the start-up becomes large. The present invention solves the problem of turning-on of a parasitic transistor due to a transitional minus potential even when the voltage of the output unit on a stationary state is set to 0 V in order to reduce the incoming current. In this invention, a switch is turned on and off by a download switching digital signal, and an input from a delay circuit for charging and discharging a condenser in the delay circuit whose one end is connected to a reference potential is input to one of the input terminals of the output terminal while the reference potential is applied to the other input terminal of the output unit. Thus, an input error in the output unit is reduced to prevent an excessive incoming current.

Abstract: Embodiments of the present invention provide a method, apparatus and system for domino multiplexing including sustaining a first domino block output in a preconditioning state using a second domino block output.

Abstract: A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control signal and the power input terminal. That switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level. This results in the logic cell operating in standby mode. A latch circuit is coupled between the power voltage and the output terminal to preserve the voltage level of the output terminal when the logic cell operates in standby mode.

Abstract: A current mode transmitter includes a first sink current path, through which a current flows from an output port according to a first bias voltage, a charge error canceller, which supplies a current from a high power supply voltage to a current control port in response to an input signal and counteracts a variation of a second bias voltage in response to an inverted input signal, which has an opposite polarity to that of the input signal, and the second bias voltage, and a second sink current path, which sinks current supplied from the output port in response to the second bias voltage and the inverted input signal, the second sink current path being controlled by the current control port. The input signal and the inverted input signal are complementary.

Abstract: A circuit for detecting phase includes a first inverter, a second inverter, a differential amplifier, an output load latch and an output latch. The first and second inverters receive an input signal and an inverted input signal to generate first and second differential input signals in response to a clock signal and first and second control signals, respectively, and shut off transmissions of the input signal and the inverted input signal. The differential amplifier differentially amplifies the first and second differential input signals in response to the clock signal to provide first and second differential output signals as the first and second control signals. The output load latch latches the first and second differential output signals to generate the first and second latch output signals. The output latch latches the first and second latch output signals to output a phase detection signal.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Abstract: A sampling switch is the one for sampling an input voltage and providing an output voltage, comprising a MOS transistor for being supplied by the input voltage to the source terminal thereof and providing the output voltage from the drain terminal thereof; and a gate voltage control unit for supplying a voltage to the gate terminal of the MOS transistor with a delayed time from the input voltage. This enables a change in the on-resistance of a MOS transistor used for a sampling switch to be suppressed to a minimum, thereby reducing a distortion of signals induced by a change in the on-resistance.

Abstract: A drive apparatus that guarantees the stable operation of a CCD image sensor. The drive apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The power supply circuit includes an over-boosting circuit for temporarily over-boosting the voltage supplied to the drive circuit to generate an over-boosted voltage, prior to the charge transfer operation of the CCD image sensor.

Abstract: A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a first path, and a second electronic switching means (T2) in a second path, which is in parallel with it. The circuit also has a means (INV, OR, T5) for producing the electrical control variable (Ugate2) for the second switching means (T2), which determines the control variable (Ugate2) as a function of an electrical variable (U0,d) which occurs on the output side of the first switching means (T1) when switching on a load which can be connected downstream.

Abstract: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

Abstract: A triangular wave generating circuit adapted to a class-D amplifier is designed not to use a PLL circuit and to secure robustness regarding an amplification gain irrespective of variations of voltages, thus producing a high-quality triangular wave with a simple circuit constitution. First and second constant currents, which are generated in proportion to positive and negative voltages, are alternately and periodically selected using high impedance elements without causing noise. A first integrator produces a triangular wave in response to charged electricity realized by the first and second constant currents, wherein the triangular wave is supplied to a second integrator performing servo-amplification operation so as to suppress phase shifts thereof. Hence, it is possible to maintain a constant gain for the class-D amplifier irrespective of variations of voltages since the maximal and minimal voltages values of the triangular wave are made proportional to the positive and negative voltages.

Abstract: A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.

Abstract: An apparatus and a method of controlling clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of phase intervals therebetween. A predetermined phase angle is divided by the number of the output signals to generate one of the phase intervals. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signal and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signal.

Abstract: A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e.g., less than about 1.2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e.g., PLL and DLL devices) within which the charge pump may be utilized.