Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.

Abstract: A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: A light emitting diode capable of emitting first light having a first peak wavelength is combined with a first phosphor layer overlying the light emitting diode, the first phosphor layer capable of absorbing the first light and emitting second light having a second peak wavelength and a second phosphor layer overlying the light emitting diode, the second phosphor layer capable of emitting third light having a third peak wavelength.

Abstract: A semiconductor apparatus includes a substrate made of a diboride single crystal expressed by a chemical formula XB2, in which X includes at least one of Ti, Zr, Nb and Hf, a semiconductor buffer layer formed on a principal surface of the substrate and made of AlyGa1?yN (0<y?1), and a nitride semiconductor layer which is formed on the semiconductor buffer layer and which includes at least one kind or plural kinds selected from among 13 group elements and As.

Abstract: Disclosed are a GaN-based semiconductor light emitting diode and a method for manufacturing the same. The GaN-based semiconductor light emitting diode includes a substrate on which a GaN-based semiconductor material is grown; a lower clad layer formed on the substrate, and made of a first conductive GaN semiconductor material; an active layer formed on a designated portion of the lower clad layer, and made of an undoped GaN semiconductor material; an upper clad layer formed on the active layer, and made of a second conductive GaN semiconductor material; an alloy layer formed on the upper clad layer, and made of an alloy selected from the group consisting of La-based alloys and Ni-based alloys; and an TCO layer formed on the alloy layer. The alloy layer has a high transmittance and forms Ohmic contact, thus reducing a contact resistance.

Abstract: To provide an electro-optical device having a buffer layer which planarizes a gas barrier layer so that stress-concentration in the gas barrier layer is reduced, the buffer layer being prevented from leaking out of a predetermined area, and to provide a method of producing the same and an electronic apparatus. In an electro-optical device 1 having, on a substrate 200, a plurality of first electrodes 23, a bank structure 221 having a plurality of openings 221a positioned correspondingly to the formed first electrodes, electro-optical layers 60 arranged in the respective openings 221a, and a second electrode 50 covering the bank structure 221 and the electro-optical layers 60, the device includes a buffer layer 210 formed so as to cover the second electrode 50 and have a substantially flat upper surface, a frame 215 made of a material having no affinity to the buffer layer 210 and surrounding the periphery of the buffer layer 210, and a gas barrier layer 30 covering the buffer layer 210 and the frame 215.

Abstract: An optical transmission module that can be produced more easily and uses a shorter wiring pattern connecting the driving device and the light-emitting device than the conventional light-emitting apparatus, with the driving device and the light-emitting device arranged close to each other. The light-emitting device and the light-receiving device for monitoring the backward light emitted from the light-emitting device are arranged on a main surface of the substrate. The driving device is disposed on a bottom of a concave formed between the light-emitting device and the light-receiving device so that the driving device is lower than a straight line connecting a backward light emitting point of the light-emitting device and a backward light receiving point of the light-receiving device.

Abstract: In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Abstract: A method for fabricating GaN-based LED is provided. The method first forms a first contact spreading metallic layer on top of the texturing surface of the p-type ohmic contact layer. The method then forms a second and a third contact spreading metallic layers on top of the first contact spreading layer. The p-type transparent metallic conductive layer composed of the three contact spreading metallic layers, after undergoing an alloying process within an oxygenic or nitrogenous environment under a high temperature, would have a superior conductivity. The p-type transparent metallic conductive layer could enhance the lateral contact uniformity between the p-type metallic electrode and the p-type ohmic contact layer, so as to avoid the localized light emission resulted from the uneven distribution of the second contact spreading metallic layer within the third contact spreading metallic layer. The GaN-based LED's working voltage and external quantum efficiency are also significantly improved.

Abstract: A semiconductor element excellent in luminous efficiency which sufficiently eliminates the effect of a piezo-electric field with the crystallinity of an active layer well retained. A quantum well active layer has a laminated structure in which a barrier layer undoped region ((In0.02Ga0.98N layer 702), a quantum well layer (undoped In0.02Ga0.8N layer 703) and a barrier layer n-type region (n-type In0.02Ga0.98N layer 701) are formed in this order. The Si concentration of a barrier layer n-type region is up to 5E18 cm?3.

Abstract: To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100.

Abstract: A nitride semiconductor light emitting element is provided with: a substrate 11 having a pair of main surfaces that face each other; a nitride semiconductor layer of a first conductivity type layered on one of the main surfaces of substrate 11; a nitride semiconductor layer of a second conductivity type layered on the nitride semiconductor layer of the first conductivity type; an active layer 14 formed between the nitride semiconductor layer of the first conductivity type and the nitride semiconductor layer of the second conductivity type; and a reflective layer 16 formed on the nitride semiconductor layer of the second conductivity type for reflecting light from active layer 14 toward the nitride semiconductor layer of the second conductivity type. This nitride semiconductor light emitting element can be mounted on a circuit board, with the other main surface of the above described substrate 11 being used as the main light emitting surface.

Abstract: A mounting substrate for a semiconductor light emitting device includes a solid metal block having a cavity in a face thereof that is configured for mounting a semiconductor light emitting device therein. An insulating coating is provided in the cavity, and first and second spaced apart conductive traces are provided on the insulating coating in the cavity that are configured for connection to a semiconductor light emitting device. The mounting substrate may be fabricated by providing a solid aluminum block including a cavity in a face thereof that is configured for mounting a semiconductor light emitting device therein. The solid aluminum block is oxidized to form an aluminum oxide coating thereon. The first and second spaced apart electrical traces are fabricated on the aluminum oxide coating in the cavity.

Abstract: A light emission device. A lead frame comprises a first lead frame segment and a second lead frame segment. A light source is coupled to the first lead frame segment. A wire bond is coupled to the light source and coupled to the second lead frame segment. A translucent epoxy cast encases the light source, the wire bond and a portion of the lead frame.

Abstract: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a sealing resin 13, a cover layer 12, covering the top surface of optical semiconductor element 14, is exposed from the top surface of sealing resin 13. Thus in comparison to a related-art example with which the entirety is sealed by a transparent resin, sealing resin 13 can be formed thinly and the thickness of the entire device can be made thin. Furthermore, semiconductor device 10 is arranged using a sealing resin having a filler mixed in. A semiconductor device that is excellent in mechanical strength and humidity resistance can thus be arranged.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.

Abstract: A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract: A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the gate array cell, the poly gate terminal, with at least one section, extends further than the doping zones at least partly in the horizontal direction, thereby enabling improved contact-connection to the adjacent cells.

Abstract: A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells. Bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction. Cuts are formed at positions of the plate lines near the bit line contacts. The active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.

Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively.

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract: Disclosed in a semiconductor device comprising a semiconductor substrate, and a ferroelectric layer provided above the semiconductor substrate and sandwiched between a lower electrode and an upper electrode, the lower electrode comprising a strontium ruthenate film having a thickness of 2 nm or less.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: A semiconductor device including square type storage nodes and a method of manufacturing the same. Word lines are formed on a semiconductor substrate Bit lines are formed separated from the word lines and perpendicular to the word lines. Active regions are defined to have a major axis slanted to the word line direction and the bit line direction. Storage nodes of capacitors are arranged along the word lines overlapping the word lines and arranged in a zigzag pattern that centers upon the bit lines. Storage node contacts are formed to electrically connect the active regions to the storage nodes, while being self-aligned with the bit lines, separated from each other on the word lines, and with a larger line width in the word line direction than the bit line direction to overlap large areas of the storage nodes.

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.

Abstract: A non-volatile memory structure including a substrate, a first memory cell row, a first source/drain region, and a second source/drain region is described. The first memory cell row is disposed on the substrate and includes a plurality of memory cells, two select gate structures, and a plurality of doped regions. The select gate structures are respectively disposed on the substrate at one side of the outmost memory cell among the memory cells, and the select gates have a tapered corner at one side far from the memory cells. The doped regions are respectively disposed in the substrate between two memory cells as well as in the substrate between the memory cells and the select gate structures. The first and the second source/drain regions are respectively disposed in the substrate at both sides of the first memory cell row.

Abstract: A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed. A disclosed method includes forming a trench in a region where a main gate pattern is to be formed, forming an insulating film having a fixed thickness in the trench, and fixing a scale of the main gate pattern filled in the trench with the thickness of the insulating film. The trench elongates a current flow passage formed by a shape of the main gate pattern.

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.

Abstract: In an ESD protecting element, a plurality of source regions and a plurality of ballast resistor regions are formed. A drain region is formed at a region which is in contact with a channel region in the ballast resistor region, and an n+ type diffusion region is formed at a region isolated from the drain region via an STI region. A third contact is provided on the drain region, first and second contacts are formed on the n+ type diffusion region, and the first contact is connected to a pad. The second contact is coupled to the third contact by a metal wire. The first and second contacts are laid out along the widthwise direction of a gate.

Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.

Abstract: This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.

Abstract: A magnetic shielding device is provided for protecting at least one magnetically sensitive component on a substrate according to embodiments of the present invention. The device comprises a first shield having a top portion, and one or more side portions, wherein the top and side portions along with the substrate encloses the magnetic sensitive component within for protecting the same from an external magnetic field, and wherein the magnetic shielding device contains at least two magnetic shielding materials with one having a relatively higher magnetic permeability property but lower magnetic saturation property while the other having a relatively lower magnetic permeability property but higher magnetic saturation property.

Abstract: An improved hinge for a micro-mirror device composed of a conductive doped semiconductor and immune to plastic deformation at typical to extreme temperatures. The hinge is directly connected to the micro-mirror device and facilitates the manufacturing of an optically flat micro-mirror. This eliminates Fraunhofer diffraction due to recesses on the reflective surface of the micro-mirror. In addition, the hinge is hidden from incoming light thus improving contrast and fill-factor.

Abstract: A SAW apparatus is provided capable of realizing a small size without adverse affect while mounting the active surfaces of the semiconductor integrated circuit and the surface acoustic wave element. The SAW apparatus comprises a semiconductor IC and a SAW element. The semiconductor IC is flip-chip mounted on a bottom of the package, a non-active surface of the SAW element is bonded to a non-active surface of the semiconductor IC by using an adhesive, and an electrode portion arranged in the active surface is wire-bonded to an electrode pattern formed on the side walls of the package by using wires.

Abstract: A differential pressure sensor has a semiconductor wafer having a top and bottom surface. The top surface of the wafer has a central active area containing piezoresistive elements. These elements are passivated and covered with a layer of silicon dioxide. Each element has a contact terminal associated therewith. The semiconductor wafer has an outer peripheral silicon frame surrounding the active area. The semiconductor wafer is bonded to a glass cover member via an anodic or electrostatic bond by bonding the outer peripheral frame to the periphery of the glass wafer. An inner silicon dioxide frame forms a compression bond with the glass wafer when the glass wafer is bonded to the silicon frame. This compression bond prevents deleterious fluids from entering the active area or destroying the silicon. The above described apparatus is mounted on a header such that through holes in the glass wafer are aligned with the header terminals.

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

Abstract: An apparatus may include a first substrate, one or more microelectromechanical systems (MEMS) coupled to the first substrate, a second substrate coupled with the first substrate, and one or more passive components coupled to the second substrate. A method may include aligning a first substrate having one or more MEMS coupled thereto and a second substrate having one or more passive components coupled thereto, and coupling the aligned substrates.