Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a baseboard, a device bay including a fuel cell mounted on the baseboard, and a power pack coupled to the baseboard. The power pack includes a fuel cartridge that delivers fuel to the fuel cell.

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract: This invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part (2) on the base board (4). The semiconductor component (3) is mounted on a thin plate region (17) that is thinner than a thick plate region (16) having its thickness increased by mounting the circuit part (2) on the base board (4). Thus, the thickness of the whole circuit board device is reduced and the filter element (5) is covered with a sufficiently thick dielectric insulating material so as to prevent deterioration in filter characteristic.

Abstract: A circuit board assembly has an attached support assembly. The support assembly includes a support, such as a handle, and a lip substantially perpendicular to the support. The lip strengthens the support such that, as a cable exerts a load on the support assembly, the lip limits deflection of the support relative to the circuit board assembly. In the case where a cable having a cable connector attaches to a port of the circuit board assembly, the support assembly minimizes displacement of the cable connector relative to the port, thereby minimizing the potential for a break in electrical connections formed between the connector and the port. The support assembly also, in such a case, minimizes strain on a wire bundle and over-molded case forming the cable, thereby limiting damage to the over-molded case and disconnection of the wire bundle to the connector that leads to losses in electrical connections formed between the circuit board assembly and computer devices connected to the circuit board assembly.

Abstract: A wind fender to isolate heat sources of a mainboard and direct heat to air vents includes a plurality of notches on the wind fender to allow cables on the mainboard to pass through and confine the movement of the cables along the X axis. The wind fender further has retaining sections normal to the wind fender to prevent the cables from moving along the Y axis. Hence heat of the mainboard may be dispelled quickly and the cables may be laid according to a preset wiring layout to accelerate heat dissipation.

Abstract: A power conversion circuit is provided. The circuit includes an isolated board mounted power module operable to convert a nominal input voltage into an intermediate bus voltage; the board mounted power module being unregulated and controlled in an open-loop; and a plurality of tightly regulated point-of-load converters operable to convert the intermediate bus voltage into respective point-of-load voltages to power a respective number of loads.

Abstract: An electronic circuit includes a first power source, a second power source, a load, and a converter connected to each power source and the load. The converter has (i) a first oscillator circuit connected to the first power source, (ii) a second oscillator circuit connected to the second power source, the first and second oscillator circuits being electrically isolated from each other, (iii) an isolation transformer which includes a first primary winding connected to the first oscillator circuit, a second primary winding connected to the second oscillator circuit, and a secondary winding coupled to the first and second primary windings by magnetic inductance, and (iv) a rectifier circuit connected to the second winding and the load.

Abstract: A switching power source apparatus has a series circuit connected to both ends of a DC power source Vdc1 and having a reactor L3, a primary winding 5a of a transformer T, and a switch Q1, a series circuit connected to both ends of the primary winding and having an auxiliary switch Q2 and a clamp capacitor C3, a saturable reactor SL1 connected in parallel with the primary winding, a rectifying-smoothing circuit D1, D2, L1, C4 for rectifying and smoothing a voltage generated on a secondary winding 5b, and a control circuit 10 for alternately turning on/off the switches Q1 and Q2 and turning off the switch Q2 if a current of the switch Q2 increases due to saturation of the saturable reactor SL1. The reactor L3 is made of leakage inductance between the primary and secondary windings.

Abstract: A high voltage power supply (HVPS) including an oscillation circuit for generating and outputting an alternating current (AC) voltage using an oscillation of a transformer, and a voltage multiplying circuit for increasing the AC voltage from the oscillation circuit using a plurality of voltage doublers, and outputting the increased AC voltage. The power supply further includes a controller for controlling the oscillation circuit.

Abstract: A capacitor-input type three-phase rectification circuit comprises a three-phase AC power supply (1), a diode rectifier circuit (4), and a low-frequency filter connected between the three-phase AC power supply (1) and the diode rectification circuitry (4), the low frequency filter consisting of AC reactors (2u)(2v)(2w) and ?-connection or Y-connection capacitors (8u)(8v)(8w), so that higher harmonic currents are reduced to be equal to or less than standard values, and that lowering in input power factor and lowering in DC voltage are prevented from occurrence.

Abstract: This invention relates to a method of operating a bridge circuit comprising an input that receives a DC signal of voltage +VS, an output having an electromagnet connected thereacross, first and second arms having first and second switches respectively and being connected to opposed ends of the electromagnet. The method comprises the steps of receiving a voltage demand signal indicative of a desired voltage to be supplied to the electromagnet in a period and generating first and second switching signals with reference to the voltage demand signal. The first and second switching signals are then applied to the first and second switches respectively during the period thereby causing the switches to switch between on and off states to produce voltages across the electromagnet pulsed at levels of +VS, 0V and ?VS, such that the average voltage across the electromagnet during the period is substantially equal to the desired voltage.

Abstract: A terminal structure for power electronics circuits reduces the need for a DC bus and thereby the incidence of parasitic inductance. The structure is secured to a support that may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as by direct contact between the terminal assembly and AC and DC circuit components. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

Abstract: An apparatus for generating electronic signals for application in subsea electromagnetic exploration. A surface generated high-voltage low-current source signal stabilized at a first frequency is supplied to a deep-tow vehicle (18) via an umbilical cable (16). The high-voltage low-current signal is transformed at the deep-tow vehicle to a high-current low-voltage a.c. signal by a transformer (52) within a cycloconverter (30). A semiconductor relay bridge (104) provides switchable rectification of the high-current low-voltage a.c. signal to provide a quasi-square wave at a second frequency, lower than the first frequency, for supply to a transmitting antenna (22) towed by the deep-tow vehicle. The times of the rectification switching are dependent on zero crossings of the high-current low-voltage a.c. signal. Allowable rectification switching times may be gated to occur only within pre-determined time windows to avoid noise-induced zero-crossing switching.

Abstract: This invention provides, in an exemplary embodiment, a Content Addressable Memory (“CAM”) architecture providing improved speed by performing mutually exclusive operations in first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in the second state of the same clock cycles. The Content Addressable Memory (CAM) architecture comprises an array of CAM cells connected to a compare-data-write-driver and to a read/write block, for receiving the compare-data and for reading and/or writing data in the array of CAM cells respectively, outputs of the said CAM cell are coupled to a match block providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during first state and enabling read-or-write operations within the second state of the same clock cycle in the event of a match.

Abstract: A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

Abstract: A memory device includes a semiconductor substrate, a transistor formed by using the semiconductor substrate, and a capacitor connected to the semiconductor substrate. Changes in electric conductivity of the semiconductor substrate are used as different data, and the transistor reads the data. By changing the amount of charge stored in the capacitor, a density of carriers (electrons) of the semiconductor substrate is changed.

Abstract: A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer is separated from the fixed layers by insulating layers preferably with different thicknesses, or with different material compositions. The resulting junction resistance can exhibit at least four distinct resistance values dependent on the magnetic orientation of the free magnetic layer. The cell is configured using a pattern with four lobes to store two bits, and eight lobes to store three bits. The resulting cell can be used to provide a fast, non-volatile magnetic random access memory (MRAM) with high density and no need to rewrite stored data after they are read, or as a fast galvanic isolator.

Abstract: A method and system for providing a magnetic memory is included. The method and system include providing at least one magnetic storage cell and at least one dummy resistor coupled with the at least one magnetic storage cell at least for a write operation of the at least one magnetic storage cell. Each of the at least one magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction. The selection device is configured to be coupled between the magnetic element and the at least one dummy resistor.

Abstract: Magnetic elements having unique shapes. In one example, the magnetic element defines an outer peripheral profile and a center point, wherein the outer peripheral profile includes a substantially curviform section and a notch section. The notch section may be configured to radially extend to at least the center point. In another example, a substantially circular or oval-shaped magnetic element defines an outer periphery and a gap void having an open end facing the outer periphery so as to form a gap along the outer periphery. The magnetic element optionally may not include an annular void that is spatially isolated from the gap void.

Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.

Abstract: Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises a magnetic memory cell and a conductor configured to provide a magnetic field to write the magnetic memory cell. Structure is configured to direct the magnetic field and reduce coercivity of the magnetic memory cell.

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.

Abstract: An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device is for setting one or more operational modes of a plurality of operational modes including at least a first reading mode of reading out data from a memory array 4, a programming mode, an erasing mode and a second reading mode of reading out data not stored in the memory array 4, in accordance with an input control command, and for performing a predetermined process in the set operational modes. The erroneous operation preventing circuit comprises an operational mode enforcing circuit 2a for setting the first reading mode regardless of the input of the control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data.

Abstract: A method of a flash memory storage device using a copy back command is provided. An error correction rule is adopted to determine whether or not data errors occurred in the un-amended data stored in the page, wherein when it is determined that data errors has occurred in the un-amended data, then a data transfer command is executed, thereby enabling the flash memory storage device to use the block having a faster transferring speed to executing the copy back command. Thus, the data in the flash memory storage device is not only correct and complete but also the stability of the system is promoted.

Abstract: The disclosed is a method of reading a multi-level NAND flash memory cell and a circuit for the same. The read circuit for the NAND flash memory device includes a NAND flash memory cell having multi-level information, a first page buffer for storing an upper-bit, a second page buffer for storing a lower bit, and pass transistor for changing information of the second page buffer according to a variation of the first page buffer. In accordance with the present invention, “00” or “01” information is read out by applying a first voltage to a word line of the cell. “00”, “01”, or “11” information is read out by applying a second voltage to the word line. A latch pass control signal is applied to a pass transistor. Thus, it is possible to read out “00”, “01”, “11”, or “10” information.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

Abstract: Systems and methods are disclosed herein to provide improved verification of flash memory erasure. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an array of flash memory cells. A plurality of sense amplifiers are also provided wherein each sense amplifier is associated with a plurality of the flash memory cells and adapted to detect a state of one of the associated flash memory cells selected from the plurality of flash memory cells. A first logic circuit is also provided to receive the states of the selected flash memory cells from the sense amplifiers and perform a first logic operation at approximately the same time on the states to verify that all states of the selected flash memory cells correspond to an erased state.

Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.

Abstract: Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B1) and the second bit (B2) coincide with their respective initial states and includes maintaining the initial states of the first bit (B1) and the second bit (B2). A second step is executed if both the first bit (B1) and the second bit (B2) have erased final states and the initial states of both the first bit (B1) and the second bit (B2) were not erased and includes erasing both the first bit (B1) and the second bit (B2). A third step is executed if neither the first bit (B1) nor the second bit (B2) is to be changed from a programmed initial state to an erased final state and includes programming the first bit (B1) if the first bit (B1) is to be changed from an erased initial state to a programmed final state, and/or programming the second bit (B2) if the second bit (B2) is to be changed from an erased initial state to a programmed final state.

Abstract: A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

Abstract: A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract: A reading/writing process control unit for instructing a reading/writing process and an erasing process control unit for instructing an erasing process are provided separately and each is connected with two HDDs via a switch. While the reading/writing process control unit is connected with one HDD and executing a reading/writing process, a switch is controlled to connect the erasing process control unit with another HDD to erase data of the HDD connected with the erasing process control unit. Since it is enabled to execute a data reading/writing process and a data erasing process for a storage device in parallel for different HDDs, lowering of the access rate as a whole can be prevented.

Abstract: A volatile memory element and a nonvolatile memory element, each of which is constituted of a field effect transistor, are formed on a single semiconductor chip. The volatile memory element includes a body region, a gate electrode, and two diffusion layer regions, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to a gate electrode, in accordance with an amount of electric charge retained in the body region. The nonvolatile memory element includes diffusion layer regions, a gate electrode, and two memory function sections, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to the gate electrode, in accordance with an amount of electric charge retained in the memory function sections. Thus, it is possible to form the volatile memory and the nonvolatile memory on a single chip with a simple process.

Abstract: A replenish circuit for a semiconductor memory device, including a bias current generating unit adapted to generate a bias current, a frequency controllable oscillator adapted to receive the bias current and to provide an oscillating output, and a pulse generator adapted to receive the oscillating output and to generate first and second pulses as a function of the oscillating output, the second pulse being embedded in the first pulse, the first pulse causing the bias current generating unit to be connected to a power supply, and the second pulse being fed to sample-and-hold circuitry adapted to sample the bias current and hold the value thereof during the first pulse.

Abstract: A semiconductor system includes a plurality of memory systems (SARM, ROM, etc.) and circuit systems. The semiconductor system further includes an analog power supply circuit which is common to the memory systems. The analog power supply circuit supplies a source potential to word line drivers of the memory systems. The source potential is set to a potential different from a ground potential and a supply voltage of the semiconductor system.

Abstract: An integrated circuit and a method for configuring programmable logic thereof are described. A data register and an address register are coupled to an array of memory cells of the integrated circuit. Address storage is configurable for storing an address associated configuration data targeted for being written to at least one defective memory cell of the array of memory cells. Data storage is configured to store the configuration data associated with the at least one defective memory cell. A controller is configured to cause the address to be loaded into the address register and the configuration data to be loaded into the data register. The controller is configured to maintain a write state for continually writing the configuration data to the array of memory cells responsive to the address during operation of the integrated circuit.

Abstract: A system device receives a first data signal and a first strobe signal from a dual-data-rate (DDR) memory. A first delay value representative of a delay to a predetermined phase location of the first strobe signal is determined. The first delay is adjusted based on a first offset value to generate a first adjusted delay value used to delay the first strobe signal. A first edge of a first pulse of the first delayed strobe signal is used to latch a first data value of the first data signal.

Abstract: An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.

Abstract: A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.

Abstract: A semiconductor memory device according to the present invention includes a BIST circuit for evaluating quality of each of memory cells and a buffer (memory) for storing address information of abnormal cells which information is sent from the BIST circuit, the BIST circuit and the buffer being mounted on the same chip as a DRAM. A repair search circuit determines a minimum of address information required to determine redundant cells for replacement in the address information of the abnormal cells which information is sent from the BIST circuit, and stores only the determined address information in the buffer. Since only a minimum of address pairs required determining the redundant cells for repairing the abnormal cells are stored in the buffer, circuit scale is reduced. Further, processing for calculating address information of the redundant cells for repairing the abnormal cells can be performed at high speed.

Abstract: A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lines upon every refresh request. An activation circuit activates any of the normal word lines and redundancy word line according to an output of the shift register. A first storing circuit stores in advance a defect address indicating a defective normal memory cell row. A first activation control circuit prohibits activation of a normal word line corresponding to the defect address stored in the first storing circuit when the output of the shift register indicates the normal word line.

Abstract: A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.

Abstract: In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also includes logic circuitry configured to generate an address for a read port.