Abstract: In order to that stress generated within a resin can be suppressed and cracking in the resin can be prevented, an ink jet recording head comprising a substrate; a resin body, which defines an ink discharge section, formed on the substrate; and a heating resistor provided on the substrate, an ink chamber being formed between the heating resistor and the ink discharge section, the resin body being dug down along the ink chamber, is provided.

Abstract: The present invention provides a group III nitride semiconductor substrate with low defect density as well as small warp and a process for producing the same; for instance, the process according to the present invention comprises the following series of steps of: forming a metallic Ti film 63 on a sapphire substrate 61, followed by treatment of nitration to convert it into a TiN film 64 having fine pores; thereafter growing a HVPE-GaN layer 66 thereon; forming voids 65 in the HVPE-GaN layer 66 by means of effects of the metallic Ti film 63 and the TiN film 64; and peeling the sapphire substrate 61 from the region of the voids 65 to remove it therefrom.

Abstract: A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level.

Abstract: A method of forming a liquid crystal cell for a liquid crystal display device includes defining a first cell region, second cell regions having smaller sizes than the first cell region, and a buffer region disposed between adjacent second cell regions on a first base substrate. After the regions are defined, elements are formed in the first and second cell regions and a buffer pattern is formed in the buffer region. An alignment layer is formed to cover the elements and the buffer pattern. The alignment layer is then rubbed along a direction from the second cell regions to the first cell region.

Abstract: The invention provides a process for producing a light-emitting semiconductor device, which comprises: (1) forming a polycarbodiimide-containing layer on a light takeout side of a light-emitting semiconductor element; and (2) forming irregularities on the surface of the polycarbodiimide-containing layer.

Abstract: A robust single-chip hydrogen sensor and a method for fabricating such a sensor. By utilizing an interconnect metallization material that is the same or similar to the material used to sense hydrogen, or that is capable of withstanding an etchant used to pattern a hydrogen sensing portion, device yields are improved over prior techniques.

Abstract: A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies that incorporate the flexible film interposer, and methods of fabricating the devices and assemblies are provided. The incorporation of the flexible film interposer achieves densely packaged semiconductor devices, without the need for a redistribution layer (RDL).

Abstract: A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Abstract: A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in a packaging material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

Abstract: The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

Abstract: A receiving layer is formed from a thermosetting resin precursor. An interconnecting layer is formed on the receiving layer from a dispersion liquid containing conductive particles. Heat is applied to the receiving layer and the interconnecting layer to cure the thermosetting resin precursor and to bond the conductive particles together.

Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.

Abstract: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may include a plurality of mutually adhered regions. The stiffeners may be configured to prevent torsional flexion or bending of the connective structure to which they are to be secured, to reinforce sprocket or indexing holes in connective structures or to include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude.

Abstract: A compression molding method for forming a mold cap over an integrated circuit structure is provided. A film is positioned adjacent a first die structure such that a mold block coupled to the film is located in a die cavity in the first die structure. The mold block comprises mold compound and at least substantially holding its own shape. An integrated circuit structure including one or more integrated circuit devices coupled to a substrate is positioned adjacent a second die structure. At least one of the first die structure and the second die structure is moved toward the other die structure to cause the integrated circuit structure to compress the mold block within the die cavity in order to form a mold cap covering at least one of the one or more integrated circuit devices.

Abstract: A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

Abstract: A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.

Abstract: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display device having a low electric resistivity can be obtained.

Abstract: Disclosed herein is a method for fabricating a memory device. According to the present invention, a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, and a semiconductor substrate in the recess gate region is etched. Accordingly, a silicon horn in the recess gate region is prevented from being formed, thereby increasing a margin of the etching process.

Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.

Abstract: In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.

Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.

Abstract: A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

Abstract: A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose an inter-metal dielectric layer adjacent to the second conductive layer in the memory cell region. The exposed inter-metal dielectric layer is etched off to form an opening adjacent to the second conductive layer. A capacitor dielectric layer and third conductive layer are formed on inner walls of the opening to constitute a metal-insulator-metal capacitor.

Abstract: A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A DRAM is provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a memory cell region and suppress malfunction caused by noise. The trench-type stacked cell includes a number of capacitors having the same shape. The capacitors are formed in such a manner that storage nodes, a capacitor insulating film, and a plate electrode are buried in each of a plurality of trenches of an interlayer insulating film. The cell layout can be as follows: the capacitors are arranged so that only a part of a side face of one trench is opposite to that of the other; the capacitors are arranged so that the side face of one trench is opposite completely to that of the other and the distance between the opposing side faces is larger at the central portions of the respective trenches; or the cell is arranged so that the plate electrode is buried in a concavity between the cell capacitors.

Abstract: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor substrate, a gate oxide film that is formed on the semiconductor substrate below the floating gate with respect to the tunnel oxide film, wherein the gate oxide film is formed along the boundary of some of the bottom and side of the floating gate, and floating nitride films that are buried at gaps between the gate oxide film formed on the semiconductor substrate and the gate oxide film formed along the boundary of some of the bottom and side of the floating gate, wherein the floating nitride films serve as a trap center of a hot charge and store 1 bit charge. The transistor of the semiconductor device can operate as a 2-bit or 3-bit cell transistor.

Abstract: Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.

Abstract: A method for fabricating a semiconductor device is disclosed. The method provides etching a predetermined region of a semiconductor substrate prior to formation of a device isolation film defining an active region and forming a gate having a stepped gate channel.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diffusing the impurity ions, depositing an interlayer insulator film on the isolation regions, the silicon substrate, and the gate electrodes, and heating the silicon substrate by irradiating a light having a wavelength that the light is absorbed by the silicon substrate without being absorbed by the interlayer insulator film, activating the impurity ions so as to form source and drain regions.

Abstract: In a micromachine according to this invention, a polyimide film is formed on the surface of each electrode. The polyimide film is formed as follows. A substrate having each electrode and a counterelectrode are dipped in an electrodeposition polyimide solution, and a positive voltage is applied to the electrode. A material dissolved in the electrodeposition polyimide solution is deposited on a surface of the positive-voltage-applied electrode that is exposed in the solution, thus forming a polyimide film on the surface.

Abstract: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a cond

Abstract: A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A method of isolating semiconductor devices including forming a pad layer on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined depth using the pad layer as an etch barrier, implanting ion impurities into a bottom of the trench so as to increase an oxidation rate thereat, performing heat treatment for activating ion implanted impurities, growing a liner oxide film on a bottom and a sidewall of the trench, forming an isolation film on the liner oxide film so as to fill the trench, and smoothing the isolation film.

Abstract: The invention relates to a layer sequence on a substrate made from copper, a copper-based alloy, a copper-plated substrate or a nickel or a nickel-based alloy for production of a composite material, in which a covering layer, consisting of tin or a tin-based alloy, which is arranged at least over part of the substrate, a barrier layer, which is located between the substrate and the covering layer and is in direct contact with the substrate, the barrier layer consisting of at least one element selected from the group consisting of Fe, Co, Nb, Mo or Ta, and an intermediate layer and a reaction layer, which is located between the barrier layer and the covering layer, the intermediate layer consisting of at least one element selected from the group consisting of Cu and Ni. The reaction layer required between covering layer and intermediate layer consists of Ag, an Ag alloy or Pt and Pd and its alloys.

Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.

Abstract: Methods are provided for producing a transfer layer of a semiconductor material on a final substrate. In some embodiments, the transfer layer is produced on the final substrate by forming a layer of semiconductor material on an initial support, assembling that layer and a final substrate by metal bonding, and mechanically separating the initial support from the layer at a weak interface that initially attached the layer to the initial support. An intermediate substrate can be obtained which can be used to fabricate a variety of components such as light-emitting diodes or laser diodes. These techniques can produce a transfer layer on a final substrate and a recyclable initial support that can be detached from the transfer layer for recycling by dint of non-destructive mechanical release.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: Nano-scale devices and methods provide reduced feature dimensions of features on the devices. A surface of a device substrate having a pattern of spaced apart first nanowires is consumed, such that a dimension of the first nanowires is reduced. A second nanowire is formed in a trench or gap between adjacent ones of the first nanowires, such that the nano-scale device includes a set of features that includes the first nanowires with the reduced dimension and the second nanowire spaced from the adjacent first nanowires by sub-trenches.

Abstract: A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. More specifically, a low resistance source and drain (n+ type semiconductor regions, p+ type semiconductor regions) with less junction leakage current are formed, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+ type semiconductor regions, p+ type semiconductor regions) of the MISFET, by depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (Co2Si) layer to a cobalt monosilicide (CoSi) layer and, then, to a cobalt disilicide (CoSi2) layer, successively.

Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed to a low level, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.

Abstract: A method for manufacturing a metal structure using a trench includes etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a portion of the insulating layer to expose a portion of the seed layer at a bottom of the trench, filling the trench with a metal material, and removing the seed layer and the insulating layer on the semiconductor substrate. As a result, a subsequent process in forming a multi-layered structure may be easily carried out, thereby simplifying a manufacturing process.