Abstract: A battery sensor has a current meter, an analytical unit, and a microprocessor. During an idle phase, in which the electrical main user, provided with a battery, is switched off, the following steps are carried out. The microprocessor is switched off. At given intervals the measured signal from the current meter is recorded for a given first duration by the analytical unit and allocated first current values which are monitored in the analytical unit for exceeding a first current threshold or dropping below a second current threshold. On exceeding or dropping below the current thresholds, the microprocessor is switched on and, for a given second duration, the measured signal from the current meter is recorded by the analytical unit and allocated second current values which are then analysed in the microprocessor. Procedures for obtaining the electrical charge of the battery by the microprocessor are initiated when a given condition is met, which is dependent on the second current values.

Abstract: A method for determining a maximum IR drop on a power grid of a circuit is disclosed. The method includes dividing a reference timing signal into multiple bins. Each one of the bins having a corresponding bin duration. The bins being divided by a corresponding fuzzy boundaries. Each one of the fuzzy boundaries having a corresponding boundary duration. Each one of the of bins is analyzed including selecting one of the bins, identifying a first set devices that transition to their corresponding maximum current states during the selected bin and identifying a second set of devices that transition to their corresponding maximum current states during at least one of the boundaries of the selected bin, but not within the selected bin. A maximum current demand equal to a sum of the maximum current states of the first and second plurality of devices is calculated. A system for testing a circuit is also disclosed.

Abstract: The present invention provides a system for, and method of, adaptable testing of backplane interconnections. In one embodiment, the system includes a board detector configured to determine a relative arrangement of a plurality of hardware boards populating positions associated with the backplane interconnections. Additionally, the system also includes a test coordinator coupled to the board detector and configured to adaptively backplane test at least a pair of the plurality of hardware boards based on the relative arrangement.

Abstract: A circuit board characteristic impedance inspection method and apparatus is proposed, which is designed for inspecting the characteristic impedance of a circuit board, and which is characterized by the provision of a set of measurement contact points on the circuit board so that during actual inspection, a set of probes can be attached to these measurement contact points for an impedance measurement instrument to measure the characteristic impedance of the circuit board, and then the measured characteristic impedance is compared against a specification value to check if the characteristic impedance meets requirements. This feature allows the manufacturer to conveniently and efficiently inspect whether each manufacturer circuit meets customer-specified requirement in characteristic impedance, and therefore ensures each manufactured circuit board to be reliable to use and quality-assured for shipment to the customer.

Abstract: A testing method or apparatus utilizes multiple frequencies applied to a device under test for measuring newly discovered frequency modulation effects. An embodiment may include a lower frequency signal with a smaller amplitude higher frequency signal to test a dynamic change in frequency response, gain, and or phase. This dynamic test can reveal frequency modulation effects. Another embodiment may include the use of a multiple frequency signal to dynamically induce a time varying phase or frequency distortion for the device that has differential phase distortion. The device's output is then measured with an FM detector to measure a shift in one of the frequencies used in the test signal or to measure frequency modulation effects of any signals, including distortion products, from the device.

Abstract: The present invention relates to an apparatus and method for analysing an amount of at least one component in a sample by measuring a microwave signal that has passed at least partially through the sample. The apparatus preferably comprises: a microwave generator that generates a continuous linear sweeping microwave signal varying in frequency, a microwave transmitter, a microwave receiver, at least one microwave analyser that analyses phase shift and/or change in amplitude of a transmitted and received signal, a means for determining a depth of the sample and a processor that determines the amount of the component(s) in the sample from the determined depth and an output signal from the microwave analyser.

Abstract: The present invention generally relates to an evanescent microwave spectroscopy probe and methods for making and using the same. Some embodiments relate to a probe in electrical communication with sapphire tuning capacitors that are arranged in parallel. Some embodiments relate to using capacitors arranged in this manner to achieve higher Q values. Furthermore, probe can be used in microwave microscopy applications, and for imaging samples thereby.

Abstract: A determination of an equivalent series resistance (ESR) effect for high frequency filtering performance of a filtered feed-through assembly is described. A low frequency signal is introduced to a filtered feed-through assembly. ESR limit of the filtered feed-through is determined based on the low frequency signal.

Abstract: Disclosed herein are a sheet-like probe capable of surly preventing positional deviation between electrode structures and electrodes to be inspected by temperature changes in a burn-in test, even when the object of inspection is a wafer having a large area of 8 inches or greater in diameter or a circuit device, the pitch of electrodes to be inspected of which is extremely small, and thus capable of stably retaining a good electrically connected state, and a production process and applications thereof. The sheet-like probe of the present invention comprises a contact film obtained by holding a plurality of electrode structures arranged in accordance with a pattern corresponding to respective electrodes to be connected and having a front-surface electrode part exposed to a front surface and a back-surface electrode part exposed to a back surface by an insulating film composed of a flexible resin, and a frame plate supporting the contact film.

Abstract: A photo-fabrication apparatus (1) has a stage (2) for holding a base board (9) thereon, a feeding part (3) for feeding photosensitive material onto the base board (9), a layer forming part (4) for smoothly spreading the fed photosensitive material to form a material layer and a light emitting part (5) for emitting a spatially-modulated light beam onto the material layer. The photo-fabrication apparatus (1) forms a lot of elastic microstructures for fine probe and arranges the microstructures at microscopic intervals in a very small range with high positional accuracy on the base board (9) by repeating formation of a material layer and light emission. The microstructures become elastic probes through plating in a later process.

Abstract: A probe card for integrated circuit devices comprises a printed circuit board, at least one probe pin positioned on the printed circuit board, and at least one ultrasonic generator configured to generate ultrasonic energy. When the probe pin contacts a pad, the ultrasonic generator emits ultrasonic energy to vibrate the probe pin so as to form a recess on the surface of a dielectric layer such as an oxide layer on the pad, and the probe pin is then pressed downward to scratch the dielectric layer to form a signal channel. While some contaminants such as oxide fragments usually adhere to the probe pin when the probe card is used to perform an electrical test of the integrated circuit device, the present invention can use ultrasonic energy to vibrate the probe pin so as to remove contaminants from the probe pin.

Abstract: A probing card and an inspection apparatus which precisely inspect a microstructure having a minute moving section by a simple method are provided. A probing card (6) has a speaker (2), and a circuit substrate (100) which fixes a probe (4), and the speaker (2) is disposed on the circuit substrate (100). The circuit substrate (100) is provided with an aperture region. As the speaker (2) is disposed on that region, a test sound wave is output to the moving section of the microstructure. The probe (4) detects a change in an electrical characteristic caused by the motion of the moving section according to the test sound wave, thereby inspecting the characteristic of the microstructure.

Abstract: A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe tip is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinates of a bond pad on the semiconductor wafer.

Abstract: A probe assembly comprises a probe base plate with a plurality of probes to be used for electrical inspection of a plurality of semiconductor chip regions continuously formed in alignment in the directions orthogonal to each other on a substantially circular semiconductor wafer, and capable of contacting the electrical connecting portions of each semiconductor chip region. The tips of a plurality of probe groups are arranged in the X and Y directions orthogonal to each other on the surface of the probe base plate in correspondence to predetermined chip region groups including the predetermined number of semiconductor chip regions. The arrangement regions of the probe groups are formed discontinuously in both of the X and Y directions. The relative feeding movement of the semiconductor wafer in either of the X and Y directions enables the electrical inspection of all the chip region groups on the semiconductor wafer.

Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

Abstract: A curved spring structure includes a base section extending parallel to the substrate surface, a curved cantilever section bent away from the substrate surface, and an elongated section extending from the base section along the substrate surface under the cantilevered section. The spring structure includes a spring finger formed from a self-bending material film (e.g., stress-engineered metal, bimorph/bimetallic) that is patterned and released. A cladding layer is then electroplated and/or electroless plated onto the spring finger for strength. The elongated section is formed from plating material deposited simultaneously with cladding layers. To promote the formation of the elongated section, a cementation layer is provided under the spring finger to facilitate electroplating, or the substrate surface is pre-treated to facilitate electroless plating.

Abstract: An electronic device test apparatus for testing IC chips (IC) by pushing their input/output terminals (HB) against contact units of a test head, provided with an IC moving system (410) for picking up and moving an IC chip (IC) at the front surface where input/output terminals (HB) are led out, a first camera for capturing an image of the front surface of an IC chip (IC) before being picked up, a second camera for capturing an image of aback surface of an IC chip (IC) after being picked up, and an image processing system for calculating the position of input/output terminals (HB) of an IC chip (IC) picked up by the IC moving system (410) from the image information captured by the first camera and second camera and identifying the relative position of the IC chip (IC) picked up by the IC moving system (410) with respect to a contact unit based on the results of calculation, wherein the IC moving system (410) corrects the position of the IC chip based on the relative position of the input/output terminals (HB) o

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.

Abstract: A test fixture is adapted to shield a device under test (DUT) from time dependent electromagnetic radiation.

Abstract: A substrate inspection method includes forming, along a route extending from a peripheral portion to a central portion of an inspection area, a conducting path built up by combining a plurality of first conducting elements disposed in a first layer of a substrate, a plurality of second conducting elements disposed in a second layer of the substrate and contact holes connecting the first conducting elements and the second conducting elements between the first layer and the second layer, and detecting electrons emitted from the inspection area by irradiating the inspection area with electron beams.

Abstract: There is provided a test apparatus having a test head containing test modules for sending/receiving signals to/from a device-under-test, a device mounting section having a socket for mounting the device-under-test and a performance board placed on the test head to connect each terminal of the test module with each terminal of the device-under-test via the device mounting section, and the performance board has a plurality of sub-boards each containing a part of a plurality of wires for connecting the test module with the device-under-test and a fixing section for attaching and fixing the plurality of sub-boards in a body to the test head.

Abstract: Systems and methods for controlling deposition of a charge on a wafer for measurement of one or more electrical properties of the wafer are provided. One system includes a corona source configured to deposit the charge on the wafer and a sensor configured to measure one or more conditions within the corona source. This system also includes a control subsystem configured to alter one or more parameters of the corona source based on the one or more conditions. Another system includes a corona source configured to deposit the charge on the wafer and a mixture of gases disposed within a discharge chamber of the corona source during the deposition of the charge. The mixture of gases alters one or more parameters of the charge deposited on the wafer.

Abstract: A method and system is provided for characterizing silicon wafers. The method and system provide for measuring a resistance between a pair of points on an epitaxial layer of a wafer's surface. The points may be substantially equidistant from the center of the wafer. The resistance measuring may be repeated at a series of pairs of points, each pair of points being radially spaced apart from an adjacent pair of points. The series of pairs of points may include a control group of pairs. A figure of merit may be calculated by subtracting from 1.0 the ratio of a minimum resistance of the resistances measured between the pairs of points to an average of the resistances measured between the pairs of points in the control.

Abstract: Systems for automated laser header testing are disclosed. A system can include a base portion, a rotary stage supported by the base portion, at least one testing site supported by the rotary stage, and a plurality of testing stations supported by the base portion and radially arranged about a center point of the rotary stage for testing the laser header. Each testing site can include a testing fixture supported by the testing site. The testing fixture can include an air shield providing an isolated environment for testing the laser header. The testing fixture can further include a heat sink and air ducts for controlling testing conditions. Electrical contact members can releasably contact leads of the laser header and a releasing mechanism releases the leads of the laser header from the electrical contact members.

Abstract: An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted “switching point”.

Abstract: In an electrical connecting apparatus, a first guide is arranged in a plate-shaped lower base in which the contactors are arranged. The first guide has a first space for guiding a device under test so that its electrodes will contact the tips of contactors and for positioning the device under test against the contactors. The device under test is guided to the first space by second guides and is received and thrust by the tips of the contactors. By doing so, displacement of the device under test caused by displacement of the upper base or the second guides is prevented.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: A high-voltage sequencer system includes positive and negative high-voltage supplies. A supply regulator is connected to the positive high-voltage supply. A master sequencer and programmable logic controller is connected to the supply regulator to control operation thereof. A high voltage regulator output circuit is connected to the supply regulator to receive high voltage signals therefrom. A plurality of sequencer circuits is connected between the master sequencer and programmable logic controller and the high voltage regulator output. The sequencer circuits provide signals to the high voltage regulator output to produce corresponding high-voltage signal outputs in selected sequences.

Abstract: When a signal having two or more frequency components is fed to a circuit to be measured, a phase of the signal output from the circuit to be measured is measured. A phase measurement device measures an output when an input signal having two input frequency components ?10 and ?20 is fed to an amplifier (circuit to be measured). The phase measurement device includes an orthogonal converter that subjects the output of the amplifier to an orthogonal conversion using an average frequency ?0, which is an average of ?10 and ?20. A phase acquisitioner acquires phases ?1 and ?2 of the input frequency components in the output of the orthogonal converter and a phase ?3 of a distortion component. A match time/phase measurer measures a match time ?t during which phase ?1 is matched with phase ?2, and measures phase ?1 (?t) during that time. A distortion component phase measurer measures phase ?3 (?t) of the distortion component in the match time ?t. A display then displays ?1 (?t) and ?3 (?t).

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly.

Abstract: A transmission circuit includes a first-stage circuit, a second-stage circuit, a negative active feedback circuit and a current buffer. The first-stage circuit includes at least an active MOS device for receiving an input voltage and issuing a first voltage signal. The active MOS device has an inductive feature during operation in a high frequency mode to compensate the first voltage signal. In response to the first voltage signal, the second-stage circuit outputs a first output voltage. The negative active feedback circuit may enhance the bandwidth of the first output voltage. The current buffer may enhance the gain value of the first output voltage. A second voltage signal is issued from the first-stage circuit and compensated by the first output voltage transmitted from the current buffer to enhance the bandwidth and the gain value thereof. In response to the compensated second voltage signal, the second-stage circuit outputs a second output voltage.

Abstract: An input buffer includes a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the input signal and a second input terminal receiving the first output signal for generating a second output signal within a first predetermined voltage range; and a level down module for generating a third output signal within a second predetermined voltage range for the core circuitry in response to the second output signal. The input signal passes through the signal passing module with a substantial voltage drop when a voltage level of the input signal is substantially greater than the first supply voltage, and without a substantial voltage drop when the voltage level of the same is less than or equal to the first supply voltage.

Abstract: A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source terminals. The drain terminal of the second transistor is coupled to the gate terminal of the first transistor. The source terminal of the second transistor is coupled to the source terminal of the first transistor. The gate terminal of the second transistor is coupled to the first voltage source. A third transistor has drain, gate and source terminals. The drain terminal of the third transistor is coupled to the gate terminal of the first transistor. The source terminal of the third transistor is coupled to the second voltage source. The gate terminal of the third transistor is coupled to the first voltage source.

Abstract: A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.

Abstract: A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an external clock signal in response to the power down mode control signal and outputs first and second internal clock signals. A clock selection unit selects one of the first and second internal clock signals based on the power down mode control signal to output the selected signal as an intermediate output clock signal. A phase update unit performs a phase update operation by using the intermediate output clock signal to output a delay locked loop (DLL) clock signal, the first internal clock signal differing in frequency from the second internal clock signal.

Abstract: A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied, and an output controller for controlling the output of the DLL through the idle state whether or not data is output.

Abstract: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The present invention can prevent a phase update operation from being interrupted when the DLL circuit enters a power-down mode. For the above purpose, an off operation of a clock buffer is delayed until a clock signal notifying a final period of the phase update is activated.

Abstract: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.

Abstract: A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.

Abstract: A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract: Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based on the up or down signals, a loop filter for low pass-filtering the output current to produce an analog control voltage, a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal, a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal, and a digital code generator for generating the digital code.

Abstract: A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.

Abstract: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.

Abstract: A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.

Abstract: A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.