Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

Abstract: Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.

Abstract: A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I0+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract: A flip-flop circuit includes a first inverter for inverting a signal of a first node and transferring an inverted signal to a second node, and a second inverter for feeding back a signal of the second node and transferring a feedback signal to the first node. The second inverter includes: a first PMOS transistor and a first NMOS transistor, each gate of which receives the signal of the second node; a second PMOS transistor connected to the first PMOS transistor and having a gate receiving a first voltage, the second PMOS transistor being longer than the first PMOS transistor; and a second NMOS transistor connected to the first NMOS transistor and having a gate receiving a second voltage, the second NMOS transistor being longer than the first NMOS transistor.

Abstract: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.

Abstract: Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adjustable delay cell that delay transmission through the set delay cells of an input signal to the respective set delay cells an amount that does not vary responsive to the control signal. Delay cells that have an adjustable delay time are also provided.

Abstract: A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through one path selected from a plurality of paths having different resistance between the input and the output of the delay line. Accordingly, the delay time can be independently controlled or adjusted by greatly changing the time taken to pass through the delay line according to the change of the power supply voltage.

Abstract: A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

Abstract: A system and method of generating a clock signal are provided for driving a plurality of consecutive circuit phase operations. The method includes generating a clock signal, transmitting the clock signal to one circuit phase operation, and transmitting another clock signal to a previous circuit phase operation. A circuit configured according to the invention can clock a plurality of consecutive circuit phase operations with a single master clock, where each circuit phase generates a clock signal to clock a previous phase, obviating connections from a master clock to multiple phases.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

Abstract: The signal switch has flat resistance across the input/output voltage range when in the ON state while still isolating input/output nodes from overshoots and undershoots when in the off state.

Abstract: A switch circuit includes first and second input/output terminals; first depletion-mode transistors serially-connected between first and second nodes; second depletion-mode transistors serially-connected between third and fourth nodes; a common terminal connected to a connection node; a bias circuit feeding a first bias voltage to gates of the first depletion-mode transistors, and feeding a second bias voltage to selected one of the third and fourth nodes; and a switch control terminal receiving a control voltage. The first node is connected to the first input/output terminal, while the third node is connected to the second input/output terminal. The second and fourth nodes are connected to the connection node. A capacitor element is connected between the connection node and selected one of the second and fourth nodes. The switch control terminal is connected to gates of the second depletion-mode transistors, and to selected one of the first and second nodes.

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generator produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract: A negative charge-pump circuit for flash memory includes a well, a pass-gate transistor, a well bias circuit and a negative voltage recovery circuit. The pass-gate transistor has a source, a drain and a gate. The well bias circuit controls the well to remain one of zero biased and reverse biased. The negative voltage recovery circuit is coupled to a negative recovery voltage and coupled to the pass-gate transistor to selectively provide the negative recovery voltage to the pass-gate transistor when the charge-pump circuit is disabled.

Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.

Abstract: An internal voltage generator supplies a stable internal voltage without increasing standby current. The internal voltage generator includes an internal voltage driver for supplying an internal voltage based on a control signal, a feedback circuit for supplying a feedback voltage having a voltage level proportional to the internal voltage, a control signal generating circuit for generating the control signal to control the internal voltage driver such that the feedback voltage is maintained at a desired reference voltage, an auxiliary driving circuit for additionally supplying the internal voltage in response to the control signal, and an auxiliary driving control circuit for activating the auxiliary driving circuit only when it is expected to dissipate a large amount of a current.

Abstract: A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: A band gap reference voltage generation circuit includes a reference voltage output node; a current distributing block coupled between the reference voltage output node and a ground voltage terminal, distributing current and supplying a first voltage and a second voltage; an operation amplifying block comparing the first voltage with the second voltage and outputting an operational amplification signal; a current supplying block coupled between a power supply voltage terminal and the reference voltage output node and supplying current to the current distributing block in response to the operational amplification signal; and a variable resistor coupled to an output node for the operational amplification signal.

Abstract: For one disclosed embodiment, a reference voltage signal is generated. Error in an output voltage signal at an output node is sensed based on the reference voltage signal. The output voltage signal is controlled based on the sensed error. The reference voltage signal is varied as the output voltage signal is controlled. Other embodiments are also disclosed.

Abstract: An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control means to turn on the pull-up driver when a first feedback voltage corresponding to the internal voltage becomes lower than a reference voltage, and a pull-down driving control means to turn on the pull-down driver when a second feedback voltage becomes higher than the reference voltage, the second feedback voltage having a voltage level corresponding to that of the internal voltage and lower than that of the first feedback voltage.

Abstract: An internal voltage generator includes a voltage comparator operating in response to an enable signal, comparing a reference voltage with a feedback voltage and outputting a comparison signal through a first node. A driving controller outputs a drive control signal in response to the comparison signal. An output driver outputs an internal voltage through a second node in response to the drive control signal. An initial operation stabilizer controls the driving controller for a certain period at which the enable signal is enabled to block an output of the drive control signal.

Abstract: The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes.

Abstract: Line drivers with extended linearity are described herein. In one embodiment, an example of a line driver includes, but is not limited to, a first amplifier having a first input, a second amplifier having a second input, the first and second amplifiers driving a load of a communication line, and a trans-conductance stage device coupled to the first and second amplifiers. The trans-conductance stage device is configured to sense a first error voltage across the first input of the first amplifier and to provide a first feedback to the second input of the second amplifier. The trans-conductance stage device is configured to sense a second error voltage across the second input of the second amplifier and to provide a second feedback to the first input of the first amplifier. Other methods and apparatuses are also described.

Abstract: The present invention relates to an input and output signal preservation circuit of an amplification circuit capable of preventing an attenuation of an input signal and an output signal of an amplification circuit in such a manner that an AC input signal is amplified using an amplification device such as a vacuum tube or a transistor in a preamplifier.

Abstract: The invention provides methods and devices for estimating power amplifier nonlinearity using simple correlation techniques. Methods and devices of the invention can monitor a power amplifier that has digitally modulated inputs and an output containing more than one signal stream. A preferred method of the invention creates a test signal by forming the products of several pseudorandom noise sequences from the digitally modulated inputs to the power amplifier. Nonlinear contributions of the power amplifier output are determined by cross-correlating the test signal and the total output signal of the power amplifier. In preferred embodiments, the determined nonlinear contributions of the power amplifier are used to introduce corrective predistortion in the power amplifier.

Abstract: A self-oscillating driver circuit comprises a driver stage, a feedforward path which is coupled to an input of the driver stage, and a feedback path which couples an output of the driver stage to an input of the feedforward path. The feedforward path comprises a feedforward filter which is designed as an active filter. In order to prevent an oscillatory state of the driver circuit at an unwanted frequency, it is proposed that an internal state variable of the feedforward filter be monitored and that the feedforward filter be reset if the value of the monitored internal state variable is outside a predefined range.

Abstract: There is provided an operational amplifier with a broad applicable band and little disturbing noise which is capable of preventing oscillation even when used in connection with a negative feedback path. The present invention relates to an operational amplifier which amplifies a difference between two input voltage signals to a non-inverting input terminal and an inverting input terminal and outputs the amplified difference to an output terminal.

Abstract: A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the first transconductance stage becomes active before the second transconductance stage with respect to the magnitude of a differential input voltage, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current converter. As each of the plurality of transconductance stages is biased differently from the others, the various transconductance stages are biased on to differing amounts based upon the biasing signals as well as the input signal.

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract: A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Abstract: A transistor drive circuit, a constant voltage circuit, and a method thereof provided with a reference voltage generator, a power voltage detector, and a plurality of error amplifying circuits. The plurality of error amplifying circuits have different operational characteristics. One of the error amplifying circuits is selectively activated in response to a control signal in accordance with an operational mode selected. A reference voltage produced by the reference voltage generator or a divided voltage produced by the power voltage detector is also changed in response to the control signal suitably for each one of the plurality of error amplifying circuits which is selectively activated so as to control the power voltage generated by a power transistor to output a constant power voltage.

Abstract: An electronic part for a high frequency power amplifier is provided which is designed to constitute at least a part of a wireless communication system for performing feedback control by detecting an output power, and which can miniaturize a directional coupler. Also, the electronic part permits control of the output power with high accuracy without having any influence on a monitor voltage by a reflected wave propagating through a line of the directional coupler. The directional coupler includes a subline disposed in parallel to and in the vicinity of a part of a main line of an impedance matching circuit on the last output stage side of a power amplifier circuit, a capacitance element connected to between the main line and the subline, and a resistor element connected to between a constant potential point and a termination side of the subline.

Abstract: An active balun device is provided. The active balun device includes: a differential input portion for receiving an external single input signal to output two complementary differential signals; and a differential amplifier connected to the differential input portion in cascade to amplify the two differential signals received from the differential input portion. Thus, the active balun device has a sufficient gain and a desired bandwidth in a semiconductor circuit.

Abstract: The invention relates to the measurement of current pulses that are very brief (a few nanoseconds) and of very low amplitude (a few microamps), such as those that can emanate from a photodetector used for the optical transmission of data at very high speed, or from a photodetector (photodiode or photoconductor) subject to a radiation that is of pulsed nature (in particular: X, gamma and other radiations). The circuit according to the invention comprises an integration stage (IT), a differentiation stage (DR), and a subtraction stage (SS). The time constants Rp.Cint and R2.C2 of the integration and differentiation stages are preferably equal.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A three dimensional (3D) microwave monolithic integrated circuit (MMIC) multi-push voltage controlled oscillator (VCO) and methods of making the same is provided. The 3D MMIC multi-push oscillator includes a plurality of matching frequency oscillators coupled to a phasing ring in substantially equidistantly spaced apart locations. A combined VCO output signal is provided at a central output connection point of the phasing ring. The central output connection point resides on a first plane. An output conductor transition has a first end coupled to the central output connection point and a second end provided as an output to the quad-push VCO. The output conductor transition extends transverse to the first plane and terminates at a second plane separated from the first plane. The multi-push oscillator can be a push-push, quad-push or N-push type VCO based on a particular implementation.

Abstract: In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: Apparatus, systems, methods, and articles may divide a frequency associated with an output of an oscillator formed in a semiconductor substrate using a programmable fractional-N divider module (PFNDM) coupled to the oscillator. A calibration module may be coupled to the PFNDM to select the division ratio to yield a first clock signal of an estimated frequency. Other embodiments may be described and claimed.

Abstract: Embodiments of the present invention provide an oscillator circuit having a steady output frequency that is independent of the supplied voltage. This oscillator includes a Schmitt trigger circuit which may be implemented within an integrated circuit of a wireless terminal or other like portable electronic device. The Schmitt trigger circuit receives a threshold voltage input and a second voltage input. The Schmitt trigger circuit generates an output voltage equal to either a first output voltage or a second output voltage based on the results of comparing the threshold voltage input to the second voltage input. An RC network may be coupled to the output of the Schmitt trigger circuit and is operable to supply the second voltage input to the Schmitt trigger circuit.

Abstract: A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.

Abstract: An oscillation circuit and the method for operating the same.

Abstract: Voltage controlled oscillator (“VCO”) circuitry includes LC tank or ring VCO circuitry and frequency divider circuitry that divides the frequency output by the oscillator circuitry by a selectable integer factor that is at least 2 in the case of a ring oscillator or at least 4 in the case of an LC tank oscillator. This arrangement allows the oscillator circuitry to operate at frequencies that are higher than the desired final output frequencies, which has such advantages as reducing the size and power consumption of the oscillator circuitry, and allowing the circuitry as a whole to have a wide range of operating frequencies while reducing the frequency range over which the oscillator circuitry may be required to operate.

Abstract: An interconnection includes a microcircuit package having a slot, and a receiving feature. A bead ring is fitted into the receiving feature. A center conductor extends through a dielectric support disposed in the bead ring and through the slot. The center conductor forms a coaxial transmission structure in cooperation with the bead ring and the dielectric support, and forms a slab line transmission structure in cooperation with the slot.

Abstract: A mechanism for coupling a coaxial cable (108) to a planar circuit to provide galvanic isolation between the coaxial cable and the planar circuit while providing low transmission loss and reflections between the coaxial cable (108) and the circuit. The mechanism comprises a co-planar waveguide (211) coupled to the coaxial cable (108), a microstrip line (240) connected to the circuit, a galvanic isolation component (234) and a ground plane (222). The co-planar waveguide (211), the microstrip line (240) and the galvanic isolation component (234) are formed on one side (203) of a two-sided substrate (202). The ground plane (222) is formed on the other side (205) of the substrate (202) and underlies at least a portion of the co-planar waveguide (211) to form a grounded co-planar waveguide (221). The ground plane (222) includes a notch (224) underlying a portion of the co-planar waveguide (211) to provide a transition region (225) from the co-planar waveguide (211) to the grounded co-planar waveguide (221).

Abstract: Terminal electrodes 9 for carrying a high frequency device 3 are formed on a surface of a circuit board having its reverse surface covered with a reverse surface conductor layer 6, and a plurality of signal lines 2 for exchanging a signal between the high frequency device 3 and an external circuit are formed thereon. The terminal electrode 9 is arranged at the center of the circuit board, and the signal lines 2 radially extends from the terminal electrode 9. Electromagnetic interference between the signal lines 2 can be reduced, so that out-of-band attenuation characteristics and isolation characteristics can be satisfactorily exhibited in a case where the high frequency device 3 is a duplexer.