Abstract: The invention relates to an oleaginous mildew and corrosion-inhibiting composition, and the use of said composition to protect metal from corrosion and mildew. The composition comprises, in parts by weight, from about 20 to 60 parts of an oleaginous material such as a lubricating oil, 10 to 40 parts of organic solvent, 20 to 60 parts of corrosion-inhibitor consisting of a sulfonic acid-carboxylic acid metal complex or a mixture of said metal complex with a small but effective amount of an oil soluble alkyl phosphate, from 0.1 to 2.0 parts of an oil soluble antioxidant, from 0.0 to 5.0 parts of a water-displacing compound, an effective amount of a mildew-inhibiting compound, and from 0.0 to 1.0 part of a heterocyclic metal deactivator.

Abstract: It is an object of the present invention to provide a method for manufacturing a multi-layered unit for a multi-layered ceramic electronic component which can reliably prevent short circuit failure from occurring in a multi-layered ceramic electronic component. According to the present invention, a multi-layered unit for a multi-layered ceramic electronic component is fabricated by printing a conductive paste containing a butyral system resin as a binder and at least one solvent selected from a group consisting of dihydroterpinyl oxyethanol, terpinyl oxyethanol, d-dihydrocarveol, I-citronellol, I-perillylalcohol and acetoxy-methoxyethoxy-cyclohexanol acetate as a solvent on a ceramic green sheet containing an acrylic system resin as a binder in a predetermined pattern, thereby forming an electrode layer.

Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Abstract: The present invention provides a conductive composition comprising (i) a cyano group-containing polymer compound which is a copolymer of a cyano group-containing monomer and a vinyl group-containing monomer, and n-conjugated conductive polymer.

Abstract: In a near-infrared ray absorption glass lot made of a copper-containing near-infrared ray absorption glass material, a near-infrared ray absorption glass lot is constituted of a glass material of which the tolerance of the refractive index (ne) at a wavelength of 546.07 nm is less than ±0.001.

Abstract: The invention relates to a method for detecting a configuration of a plurality of lifting devices (12, 13) in a lifting system (11), wherein a lifting device (12, 13) is defined as a master lifting device with the node address 1, wherein subsequently a node address n+1 is generated and stored for the subsequent lifting device (12b, 13b) so that the number and assignment of the lifting devices (12, 13) will be detected.

Abstract: A motorcycle rear stand for lifting the rear end of a motorcycle having a rear end lift pivot member and supported on a kickstand having a frame with a pair of side support members, a stop surface at one end of the frame, a pivot mounted at different distances forwardly of the stop surface on each of the side members, a lift arm having a bike engagement member at its outer end mounted on the frame and projecting upwardly therefrom wherein pivotal movement of the frame simultaneously lifts the rear end of a motorcycle and levels the motorcycle from an initial leaning position.

Abstract: A motorcycle rear stand for lifting the rear end of a motorcycle having a rear end lift pivot member and supported on a kickstand having a frame with a pair of side support members, a stop surface at one end of the frame, a pivot mounted at different distances forwardly of the stop surface on each of the side members, a lift arm having a bike engagement member at its outer end mounted on the frame and projecting upwardly therefrom wherein pivotal movement of the frame simultaneously lifts the rear end of a motorcycle and levels the motorcycle from an initial leaning position.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.

Abstract: A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13.

Abstract: A field emission device includes a substrate, a first conductive layer formed over the substrate biased at a first voltage level, a second conductive layer formed over the substrate biased at a second voltage level different from the first voltage level, emitters formed on the first conductive layer and the second conductive layer for transmitting electrons, and a phosphor layer formed over the substrate and being disposed between the first conductive layer and the second conductive layer, wherein the electrons are transmitted from one of the first conductive layer and the second conductive layer through the phosphor layer to the other of the first conductive layer and the second conductive layer in a direction substantially orthogonal to the normal direction of the substrate.

Abstract: A light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a composition modulation layer provided on the n-type contact layer; and a transparent electrode provided on the composition modulation layer. The composition modulation layer consists of a plurality of elements which constitute the compound. A composition ratio of one of the plurality of elements is higher in the composition modulation layer than in the compound. Alternatively, the light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a metal layer provided on the n-type contact layer; and a transparent electrode provided on the metal layer. The metal layer is made of a metal having a lower work function than the compound.

Abstract: A nitride semiconductor device having excellent ESD tolerance, by preventing uneven distribution of the electric current in the p-side nitride semiconductor layer. The p-side nitride semiconductor layer (40) comprises, from the active layer (30) side, (a) a p-side wide band gap layer (12) containing a p-type impurity and (b) a three-layer structure (15) comprising a first p-side nitride semiconductor layer (16), a second p-side nitride semiconductor layer (17), and a third p-side nitride semiconductor layer (18).

Abstract: An organic-inorganic hybrid nanocomposite thin film for a high-powered and/or broadband photonic device having an organic ligand-coordinated semiconductor quantum dot layer, a photonic device having the same, and a method of fabricating the same are provided. The organic-inorganic hybrid nanocomposite thin film is composed of a stack structure comprising a polymer layer and an organic ligand-coordinated semiconductor quantum dot layer self-assembled on the polymer layer, or composed of a first composite thin film comprising a first polymer layer pattern having a first hole, and an organic ligand-coordinated first semiconductor quantum dot layer pattern filling the first hole. The organic-inorganic hybrid nanocomposite thin film may be formed by spin-coating a semiconductor quantum dot solution and a polymer solution alternately to be stacked by one layer so as to form a multi-layered organic thin film composed of a plurality of layers.

Abstract: There is provided a field effect transistor including a substrate, an organic semiconductor layer 6, an insulating layer 3, and a conductive layers 2, 4, and 5, wherein the insulating layer 3 comprises a cured product of a phenol resin represented by the following general formula (1): (R1, R2 and R3 each represent hydrogen atom, halogen atom, hydroxymethyl group, alkyl group having 1 to 12 carbon atoms, alkenyl group, alkinyl group, alkoxyl group, alkylthio group, or alkyl ester group, X1 and X2 each represent hydrogen atom, alkyl group having 1 to 12 carbon atoms, alkenyl group, alkinyl group, or aryl group, and n represents an integer of 0 to 2,000.) According to the present invention, a field effect transistor capable of smoothening the gate electrode having a low surface smoothness, in which a current leak to the gate electrode is small can be obtained.

Abstract: A rectifying diode comprising a semiconducting layer, a first electrode, and a second electrode, wherein the width of the region of closest contact between the two electrodes is on the order of the thickness of the semiconducting layer.

Abstract: In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface of the wide gap semiconductor element is coated, is formed in a three-dimensional steric structure which is formed by linking together organosilicon polymers C with covalent bonds resulting from addition reaction. The organosilicon polymers C have been formed by linking at least one organosilicon polymers A having a crosslinked structure using siloxane (Si—O—Si combination) with at least one organosilicon polymers B having a linear linked structure using siloxane through siloxane bonds.

Abstract: Crosslinkable arylamine compounds; oligomers and polymers prepared from such crosslinkable arylamine compounds; films and coatings; and multilayer electronic devices comprising such films are disclosed.

Abstract: Embodiments of substrate core polymer nanocomposite with nanoparticles and randomly oriented nanotubes and method for making the substrate core are generally described herein. Other embodiments may be described and claimed. In some embodiments, a nanotube suspension is combined with nanoparticle-impregnated polymer.

Abstract: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, an aromatic moiety, at least one of which moieties is substituted with at least one electron donating group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation deposition onto a substrate, wherein the substrate temperature is no more than 100° C.

Abstract: A photosensitive device includes a series of organic photoactive layers disposed between two electrodes. Each layer in the series is in direct contact with a next layer in the series. The series is arranged to form at least one donor-acceptor heterojunction, and includes a first organic photoactive layer comprising a first host material serving as a donor, a thin second organic photoactive layer comprising a second host material disposed between the first and a third organic photoactive layer, and the third organic photoactive layer comprising a third host material serving as an acceptor. The first, second, and third host materials are different. The thin second layer serves as an acceptor relative to the first layer or as a donor relative to the third layer.

Abstract: There is provided an electrode having a first layer of a metallic material having a work function greater than 4.0 eV and a second layer of an organic material having an electron affinity greater than 4.0 eV. The second layer has a thickness in the range of 0.5 to 5 nm.

Abstract: Using a realistic plasmonic model, an optically thick electrically conductive film with subwavelength hole or holes therein is shown to always support propagating modes near the surface plasmon frequency, where cross-sectional dimensions of the hole or holes are less than about ?/2nh, ? being the wavelength of the light and nh the refractive index of the dielectric material in the hole or holes. This is the case even when material losses are taken into account. Based on the dispersion analysis, in both a single hole or hole array designs, propagating modes play a dominant role in the transport properties of incident light. These structures exhibit a new region of operation, while featuring a high packing density and diffraction-less behavior.

Abstract: An organic transistor including a stacked insulating film in which an insulating layer and a wettability control layer are stacked in order is provided, wherein the wettability control layer includes a material whose surface energy can be changed by irradiation with an ultraviolet ray and a transmittance of the ultraviolet ray for irradiation therethrough is 10% or greater.

Abstract: The present invention relates to organic semiconductor diodes, in particular, to the diodes with nonlinear current-voltage characteristics, which are used for power switching, rectifying variable signals, and frequency mixing. The organic semiconductor diode with the p-n junction comprises an anode, cathode, a hole transport layer in contact with the anode, and an electron transport layer in contact with the cathode, and two transport layers being in contact with each other. Another aspect of the present invention is a Schottky barrier diode comprising anode, cathode, and an organic semiconductor layer, wherein the semiconductor layer is either hole or electron transport layer. At least one of the transport layers is characterized by a globally ordered crystalline structure with intermolecular spacing of 3.4±0.3 ? in the direction of one crystal axis. One more aspect of the present invention is a method for obtaining an organic semiconductor layer with the electron-hole type of conductivity.

Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Abstract: A method of testing a semiconductor machine is provided. A wafer is provided and a removable auxiliary layer is formed on the wafer. A low dielectric constant dielectric layer with an expected thickness is formed on the removable auxiliary layer. The actual thickness of the low dielectric constant dielectric layer is measured and then compared with the expected value to determine if the deposition machine operates normally. The low dielectric constant dielectric layer is removed and then the removable auxiliary layer is removed. The method permits a recycling of the test wafer to reduce the production cost.

Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

Abstract: This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

Abstract: Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first direction. A second layer is formed that includes one or more line or trench structures that extend in a second direction that is perpendicular to the first structure, such that a projection of the target structure along the first direction is independent of the second direction and a projection of the target structure along the second direction is independent of the first direction. A target structure and a method for generating a calibration curve are also described.

Abstract: There are provided a test pattern for a semiconductor device includes a buried layer formed on a surface of a substrate; a semiconductor layer formed on an entire surface of the substrate; and first and second high-concentration impurity regions formed in the surface of the semiconductor layer and electrically connected to the buried layer, wherein the first and second high-concentration impurity regions are misaligned. with the buried layer by a predetermined distance; measuring the current flowing through the test pattern in a first direction and a second direction, the first direction being perpendicular to the second direction; and calculating a shifted value of the buried layer from the measuring result.

Abstract: It is conceivable that the problem that a signal is delayed by resistor of a wiring in producing a display which displays large area becomes remarkable. The present invention provides a manufacturing process using a droplet discharge method suitable for a large-sized substrate. In the present invention, after forming a base layer 11 (or base pretreatment) which enhances adhesiveness over a substrate in advance and forming an insulating film, a mask having a desired pattern shape is formed, and a desired depression is formed by using the mask. A metal material is filled in the depression having a mask 13 and a sidewall made from an insulating film by a droplet discharge method to form an embedded wiring (a gate electrode, a capacitor wiring, lead wiring or the like. Afterwards, it is flattened by a planarization processing, for example, a press or a CMP processing.

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract: A conductive structure includes a laminated structure of an upper layer and a lower layer. The lower layer is formed of an aluminum alloy containing at least one kind of Group 8 elements in periodic table. The upper layer is laminated on the lower layer and formed of an aluminum alloy containing at least one kind of Group 8 elements in periodic table and nitrogen.

Abstract: A display device including a plurality of pixels is disclosed. Each of the pixels includes a switching transistor, a plurality of scanning lines connected to the switching transistors and a plurality of data lines connected to the switching transistors. The scanning lines transmit a gate turn-on voltage that turns on the switching transistors and a gate turn-off voltage that turns off the switching transistors and the data lines transmit a data voltage. The gate turn-on voltage is determined based on a maximum value of the data voltage. The gate turn-on voltage based on the maximum value of the data voltage results in high luminance and less crosstalk phenomenon.

Abstract: A thin film transistor according to an embodiment of the present invention includes: a substrate; a control electrode disposed on the substrate; a gate insulating layer disposed on the control electrode; a semiconductor member disposed on the gate insulating layer, overlapping the control electrode, and including a first portion of amorphous silicon and a second portion of polycrystalline silicon; an input electrode contacting the semiconductor member; and an output electrode contacting the semiconductor member.

Abstract: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge groove is formed by an anisotropic etching process, as a first groove in such a way as to have a depth from a surface of the multi-layered semiconductor layer and as not to cross the etching stop layer at the depth. A bottom groove of the ridge groove is formed by an isotropic etching process, as a second groove by performing etching in such a way as to be stopped by the etching stop layer.

Abstract: An LCD panel includes a plurality of gate lines and gate electrodes formed on a substrate and a gate insulating film formed on the substrate including the gate lines and the gate electrodes. A semiconductor film is formed in a region on the gate insulating film and an ohmic contact film formed on the semiconductor film. A plurality of data lines cross the gate lines; a source electrode is formed on the ohmic contact film; and a pixel electrode is formed in a pixel region defined by the gate and data lines. A drain electrode is formed on the ohmic contact film, and has an uneven width. Since a portion of drain electrode that overlaps with the gate electrode has a smaller width than a width of other portions of the drain electrode, variation in an area of the drain electrode overlapped with the gate electrode is small, so that variation of the parasitic capacitance can be reduced, thereby improving picture quality.

Abstract: The semiconductor device according to the present invention has a semiconductor layer having not smaller than two types of crystal grains different in size within a semiconductor circuit on a same substrate.

Abstract: [Problemsp] To provide a semiconductor device including a MIS-type FET having an excellent characteristic of low leakage current despite use of a high-K material of a high dielectric constant in a gate insulating film. [Means for solving Problems] A MIS-type field-effect-transistor (FET) including: a silicon substrate (1); an insulating film (6) formed on the silicon substrate and containing silicon and at least one of nitrogen and oxygen; a metal oxide film formed on the insulating film and containing silicon and hafnium; and a gate electrode formed on the metal oxide film, wherein a silicon molar ratio (Si/(Si+Hf)) in the meal oxide film is in the range of 2 to 15%.

Abstract: Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a polysilicon layer and a tungsten layer and performing an angled implant at the at least one edge portion to form a doped region through the at least one edge portion of the intermediate nitride layer is provided. The intermediate nitride layer may be formed by an anneal process, for example.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A SiC semiconductor device with a SiC layer and an insulating layer is provided. The insulating layer may include glass or ceramic. The thermal expansion coefficient of the insulating layer may be matched to that of SiC to reduce stress at the interface. A method of processing the SiC semiconductor device is also provided.

Abstract: By providing a barrier layer stack including a silicon nitride layer for confining a copper-based metal region, thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region, and a nitrogen-enriched silicon carbide layer, the total relative permittivity may be maintained at a low level, since the thickness of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.

Abstract: A semiconductor material having a stepwise surface structure of (0001)-plane terraces and (11-2n)-plane steps [n?0] on the SiC substrate, a semiconductor device using the same and a method of producing the semiconductor material in which a carbon-rich surface is formed on the SiC substrate prior to epitaxial growth of an SiC crystal, the carbon-rich surface satisfies the ratio R=(I284.5/I282.8)>0.2, wherein I282.8 (ISiC) is an integrated intensity of a C1s signal having a peak at the binding energy relating to stoichiometric SiC (in the region of 282.8 eV), and I284.5 (IC) is an integrated intensity of a C1s signal having a peak at the binding energy relating to graphite, SiCx (x>1), or SiyCH1-y (y<1) (in the region of 284.5 eV), as measured by an X-ray photoelectron spectroscopic analyzer (XPS).