Abstract: A method of manufacturing a device includes forming a dielectric layer on a substrate and forming a resistor on the dielectric layer. A second dielectric layer formed over the resistor is etched to expose edge portions of the resistor. The edge portions of the resistor are doped through the openings. A contact is formed in the openings. A device is also provided.

Abstract: In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.

Abstract: A method for manufacturing a nitride semiconductor substrate comprises the steps of: growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Abstract: A semiconductor device includes a substrate, an inter-metal dielectric (IMD) layer over the substrate, and either a nitrogen-containing tetraethoxysilane (TEOS) oxide layer or an oxygen-rich TEOS oxide layer over the IMD layer. The molecular ratio of oxygen in the oxygen-rich TEOS oxide layer is greater than 70%. The IMD layer comprises an extra-low dielectric constant (ELK) layer.

Abstract: A multiple die package for integrated circuits is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A removable storage card package is also described.

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.

Abstract: A motherboard with selective chip layout includes a first chip mounting area for receiving a first chip, a plurality of first pads located at edges of the first chip mounting area, for attachment of soldering pins of the first chip thereon, a second chip mounting area for receiving a second chip, and a plurality of second pads located at edges of the second chip mounting area, for attachment of soldering pins of the second chip thereon. The second chip mounting area and the second pads are positioned within the first chip mounting area.

Abstract: The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

Abstract: A leadframe for semiconductor packages. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. Each lead has a corresponding lead relative to a predetermined center line. A predetermined pair of corresponding leads are substantial asymmetrical with each other in appearance relative to the predetermined center line.

Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The die may be silicon or GaN based MOSFETs or integrated circuits or a mixture thereof. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant. One die can be connected to the clip as well as the lead frame and the other may be an IC die insulated from the clip.

Abstract: A substrate frame includes an insulative board (10a) having a pair of ear portions (13) extending along its longitudinal edges; a plurality of wiring substrate regions (11) arranged on the insulative board (10a) between the ear portions (13) at predetermined intervals; and a plurality of grooves (18) provided around said wiring substrate regions (11) from which wiring patterns are removed.

Abstract: A LED package includes a LED chip and a flexible carrier, wherein the LED chip has a plurality of electrodes. The flexible carrier has a flexible substrate and a circuit layer, wherein the flexible substrate has a support surface and a back surface opposite the support surface, and the circuit layer is disposed on the support surface. In addition, the LED package further includes a plurality of bumps and the electrodes of the LED chip are electrically connected to the circuit layer of the flexible carrier through the bumps.

Abstract: EMI radiation in an integrated circuit device package (10) is reduced or eliminated by the introduction of a magnetic material into the encapsulating medium (14). The permeance of the magnetic encapsulating medium (14) affects the inherent series inductance of the lead frame conductors (16) to thereby reduce electromagnetic interference. Ferrite microbeads (30) are formed around the lead frame conductors (16) to contain the magnetic flux (32) generated by an electrical current signal and to attenuate the effects of mutual inductance.

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.

Abstract: A designing for a power semiconductor, and especially to a structure of a power semiconductor formed by using the basic materials including two metal plates and a ceramic plate, in the power semiconductor, mainly surfaces of the ceramic base plate provided with a receiving groove is metallized, and the metallic base plates having electric connecting pins extending outwards therefrom are placed at the two lateral sides of the ceramic base plate, then a chip is placed in the receiving groove of the ceramic base plate, and the ceramic base plate is sintered together with the two metallic base plates, thus the structure of the power semiconductor with the twin metal plates and the ceramic plate is formed.

Abstract: An integrated circuit package comprises an integrated circuit die comprising at least four pads that at least one of transmit and receive differential signals. A lead frame comprising at least four leads. At least four bondwires connecting the leads to the pads. A set of polarities of adjacent signals carried by the at least four leads is different than a set of polarities of adjacent signals carried by the bondwires and the pads.

Abstract: A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base.

Abstract: A structure for protecting electronic package contacts and the method for manufacturing the same are provided. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip and the vias for rerouting so as to raise the reliability of the conductor trace line in the electronic package structure. The protecting layer is formed in the wafer-level manufacturing processes by coating, depositing, and printing. The method is suitable for all kinds of electronic package structures owing to its high compatibility.

Abstract: An image sensor module structure and method for manufacturing the same includes a substrate having an upper surface and a lower surface, a chip is mounted on the upper surface of the substrate, a plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate, an adhered layer is coated on the upper surface of the substrate, a lens holder has a lateral wall and internal thread, the lateral wall is adhered on the upper surface of the substrate by the adhered layer to encapsulate the chip, so that the adhered layer is pressed to cover the wires, and a lens barrel is formed with external thread screwed on the internal thread of the lens holder.

Abstract: An implantable hermetically sealed microelectronic device, and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Abstract: An integrated circuit package system including a high-density small footprint system-in-package with a substrate is provided. Passive components are mounted on the substrate. Solder separators are provided on the substrate, the solder separators having flattened tops at a predetermined height above the substrate. A die is supported on the solder separators above the substrate.

Abstract: A method of configuring an electronic device to be operable with an electronic apparatus. The method comprises obtaining at least one image associated with the electronic apparatus, submitting a request for identifying the electronic apparatus to at least one data repository, said request including the at least one image, receiving from the at least one data repository configuration data associated with the electronic apparatus and configuring the electronic device using the configuration data. An electronic device that may be configured according to the disclosed method is also disclosed.

Abstract: Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.

Abstract: A semiconductor die substrate is disclosed for preventing delamination of the die and/or die cracking due to air bubbles trapped beneath the die, and a semiconductor package incorporating the substrate. A solder mask may be laminated on a surface of the substrate which is patterned with one or more passageways, or canals, allowing air bubbles to be expelled from beneath the semiconductor die during the semiconductor package fabrication. The canals may have a variety of shapes, including for example a wavy, undulating shape.

Abstract: In a semiconductor module including a first connection substrate having first and second surfaces opposite to each other, and at least one first semiconductor device mounted on the first surface of the first connection substrate, a second connection substrate having at least one opening is adhered to the second surface of the first connection substrate. At least one second semiconductor device is mounted on the second surface of the first connection substrate through the opening of the second connection substrate, and external electrodes are formed on a surface of the second connection substrate opposite to the first connection substrate.

Abstract: Packaging performance of a semiconductor device is improved. A semiconductor device has a package substrate having a base material formed of resin; a semiconductor chip mounted on a main surface of the package substrate; a tape substrates being stacked on the package substrate in several stages, and electrically connected to a substrate at a lower stage via a plurality of solder balls; a second-stage chip, third-stage chip, and fourth-stage chip mounted on the tape substrates at respective stages; and a plurality of solder balls provided on a back surface of the package substrate; wherein a sealing body, which resin-seals the semiconductor chip and is formed by resin molding, is formed on a main surface of a package substrate disposed at the lowest stage, and the sealing body is disposed between the package substrate at the lowest stage and the tape substrate stacked thereon.

Abstract: A multi-chip package includes a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has an external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.

Abstract: For the purpose of providing a semiconductor element built-in type multilayered circuit board in which a semiconductor element is closely joined to a recess of an insulating substrate to effectively disperse heat generated from the semiconductor element through the insulating substrate at a working temperature region of the semiconductor element circuit board, to surely conduct an electrical connection of an electronic part such as semiconductor element or the like in a short wiring and to enable the high density mounting of semiconductor elements, miniaturization and increase of working speed, there is proposed a semiconductor element built-in type multilayered circuit board formed by laminating a plurality of semiconductor element built-in type boards each comprising an insulating substrate and a semiconductor element accommodated in a recess formed therein, characterized in that a difference between a linear expansion coefficient of the insulating substrate and a linear expansion coefficient of the semicon

Abstract: An active device base and a leadframe utilizing the base. The base includes a plate, a predetermined attachment area for an active device on a surface of the plate, and at least one through hole in the plate, beyond the predetermined attachment region.

Abstract: A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.

Abstract: The electronic-part built-in substrate includes a coreless substrate 11 in which a wiring pattern 31 is formed in laminated insulating layers 26 and 27, a semiconductor chip 14 electrically connected to the wiring pattern 31, a resin layer 13 configured to cover a first main surface of the coreless substrate 11 and to have an accommodating portion 57 that accommodates the semiconductor chip 14, and a sealing resin 19 that seals the semiconductor chip 14 accommodated in the accommodating portion 57.

Abstract: The present invention provides a package device for reducing the electromagnetic/radio frequency interference, which includes a first substrate with a shielding structure on the under surface of the first substrate, and an insulating layer on the shielding structure. The first substrate includes a through hole that is filled with the conductor therein. A plurality of lead-frames located on the bottom surface of the first substrate. A second substrate located above between the two lead-frames. Then, the molding compound encapsulated to cover the above structures to form a package device. Therefore, the shielding path of the package device is constructed of the plurality of lead-frames, the conductor within the first substrate, the shielding structure, and the grounded to discharge the electromagnetic/radio frequency out of the package device, thus, the electromagnetic/radio frequency interference for the package device can be reduced.

Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: A wafer or a portion of a wafer including capped chips such as surface acoustic wave (SAW) chips is provided with terminals by applying a terminal-bearing element such as a dielectric element with terminals and leads thereon, or a lead frame, so that the terminal-bearing element covers the caps, and the leads are aligned with channels or other depressions between the caps. The leads are connected to contacts on the wafer, and the wafer is severed to form individual units, each including terminals supported by the cap and connected to the contacts by the leads. The resulting units can be handled and processed in the same manner as ordinary chips or chip assemblies.

Abstract: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying the ceramic base. The cover includes recesses arranged to receive the one or more die, the ceramic base, gate and drain leads and a portion of the source leads. The cover further includes bolt holes arranged to clamp the ceramic base and source leads to a heat sink. Bosses at corners of the cover outward of the bolt holes exert a downward bowing force along the periphery of the cover between the bolt holes.

Abstract: A thermal management device attachment apparatus may be used to thermally couple a thermal management device to a heat generating component on a circuit board. The attachment apparatus may include a support member mounted on the same side of the circuit board as the heat generating component and extending around at least a portion of the component. The support member may include a circuit board mounting portion, a thermal management mounting portion and a side portion extending between the circuit board mounting portion and the thermal management mounting portion. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant.

Abstract: Described herein is the use of a diffusion barrier layer between metallic layers in MEMS devices. The diffusion barrier layer prevents mixing of the two metals, which can alter desired physical characteristics and complicate processing. In one example, the diffusion barrier layer may be used as part of a movable reflective structure in interferometric modulators.

Abstract: The invention relates to a semiconductor device (10) comprising an electrically conductive bottom plate (1) on an upper side of which a semiconductor element (2) is positioned with a first connection region and a second connection region and with a first conductor and a second conductor, part of which is connected to, respectively, the first and the second connection region of the semiconductor element (2), the semiconductor element (2) and the parts of the conductors connected to the semiconductor element (2) being provided with an electrically insulating resin encapsulation (4) that covers a side face of the bottom plate (1), and the side face of the bottom plate (1) being provided, at the bottom face of the bottom plate (1), with a cavity (5) which is filled with a part of the encapsulation (4). According to the invention, the cavity (5), viewed in a direction transverse and perpendicular to the edge of the bottom plate (1), has the form of a staircase with to steps.

Abstract: A semiconductor memory module includes an electronic printed circuit board with a contact strip and a plurality of semiconductor memory chips of identical type that are mounted on at least one external area of the printed circuit board. The semiconductor memory chips are rectangular in shape and are arranged, in at least two rows with the adjacent chips being oriented perpendicular to one another, such that the area used on the PC board is optimized.

Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: A semiconductor component includes a thin semiconductor chip and a wiring substrate that carries the semiconductor chip on its upper side and includes external contacts on its underside and/or its edge sides. The semiconductor chip is preferably produced from monocrystalline silicon having a thickness d?25 ?m.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: In a semiconductor device, a occupation ratio of the surface of a resin substrate encapsulated with resin by conductor patterns provided on the same surface is set so as to be 70% or higher in order to raise the toughness of the resin substrate during heating and pressurization. Preferably, the distance between conductor patterns is set so as to be 0.15 mm or less. The resin substrate may be prevented from becoming deformed, that is, a semiconductor device in which cracking in a resin substrate, at the time of resin encapsulation, may be prohibited in a simplified manner from occurrence.

Abstract: A semiconductor device comprises: a plurality of semiconductor chip; a socket; and a mounting board equipped with the socket. Each of the semiconductor chips has a major surface, a back surface and a plurality of connection terminals on the major surface. The socket has internal connection terminals inside and external connection terminals outside, and the internal connection terminals are in contact with the connection terminals of the semiconductor chips.

Abstract: A semiconductor device includes a first wiring portion and a second wiring portion. The first wiring portion is configured to include a plurality of fine wirings placed densely. The second wiring portion configured to include a wiring, which is connected to one of the plurality of fine wirings in the same wiring layer, and of which outside dimension is larger than that of the one of the plurality of fine wirings. The wiring of the second wiring portion is composed of a peripheral wiring which circles an outer periphery of the wiring.