Abstract: The invention relates to very small-sized color image sensors. The sensor according to the invention is made by the following method: the formation, on the front face of the semiconductive wafer (10), of a series of active zones (ZA) comprising image detection circuits and each corresponding to a respective image sensor, each active zone comprising photosensitive zones (12) covered with conductive and insulating layers (14, 16) enabling the collection of electrical charges generated in the photosensitive zones, the transfer of the wafer (10) by its front face against the front face of a supporting substrate (20), the elimination of the major part of the thickness of the semiconductive wafer, leaving a very fine semiconductive layer (30) on the substrate, this fine semiconductive layer comprising the photosensitive zones, the deposition and etching of color filters (18) on the semiconductive layer thus thinned.

Abstract: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Abstract: A method for assembling and integrating microstructures (pills) onto a substrate. A plurality of patterned recesses are formed on the substrates, the recesses having transverse cross-sections and openings of specific shapes. A hard magnetic layer is deposited at the bottom of each said recess. A guide is positioned over the substrate, the guide having patterned hole shapes matching the shapes of the openings to the patterned recesses with which the holes mate. A collection of the pills is placed atop the guide. The said collection includes members with cross-sections matching the shapes of the openings to the recesses, and each pill is coated at one end with a soft magnetic layer. A moving magnetic field is applied to the collection of pills to agitate the pills, and effect a magnetic attraction between the layers at the ends of the pills and the soft magnetic layer at the bottom of the recesses.

Abstract: A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.

Abstract: The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of the volume between the bonded integrated circuits. The material may be the same material as that used for underfilling the volume between the bottom integrated circuit and a substrate.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: An improved semiconductor die stacking scheme is provided. In accordance with one embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. In accordance with another embodiment of the present invention a multiple die semiconductor assembly is provided. Each embodiment relates generally to a stacked semiconductor die assembly including a substrate, first and second semiconductor dice including stacking surfaces and active surfaces, a decoupling capacitor, and one or more conductive lines connecting elements of the assembly.

Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: An embodiment is a cyclic olefin semiconductor package. Further an embodiment is a combination of a cyclic olefin monomer and a ruthenium-based catalyst that is stable at approximately room temperature and humidity for extended storage life and pot life, and that can be screen printed or valve/jet deposited.

Abstract: In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.

Abstract: A semiconductor device employing a PD-SOI substrate and a method of manufacturing the same are capable of minimizing a floating body effect. The semiconductor device employs a silicon layer over a buried insulating layer on a silicon wafer, isolating layers in the silicon layer in contact with the buried insulating layer, a body layer of a first conductivity type in the silicon layer between the isolating layers and having a trench, a gate insulating layer and a gate electrode in the trench of the body layer, a spacer on the sidewall of the gate electrode, LDD regions of a second conductivity type in the body layer on both sides of the gate electrode in contact with the buried insulating layer under the trench, and source and drain regions of the second conductivity type the body layer on both sides of the spacer in contact with the buried insulating layer.

Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Abstract: A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.

Abstract: A crystalline semiconductor film having crystal grains of large grain size or crystal grains in which the position and the size are controlled is formed to manufacture a TFT, whereby a semiconductor device that enables a high-speed operation is realized. First, a reflecting member is provided on a rear surface side of a substrate on which a semiconductor film is formed (semiconductor film substrate). When a front surface side of the semiconductor film substrate is irradiated with a laser beam that penetrates the semiconductor film substrate, the laser beam is reflected by the reflecting member to irradiate the semiconductor film from the rear surface side. With this method, an effective energy density is raised in the semiconductor film, and an output time is made long. Thus, the cooling rate of the semiconductor film is made gentle and crystal grains of large grain size are formed.

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n+-type contact from the upper surface of the substrate to the buried n+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

Abstract: A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

Abstract: In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C.

Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A method of forming a capacitor having a capacitor dielectric layer comprising ABO3, where “A” is selected from the group consisting of Group IIA and Group IVB metal elements and mixtures thereof, where “B” is selected from the group consisting of Group IVA elements and mixtures thereof, includes feeding a plurality of precursors comprising A, B and O to a chamber having a substrate positioned therein under conditions effective to chemical vapor deposit an ABO3-comprising dielectric layer over the substrate. During the feeding, pressure within the chamber is varied effective to produce different concentrations of B at different elevations in the deposited layer and where higher comparative pressure produces greater concentration of B. The ABO3-comprising dielectric layer is incorporated into a capacitor, with the ABO3-comprising dielectric layer comprising a capacitor dielectric layer of the capacitor and having a dielectric constant k of at least 20 in the capacitor.

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract: The top of the semiconductor body (1) has a sacrificial layer (4) made of nitride applied to it on a region, which is provided for the actuation circuit. A memory layer (6) provided for the memory cells is applied over the entire area and is removed above the sacrificial layer (4) by dry etching. The nitride in the sacrificial layer (4) can then be removed by wet chemical means without starting to etch the semiconductor material.

Abstract: The disclosure provides methods of forming a silicon quantum dots for application in a semiconductor memory device. One example method includes sequentially forming a pad oxide film and a sacrificial insulation film on a silicon substrate; forming a wall layer by selectively etching the sacrificial insulation film; forming a spacer at the side wall of the wall layer; etching the silicon substrate as much as a predetermined thickness using the spacer as a mask, thereby forming a silicon pattern; forming a barrier film for burying the upper surface and the side surface of the silicon pattern; applying isotropic etching to the substrate using the barrier film as a mask; and oxidizing the isotropic etched substrate with thermal treatment.

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.

Abstract: In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: A method of fabricating a semiconductor device forms a shallow source/drain region after a deep source/drain region. First, a gate insulating layer including a gate pattern and a gate electrode are formed on a semiconductor substrate. A buffer insulating layer, a first insulating layer, and a second insulating layer are then sequentially formed on the entire surface of the gate pattern and the semiconductor substrate. A first spacer is formed on the first insulating layer at both sidewalls of the gate pattern by etching the second insulating layer. A deep source/drain region is then formed on the semiconductor substrate as aligned by the first spacer. The first spacer is removed. Next, an offset spacer is formed at both sidewalls of the gate pattern by etching the first insulating layer. Finally, a shallow source/drain region is formed on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.

Abstract: Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

Abstract: The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.

Abstract: A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

Abstract: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

Abstract: The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.

Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.

Abstract: Methods of forming a device isolation layer in a semiconductor substrate are disclosed. A disclosed method includes: forming a trench in a field area of a semiconductor substrate, growing a SiON layer on an inside of the trench by annealing in an ambience of NO gas, and filling the trench with a trench-fill material.

Abstract: Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer on the semiconductor substrate and the trench, forming a photoresist pattern on the oxide layer exposing the oxide layer on a bottom surface of the trench, forming STI films on sidewalls of the trench by etching the exposed oxide layer using the photoresist pattern as an etch protection layer, removing the photoresist pattern, developing an epitaxial layer between the STI, and planarizing the epitaxial layer and the oxide layer.

Abstract: The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising material sidewalls within the isolation trenches. Electrically insulative trench isolation material is formed within the isolation trenches over the epitaxially-grown silicon-comprising layer. Other aspects and implementations are contemplated.

Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1?yAly)1?xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.

Abstract: Provided is a treatment method of a semiconductor wafer facilitating picking-up of semiconductor chips and preventing contamination by a dicing sheet. A wafer back surface treating method is characterized in that a ground or polished surface of a semiconductor wafer activated in a grinding or polishing step, with semiconductor circuits formed thereon, is deactivated. In the method, the activation treatment with an oxidizing agent is preferable. Furthermore, the activation treatment is preferably implemented with blowing of ozone to a ground or polished surface of a wafer, with ozone water or with illumination of a ground or polished surface of a wafer with ultraviolet (UV). It is preferable to adhere a dicing sheet after the deactivation treatment.

Abstract: The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of the predetermined splitting area which evidences the physical strength of the predetermined splitting area during or after heating to detect anomalies that may lead to damage of the source substrate, handle or assembly. The degree of weakening is advantageously determined in-situ and may be determined continuously or periodically during the heating. The invention further relates to an apparatus for thermal annealing device used in the manufacturing process of a material compound wafer.

Abstract: A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a curved surface provided at an intersection of a side surface of the notch and the rear surface of the substrate.

Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.