Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.

Abstract: Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure (16) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer (18) comprising HfXZr1-XO2, where 0?X?1. An amorphous interlayer (20) overlies the first amorphous dielectric layer. The interlayer has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4. A second amorphous dielectric layer (22) overlies the interlayer. The second amorphous dielectric layer comprises HfYZr1-YO2, where 0?Y?1. The stacked dielectric structure (16) has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.

Abstract: Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement The present invention provides a method for connecting an integrated circuit (C1), in particular a chip or a wafer or a hybrid, to a substrate (C2), which has the following steps: provision of a first electrical contact structure (KF1, BP, LB; KF1, BP?) on a first main area (HF1) of the integrated circuit (C1); provision of a corresponding second electrical contact structure (KF2) on a second main area (HF2) of the substrate (C2); at least one of the contact structures, the first electrical contact structure (KF1, BP, LB; KF1, BP?) or the second electrical contact structure (KF2), being elastic; placement of the first electrical contact structure (KF1, BP, LB; KF1, BP?) onto the corresponding second electrical contact structure (KF2), so that both are in electrical contact and under mechanical compression pressure (P); and connection of a region of the main area (HF1) surrounding the first electrical contact struc

Abstract: Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

Abstract: A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.

Abstract: A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive interconnect material filling multiple features in the pattern. The first conductive interconnect material having an overburden portion. The over burden portion is planarized. The over burden portion is substantially entirely removed in the planarizing process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized over burden portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.

Abstract: A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

Abstract: Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock material and into the interconnect. A layer of electroless material is on the base of the trench and the surfaces of the via, interlock material, and interlock opening. An subsequent interconnect is formed on the electroless material, in the trench, via, and interlock openings. The structure can be repeated to form a stack or column of interconnects that resist delamination.

Abstract: A process for making semiconductor structures uses a decoupled plasma source to produce a highly selective plasma etchant to form a structure with a thin adhesive layer and overlaying conductive layer. The preferred plasma is formed from chlorine and oxygen feed gases. The highly conductive semiconductor structure has a thickness less than about 3000 ?, preferably less than about 2600 ?, and incorporates an adhesive layer that is preferably less than about 100 ? thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.

Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract: High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the process initially dominates the sputter component of the process. For example, reactive gasses are introduced in a gradient fashion into the HDP reactor and introduction of bias power onto the substrate is delayed and gradually increased or reactor pressure is decreased. In the case of a multi-step etch enhanced gap fill process, the invention may involve gradually modulating deposition and etch components during transitions between process steps. By carefully controlling the transitions between process steps, including the introduction of reactive species into the HDP reactor and the application of source and bias power onto the substrate, structure erosion is prevented.

Abstract: A process for producing an electronic device material of a high quality MOS-type semiconductor having an insulating layer and a semiconducting layer. The process includes a step of CVD-treating a substrate to be processed having single-crystal silicon as a main component to thereby form an insulating layer, and a step of exposing the substrate to be processed to a plasma which has been generated from a process gas on the basis of microwave irradiation via a plane antenna member having a plurality of slots to thereby modify the insulating film by using the thus generated plasma.

Abstract: A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

Abstract: There is disclosed a method of processing a substrate, which comprises applying a surfactant or a water soluble polymer agent onto a surface of a substrate to be processed, and sliding a circumferential portion of the substrate and a polishing member against each other to polish the circumferential portion of the substrate.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.

Abstract: A method for forming a high aspect ratio magnetic structure in a magnetic write head using a combination of chemical mechanical polishing and reactive ion etching.

Abstract: An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more masks, manipulating the beam line of an ion implant tool, moving a workpiece relative to the ion beam, or the like. The dose can vary as a function of distance from the center of the workpiece or vary locally based on the design of the electronic device or desires of the electronic device fabricator. In one embodiment, the impurity can be implanted in such a way as to result in a more uniform SiGe condensation across the substrate or across one or more portions of the substrate when the semiconductor layer includes a SiGe layer.

Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Abstract: A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O2 gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Abstract: A single substrate reactor system for processing batches of product substrates one at a time is provided with at least one dummy substrate. In the time after one batch of product substrates is processed and before another batch of product substrates is ready for processing, the dummy substrate is used as a substitute for the thermal load presented by a product substrate. The dummy substrate is loaded into and unloaded from the reactor in the same manner as a batch of product substrates. Advantageously, the thermal load presented by the dummy substrate maintains the thermal equilibrium established during the processing of a batch of product substrates, thereby eliminating the need for and time required to re-establish this equilibrium at the beginning of processing the next batch of substrates.

Abstract: A fiber mat comprises fibers; a resinous fiber binder; and a binder modifier which is a methacrylate/C1-2 succinate/hydroxyacrylate copolymer.

Abstract: An optical glass wherein an amount of change in refractive index (?n: difference in refractive index between a state before radiation and a state after radiation) caused by radiation of laser beam at wavelength of 351 nm having average output power of 0.43W, pulse repetition rate of 5 kHz and pulse width of 400 ns for one hour is 5 ppm or below is provided. The optical glass comprises a fluorine ingredient and/or a titanium oxide ingredient and/or an arsenic oxide ingredient. The optical glass suffers little change in refractive index by radiation of strong light having wavelengths of 300 nm to 400 nm such as ultraviolet laser.

Abstract: The borosilicate glass of the invention is highly resistant to solarization, because it is free of CeO2. Also it contains 0.01 to 0.05 wt. % of Fe2O3 and 0.05 to 0.8 wt. % of TiO2. This borosilicate glass is especially advantageous for production of flash tubes, gas discharge lamps, and fluorescent tubes for brake lights and display backlights.

Abstract: A ceramic body, as well as a method of making the ceramic body, wherein in one aspect a hot-pressing method is used to produce the ceramic body. In another aspect, a sintering to full density method is used to produce the ceramic body. The hot-pressed ceramic body contains between about 15 volume percent and about 35 volume percent of a boron carbide phase and at least about 50 volume percent of alumina, and the substrate has a fracture toughness (KIC, 18.5 Kg Load E&C) greater than or equal to about 4.5 MPa·m0.5. The sintered to full density ceramic body contains between about 15 volume percent and about 50 volume percent of a boron carbide irregular-shaped phase and at least about 50 volume percent alumina.

Abstract: This invention relates to transition metal catalyst compounds represented by the formula: LMX2 wherein M is a Group 7 to 11 metal; L is a tridentate or tetradentate neutrally charged ligand that is bonded to M by least three or four nitrogen atoms, and at least one terminal nitrogen atom is part of a pyridinyl ring, a different terminal nitrogen atom is substituted with one C3–C50 hydrocarbyl, and one hydrogen atom or two hydrocarbyls; wherein at least one hydrocarbyl is a C3–C50 hydrocarbyl, and the central nitrogen atom is bonded to at least three different carbon atoms or two different carbon atoms, and one hydrogen atom; X is independently a monoanionic ligand or both X are joined together to form a bidentate dianionic ligand.

Abstract: This invention relates to a catalyst support comprising the result of the combination of: (a) a support comprising hydroxyl groups; (b) a capping agent comprising a boron containing Lewis acid; and (c) an ionic activator, wherein at least some of the capping agent does not form a support bound activator.

Abstract: A method is provided for producing a specific crosscoupling compound and a specific catalyst for producing the compound. The method includes reacting in the presence of a base and a nickel compound catalyst organic halide of the formula n?(R1X1n), wherein R1 is a hydrocarbon group and the ? and ? carbons to X? are sp3 carbon atoms; X1 is a chlorine, bromine, or iodine atoms, and n and n1 and 1 or 2 but not both 2, with a compound having the formula m{R2(BX22)n?} where an R2 is an aryl, heteroaryl, or alkenyl group, and n? is 1 or 2, X2 is independently a hydroxyl group, an alkoxy or arylalkoxy group or X22 together form an alkylenedioxy or arylenedioxy group, and m represents 1 or 2 but m?n, and the boron atom is bonded to a sp2 carbon atom of R2 group or a boronic acid trimer anhydride.

Abstract: A crystalline alpha-chromium oxide where from about 0.05 atom % to about 6 atom % of the chromium atoms in the alpha-chromium oxide lattice are replaced by trivalent cobalt (Co+3) atoms is disclosed. Also disclosed is a chromium-containing catalyst composition comprising as a chromium-containing component the crystalline cobalt-substituted alpha-chromium oxide; and a method for preparing a composition comprising the crystalline cobalt-substituted alpha-chromium oxide. The method involves (a) co-precipitating a solid by adding ammonium hydroxide to an aqueous solution of a soluble cobalt salt and a soluble trivalent chromium salt that contains at least three moles of nitrate per mole of chromium in the solution and has a cobalt concentration of from about 0.

Abstract: A catalyst for the hydrogenation of C4-dicarboxylic acids and/or their derivatives, preferably maleic anhydride, in the gas phase comprises from 5 to 100% by weight, preferably from 40 to 90% by weight, of copper oxide and from 0 to 95% by weight, preferably from 10 to 60% by weight, of one or more metals or compounds thereof selected from the group consisting of Al, Si, Zn, Pd, La, Ce, the elements of groups III A to VIII A and groups I A and II A as active composition applied in the form of a thin layer to an inert support material.

Abstract: A method for producing a composite oxide catalyst for gas phase catalytic oxidation of an unsaturated aldehyde with a molecular oxygen-containing gas to produce the corresponding unsaturated carboxylic acid in good yield, is presented. A method for producing a composite oxide catalyst, which is a method for producing a composite oxide catalyst having the following formula (I), characterized in that Sb2O3 of isometric system is used as at least a part of an antimony-supplying source compound: Mo12XaVbSbcCudSieCfOg ??(I) (wherein the respective components and variables have the following meanings: X is at least one element selected from the group consisting of Nb and W; a, b, c, d, e, f and g represent atomic ratios of the respective elements, and against 12 of molybdenum atom, 0<a?10, 0<b?10, 0<c?5, 0<d?5, 0?e?1,000, and 0?f?1,000, and g is a number determined by the degrees of oxidation of the above respective components.

Abstract: A method of reducing nematode-fungal interaction in a plant by treating a propagation material thereof with a nematicidally effective amount of a nematicide, and a fungicidally effective amount of a fungicide before the material is planted or sown.

Abstract: A 4-methoxymethyl-2,3,5,6-tetrafluorobenzyl 2,2-dimethyl-3-(2-cyano-3-hydrocarbyloxy-3-oxo-1-propenyl) cyclopropanecarboxylate given by the formula (1): wherein G represents C1–C4 alkyl or C3–C4 alkenyl, has excellent pests controlling effect.

Abstract: Nanoscale chemicals based on polyhedral oligomeric silsesquioxanes (POSS) and polyhedral oligomeric silicates (POS) are taught as lubricants, mold release agents, and as additives to control the viscosity, lubrication, wear, and thermal properties of conventional lubricous materials. The precisely defined nanoscopic dimensions of POSS materials enable viscosity, miscibility, and thermal properties to be (increased) or reduced (decreased) as desired. A key feature to the successful tailoring of properties is the inherent thermal and chemical stability of the POSS/POS nanostructure and the ability to control its topology and chemical potential to match that of surfaces and other materials.

Abstract: The invention relates to a method for cleaning a contaminated medical instrument including the step of immersing the instrument in a solution containing an enzyme based cleaning composition including a “hospital grade disinfectant”. Compositions useful for cleaning contaminated medical instruments in accordance with the method include an enzyme, a quat biocide and an “activity protector”, which may be for example, enzyme stabilizers, enzyme stabilizing systems, micelle formation modifiers and inhibitors, and combinations thereof.

Abstract: A method of treating the surfaces of medical instruments which are contaminated with prions includes contacting the surface with a composition containing a source of peroxide ions, such as hydrogen peroxide, at a molar concentration of at least 1.5M peroxide (equivalent to approximately 5% hydrogen peroxide) and preferably, about 2M peroxide (approximately 7% hydrogen peroxide). The composition is optionally in the form of a gel. The composition is retained in contact with the surfaces for about 1–2 hours until all or substantially all prion contamination is removed.

Abstract: A DNA sequence coding for oncofetal ferritin 1 (OFF1) as well as an amino acid sequence encoded by the DNA sequence. Pharmaceutical compositions may be prepared comprising the above-sequences for treating various diseases, for facilitating transplantations and for treating pathological pregnancies.

Abstract: The invention relates to the use of osteopontin, or of an agonist of osteopontin activity, for treatment or prevention of a neurologic diseases.

Abstract: The invention provides isolated agents having novel chemical structures and possessing superior activity as derepressors of IAP inhibited caspase. The invention further provides a method of derepressing an IAP-inhibited caspase. The invention further provides assay methods employing labeled compounds of the invention, especially fluorescent labeled compounds.

Abstract: Erythropoietin analogs having at least one additional site for glycosylation, or a rearrangement of at least one site for glycosylation are disclosed. The invention also relates to DNA sequences encoding said erythropoietin analogs, and recombinant plasmids and host cells for analog expression.

Abstract: The present invention provides methods of using small cyclic peptides that can inhibit or prevent skin irritation caused by proteolytic activity.

Abstract: Purified BMP-2 and BMP-4 proteins and processes for producing them are disclosed. The proteins may be used in the treatment of bone and cartilage defects and in wound healing and related tissue repair.

Abstract: The present invention relates to complexes of the FOXC2 protein with other proteins, in particular complexes of FOXC2 with proteins designated p621, NOLP, HSC71, FTP3, CLH1, and Kinase A Anchor Protein 84/149 (AKAP). The protein complexes can be used in methods of identifying agents useful for the treatment of medical conditions that can be treated by modulated FOXC2 activity, such as obesity, hypertriglyceridemia, diet-induced insulin resistance, and/or type 2 diabetes.